Lower Power Synthesis1999. 8
http://vada.skku.ac.kr
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System Partitioning
To decide which components of the system will be realized in hardware and which will be implemented in software
High-quality partitioning is critical in high-level synthesis. To be useful, high-level synthesis algorithms should be able to handle very large systems. Typically, designers partition high-level design specifications manually into procedures, each of which is then synthesized individually. Different partitionings of the high-level specifications may produce substantial differences in the resulting IC chip areas and overall system performance.
To decide whether the system functions are distributed or not. Distributed processors, memories and controllers can lead to significant power savings. The drawback is the increase in area. E.g., a non-distributed and a distributed design of a vector quantizer.
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Circuit Partitioning
account by letting the weight of a node (i,j)
in Nc be the sum of the weights of the
nodes I and j. We can similarly take edge
weights into account by letting the weight
of an edge in Ec be the sum of the weights
of the edges "collapsed" into it.
Furthermore, we can choose the edge (i,j)
which matches j to i in the construction of
Nc above to have the large weight of all
edges incident on i; this will tend to
minimize the weights of the cut edges. This
is called heavy edge matching in METIS,
and is illustrated on the right.
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Multilevel Kernighan-Lin
Given a partition (Nc+,Nc-) from step (2) of Recursive_partition, it is easily expanded to a partition (N+,N-) in step (3) by associating
with each node in Nc+ or Nc- the nodes of N that comprise it. This is again shown below:
Finally, in step (4) of Recurive_partition, the approximate partition from step (3) is improved using a variation of Kernighan-Lin.
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WRITE VHDL
Minimizing switching activity in Register
Minimizing switching activity in resource and interconnection
LOW POWER AND FAST SCHEDULING
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Instructions
Operations
Variables
Arrays
signals
@(posedge clk);
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High-Level Synthesis
The allocation task determines the type and quantity of resources used in the RTL design. It also determines the clocking scheme, memory hierarchy and pipelining style. To perform the required trade-offs, the allocation task must determine the exact area and performance values.
The scheduling task schedules operations and memory references into clock cycles. If the number of clock cycles is a constraint, the scheduler has to produce a design with the fewest functional units
The binding task assigns operations and memory references within each clock cycle to available hardware units. A resource can be shared by different operations if they are mutually exclusive, i.e. they will never execute simultaneously.
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Sibling [ Fang , 96 ]
correlation resource sharing [ Gebotys, 97 ]
FU shut down (Demand-driven operation) [ Alidina, 94 ]
[ Rabaey, 96 ]
Dual [ Sarrafzadeh, 96 ]
Spurious [ Hwang, 96 ]
+ [Cho,97]
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+1
+2
+3
*1
a
b
c
d
e
g
f
h
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where PREG is the power of the registers
PMUX is the power of multiplexers
PFU is the power of functional units
PINT is the power of physical interconnet capacitance
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High-Level Power Estimation: PREG
Compute the lifetimes of all the variables in the given VHDL code.
Represent the lifetime of each variable as a vertical line from statement i through statement i + n in the column j reserved for the corresponding varibale v j .
Determine the maximum number N of overlapping lifetimes computing the maximum number of vertical lines intersecting with any horizontal cut-line.
Estimate the minimal number of N of set of registers necessary to implement the code by using register sharing. Register sharing has to be applied whenever a group of variables, with the same bit-width b i .
Select a possible mapping of variables into registers by using register sharing
Compute the number w i of write to the variables mapped to the same set of registers. Estimate n i of each set of register dividing w i by the number of statements S: i =wi/S; hence TR imax = n i f clk .
Power of latches and flip flops is consumed not only during output transitions, but also during all clock edges by the internal clock buffers
The non-switching power PNSK dissipated by internal clock buffers accounts for 30% of the average power for the 0.38-micron and 3.3 V operating system.
In total,
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PCNTR
After scheduling, the control is defined and optimized by the hardware mapper and
further by the logic synthesis process before mapping to layout.
Like interconnect, therefore, the control needs to be estimated statistically.
Local control model: the local controller account for a larger percentage of the total capacitance than the global controller.
Where Ntrans is the number of tansitions, Nstates is the number of states, Clc is the capacitance switched in any local controller in one sample period and Bf is the ratio of the number of bus accesses to the number of busses.
Global control model
Ntrans
The number of transitions depends on assignment, scheduling, optimizations, logic optimization, the standard cell library used, the amount of glitchings and the statistics of the inputs.
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(a)
(b)
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The coarse-grained model provides a fast estimation of the power consumption when
no information of the activity of the input data to the functional units is available.
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Fine-grained model
When information of the activity of the input data to the functional units is available.
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of an 8 X 8-bit Booth multiplier.
AHD
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Loop Interchange
If matrix A is laid out in memory in column-major form, execution
order (a.2) implies more cache misses than the execution order in (b.2).
Thus, the compiler chooses algorithm (b.1) to reduce the running time.
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Motion Estimation
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Retiming
Flip- flop insertion to minimize hazard activity moving a flip- flop in a circuit
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power reduction
By sampling a steady state signal at a register input,
no more glitches are propagated through the next
combinational logics.
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Common patterns enable the design of less complex architecture and therefore simpler interconnect structure (muxes, buffers, and buses). Regular designs often have less control hardware.
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Module Selection
Select the clock period, choose proper hardware modules for all operations(e.g., Wallace or Booth Multiplier), determine where to pipeline (or where to put registers), such that a minimal hardware cost is obtained under given timing and throughput constraints.
Full pipelining: ineffective clock period mismatches between the execution times of the operators. performing operations in sequence without immediate buffering can result in a reduction of the critical path.
Clustering operations into non-pipelining hardware modules, the reusability of these modules over the complete computational graph be maximized.
During clustering, more expensive but faster hardware may be swapped in for operations on the critical path if the clustering violates timing constraints
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Estimate min and max bounds on the required resources to
delimit the design space min bounds to serve as an initial solution
serve as entries in a resource utilization table which guides the transformation, assignment and scheduling operations
Max bound on execution time is tmax: topological ordering of DFG using ASAP and ALAP
Minimum bounds on the number of resources for each resource class
Where NRi: the number of resources of class Ri
dRi : the duration of a single operation
ORi : the number of operations
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Find the minimal area solution constrained to the timing constraints
By checking the critical paths, it determine if the proposed graph violates the timing constraints. If so, retiming, pipelining and tree height reduction can be applied.
After acceptable graph is obtained, the resource allocation process is
initiated.
transform the graph to reduce the hardware requirements.
Use a rejectionless probabilistic iterative search technique (a variant of Simulated Annealing), where moves are always accepted. This approach reduces computational complexity and gives faster convergence.
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Scheduling and Binding
The scheduling task selects the control step, in which a given operation will happen, i.e., assign each operation to an execution cycle
Sharing: Bind a resource to more than one operation.
Operations must not execute concurrently.
Graph scheduled hierachically in a bottom-up fashion
Power tradeoffs
Schedule directly impacts resource sharing
Energy consumption depends what the previous instruction was
Reordering to minimize the switching on the control path
Clock selection
Eliminate slacks
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ASAP Scheduling
Mechanical analogy:
Probability of scheduling operations into control steps
Probability of scheduling operations into control steps after operation o3 is scheduled to step s2
Operator cost for multiplications in a
Operator cost for multiplications in c
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ready operation list/resource constraint
Priority list
Decompose a computation into strongly connected components
Any adjacent trivial SCCs are merged into a sub part;
Use pipelining to isolate the sub parts;
For each sub part
If (the sub part is linear)
Apply optimal unfolding;
Merge linear sub parts to further optimize;
Schedule merged sub parts to minimize memory usage
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SCC decomposition step
Using the standard depth-first search-based algorithm [Tarjan,1972] which has a low order polynomial-time complexity. For any pair of operations A and B within an SCC, there exist both a path from A to B and a path from B to A. The graph formed by all the SCCs is acyclic. Thus, the SCCs can be isolated from each other using pipeline delays, which enables us to optimize each SCC separately.
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Idetifying SCC
The first step of the approach is to identify the computation's strongly connected components,.
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Pipeline operations inside a loop.
Overlap execution of operations.
Use pipeline scheduling for loop graph model.
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DFG Restructuring
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Control Synthesis
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Optimum binding
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Resource sharing can destroy signal correlations and increase switching activity, should be done between operations that are strongly connected.
Map operations with correlated input signals to the same units
Regularity: repeated patterns of computation (e.g., (+, * ), ( * ,*), (+,>)) simplifying interconnect (busses, multiplexers, buffers)
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Datapath interconnections
Multiplexer-oriented datapath
Bus-oriented datapath
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Insertion of Latch (out)
Insertion of latches at the output ports of the functional units
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Insertion of Latch (in/out)
Insertion of latches at both the input and output ports of the functional units
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Overlapping data transfer with functional-unit execution
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Scheduled DFG
Graph model
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Register Allocation
Allocation : bind registers and functional modules to variables and operations in the CDFG and specify the interconnection among modules and registers in terms of MUX or BUS.
Reduce capacitance during allocation by minimizing the number of functional modules, registers, and multiplexers.
Register allocation and variable assignment can have a profound impact on spurious switching activity in a circuit
Judicious variable assignment is a key factor in the elimination of spurious operations
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Effect of Register Sharing on FU
For a small increase in the number of registers, it is possible to significantly reduce or eliminate spurious operations
For Design 1, synthesized from Assignment 1, the power consumption was 30.71mW
For Design 2, synthesized from Assignment 2, the power consumption was 18.96mW @1.2-m standard-cell library
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Operand sharing
To schedule and bind operations to functional units in such a way that the activity of the input operands is reduced.
Operations sharing the same operand are bound to the same functional unit and scheduled in such a way that the function unit can reuse that operand.
we will call operand reutilization (OPR) the fact that an operand is reused by two operations consecutively executed in the same functional unit.
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Loop unrolling
The technique of loop unrolling replicates the body of a loop some number of times (unrolling factor u) and then iterates by step u instead of step 1. This transformation reduces the loop overhead, increases the instruction parallelism and improves register, data cache or TLB locality.
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Loop Unrolling Effects
Loop overhead is cut in half because two iterations are performed in each iteration.
If array elements are assigned to registers, register locality is improved because A(i) and A(i +1) are used twice in the loop body.
Instruction parallelism is increased because the second assignment can be performed while the results of the rst are being stored and the loop variables are being updated.
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Loop Unrolling (IIR filter example)
loop unrolling : localize the data to reduce the activity of the inputs of the functional units or two output samples are computed in parallel based on two input samples.
Neither the capacitance switched nor the voltage is altered. However, loop unrolling enables several other transformations (distributivity, constant propagation, and pipelining). After distributivity and constant propagation,
The transformation yields critical path of 3, thus voltage can be dropped.
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obtaining a reduction of 9.4%.
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Operand Retaining
An idle functional unit may have input operand changes because of the variation of the selection signals of multiplexers.
The operand-retaining technique attempts to minimize the useless power consumption of the idle functional units.
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Minimize the useless power consumption of idle units
(a) with a proper register binding that minimizes the activity of the functional units
(b) by wisely defining the control signals of the multiplexors during the idle cycles in such a way that the changes at the inputs of the functional units are minimized (this may result in defining some of the don't care values of the control signals) [RJ94]
(c) latching the operands of those units that will be often idle.
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(C) latching the operands
It consists of the insertion of latches at the inputs of the functional units to store the operands only when the unit requires them. Thus, in those cycles in which the unit is idle no consumption in produced.
The control unit has to be redesigned accordingly, in such a way that input latches become transparent during those cycles in which the corresponding functional unit must execute an operation.
Similar to putting the functional units to sleep when they are not needed through gated-clocking strategies [CSB94,BSdM94, AMD94].
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LMS filter Example
The power consumption generated by the idle units (useless consumption) is:
the power consumption because of the useful calculations (useful consumption) is:
The estimated reduction in power consumption is:
reduction of 34%.
interconnect power reduction
A spatially local cluster: group of algorithm operations that are tightly connected to each other in the flowgraph representation.
Two nodes are tightly connected to each other on the flowgraph representaion if the shortest distance between them, in terms of number of edges traversed, is low.
A spatially local assignment is a mapping of the algorithm operations to specific hardware units such that no operations in different clusters share the same hardware.
Partitioning the algorithm into spatially local clusters ensures that the majority of the data transfers take place within clusters (with local bus) and relatively few occur between clusters (with global bus).
The partitioning information is passed to the architecture netlist and floorplanning tools.
Local: A given adder outputs data to its own inputs Global: A given adder outputs data to the aother adder's inputs
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Hardware Mapping
The last step in the synthesis process maps the allocated, assigned and scheduled flow graph (called the decorated flow graph) onto the available hardware blocks.
The result of this process is a structural description of the processor architecture, (e.g., sdl input to the Lager IV silicon assembly environment).
The mapping process transforms the flow graph into three structural sub-graphs:
the data path structure graph
the controller state machine graph
the interface graph (between data path control inputs and the
controller output signals)
Spectral Partitioning in High-Level Synthesis
The eigenvector placement obtained forms an ordering in which nodes tightly connected to each other are placed close together.
The relative distances is a measure of the tightness of connections.
Use the eigenvector ordering to generate several partitioning solutions
The area estimates are based on distribution graphs.
A distribution graph displays the expected number of operations executed in each time slot.
Local bus power: the number of global data transfers times the area of the cluster
Global bus power: the number of global data transfer times the total area:
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Interconnection Estimation
For connection within a datapath (over-the-cell routing), routing between units increases the actual height of the datapath by approximately 20-30% and that most wire lengths are about 30-40% of the datapath height.
Average global bus length : square root of the estimated chip area.
The three terms represent white space, active area of the components, and wiring area. The coefficients are derived statistically.
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Datapath Generation
Register file recognition and the multiplexer reduction:
Individual registers are merged as much as possible into register files
reduces the number of bus multiplexers, the overall number of busses (since all registers in a file share the input and output busses) and the number of control signals (since a register file uses a local decoder).
Minimize the multiplexer and I/O bus, simultaneously (clique partitioning is Np-complete, thus Simulated Annealing is used)
Data path partitioning is to optimize the processor floorplan
The core idea is to grow pairs of as large as possible isomorphic regions from corresponding of seed nodes.
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( input ) : V,
( output ) : V
Cij=1, Bij=L
Cij=1, Bij=W
Wa :
N :
M : Wa * N
L : W
V : )
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Minimize Z=

1 : flow = 0;
2 : Bij* .
3 : 2 S T flow .
= min (1, 2)
2 = min{Xij}
4: 2 .
5: V .
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PATH 2 : S-b-T REG2 : b
PATH 3 : S-c-g-T REG3 : c, g
PATH 4 : S -d-T REG4 : d
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(a,e) +(b, b),
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( input ) : V, Network for resource sharing
(output ) : V
Cij=1, Bij=L
Cij=1, Bij=W
Wmux :
K :


V :
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PATH 2 :
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CDFG
exclusive-OR
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,
15%

(polynomial time and optimal solution algorithm)
TOP-DOWN
(DSP, Microcontroller, ASIC, etc)
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Programmable DSP bit-swapping .
DSP / .
ALU
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Bus switchings/transition bus-based system power dissipation . off-chip power consumption chip power 70%
CPU ALU Datapath . ALU bus signal transition bus ALU
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mux-in1
reg-in1
mux-in2
reg-in2
reg-in3
ALU
databus-in1
databus-in2
C1 = Y1(A2) EXOR Y2(B2)
bit-wise swapping a bit inY2(A2) and a bit in Y2(B2) when a bit in C1 is “1”
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simulation testvector test.
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[6] Y. Fang and A. Albicki, "Joint scheduling and allocation for low power," in Proc. of Int'l Symp. on Circuits & Systems, pp. 556-559, May. 1996.
[7] J. Monteiro and Pranav Ashar, "Scheduling techniques to enable power management", 33rd Design Automation Conference, 1996.
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