ltc3734 - single-phase, high efficiency dc/dc controller ...€¦ · ltc3734 1 3734fa typical...
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LTC3734
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Single-Phase, High Efficiency DC/DC
Controller for Intel Mobile CPUs
The LTC®3734 is a single-phase synchronous step-down switching regulator controller that drives all N-channel power MOSFETs in a constant frequency architecture. The output voltage is programmable by six VID bits during normal operation and by external resistors during initial boot-up and deeper sleep state. The LTC3734 drives its output stage at frequencies up to 550kHz. Powerful on-chip gate drivers eliminate the need for external gate driver ICs, thus simplifying the design.
An Intel compatible PSIB input is provided to select between two modes of operation. Fully enhanced synchronous mode achieves a very small output ripple and very fast transient response while power saving mode realizes very high efficiency. OPTI-LOOP® compensation allows the transient response to be optimized for a wide range of output capacitance and ESR values.
The LTC3734 is available in a small 5mm × 5mm QFN package. For 2-phase applications refer to the LTC3735.
APPLICATIONS
n Wide Input Voltage Range: 4V to 30V ±1% Output Voltage Accuracy 6-Bit IMVP-IV VID Code: VOUT = 0.7V to 1.708V Intel Compatible Power Saving Mode (PSIB) Power Good Output with Adaptive Masking Lossless Voltage Positioning Resistor Programmable VOUT at Boot-Up and
Deeper Sleep State Resistor Programmable Deep Sleep Offset Programmable Fixed Frequency: 210kHz to 550kHz Adjustable Soft-Start Current Ramping Foldback Output Current Limit Short-Circuit Shutdown Timer with Defeat Option Overvoltage Protection Available in 32-Lead 5mm × 5mm × 0.8mm (Profile)
QFN Package
n Mobile and Desktop Computers Internet Servers L, LT, LTC, LTM, OPTI-LOOP, Burst Mode, Linear Technology and the Linear logo are registered
trademarks and Stage Shedding is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
0.8µHM1
M2 D1
0.002Ω
12.7k
COUT270µF2V×3
VOUT0.7V TO 1.708V20A
VIN5V TO 24V
13.3k
1.27M
1.27M
3734 F01
56.2k
13.3k
TGMCH_PG
DPRSLPVR
STP_CPUB
PSIB
FREQSET
VID5-VID0
PGOOD
ITH
SGND
RUN/SS
CC680pF
100pF0.1µF
0.47µF
4.5V TO 7V
RC3k
SW
BG
PGND
SENSE+
SENSE–
RBOOT
RDPRSLP
RDPSLP
OAOUT
VOA+
VOA–
CIN10µF35V×4
BAT54A
SW
PVCC
BOOST SVCC
4.7µF
+
0.1µF4.5V TO 7V
6-BIT VID
LTC3734
Figure 1. High Current Step-Down Converter
LTC3734
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ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (PVCC, SVCC) ............. 7V to –0.3V Topside Driver Voltages (BOOST) .............. 38V to –0.3VSwitch Voltage (SW) ..................................... 32V to –5VBoosted Driver Voltages (BOOST-SW) ......... 7V to –0.3VDPRSLPVR, STP_CPUB, MCH_PG, PGOOD, RDPRSLP, RDPSLP, RBOOT Voltages ......... 5V to –0.3VRUN/SS, FREQSET, PSIB Voltages ..............7V to –0.3VVID0-VID5 Voltages ....................................5V to –0.3VVFB Voltage ................................................. 2V to –0.3VVOA
+, VOA– Voltage .................................... 3.6V to –0.3V
Peak Gate Drive Current <1µs (TG, BG) ......................5AOperating Ambient Temperature Range(Note 2) ...................................................–40°C to 85°CJunction Temperature (Note 3) ............................. 125°CStorage Temperature Range ................... –65°C to 125°CReflow Peak Body Temperature ............................ 245°C
(Note 1)
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VPVCC = VSVCC = 5V, VRUN/SS = 5V unless otherwise noted.
ORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3734EUH#PBF LTC3734EUH#TRPBF 3734 32-Lead Plastic (5mm × 5mm) QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
PIN CONFIGURATION
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1VOA+
VOA–
OAOUT
STP_CPUB
SGND
SENSE+
SENSE –
RDPRSLP
TG
SW
PVCC
BG
PGND
VID5
VID4
VID3
PSIB
FREQ
SET
DPRS
LPVR
SVCC
V FB
MCH
_PG
PGOO
D
BOOS
T
RDPS
LP
RUN/
SS I TH
RBOO
T
VID0
VID1
VID2 NC
UH PACKAGE32-LEAD (5mm × 5mm) PLASTIC QFN
33
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
Reference Regulated Feedback Voltage ITH Voltage = 0.5V; Measured at VFB (Note 4) 0.600 V
VSENSEMAX Maximum Current Sense Threshold ITH Voltage = Max; VCM = 1.7V l 59 72 85 mV
VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop, ∆ITH Voltage: 1.2V to 0.7V Measured in Servo Loop, ∆ITH Voltage: 1.2V to 2V
l
l
0.1 –0.1
0.5 –0.5
% %
VREFLNREG Reference Voltage Line Regulation VPVCC = VSVCC = 4.5V to 7V 0.02 0.1 %/V
VPSIB Forced Continuous Threshold 0.57 0.6 0.63 V
IPSIB Forced Continuous Current VPSIB = 0V –0.5 –1 µA
VOVL Output Overvoltage Threshold Measured with Respect to VFB = 0.6V 0.64 0.66 0.68 V
gm Transconductance Amplifier gm ITH = 1.2V, Sink/Source 25µA (Note 4) l 4.5 6 7.5 mmho
gmOL Transconductance Amplifier Gain ITH = 1.2V, (gm • ZL; No Ext Load) (Note 4) 3 V/mV
VACTIVE Output Voltage in Active Mode VID = 010110, ITH = 0.5V (0°C – 85°C) VID = 010110, ITH = 0.5V (Note 2)
l
1.342 1.336
1.356 1.356
1.370 1.376
V V
LTC3734
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ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VPVCC = VSVCC = 5V, VRUN/SS = 5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IQ Input DC Supply Current Normal Mode Shutdown
(Note 5) VRUN/SS = 0V
2
20
3
100
mA µA
UVR Undervoltage RUN/SS Reset VCC Lowered Until the RUN/SS Pin is Pulled Low 3.2 3.7 4.2 V
IRUN/SS Soft-Start Charge Current VRUN/SS = 1.9V –2.3 –1.5 –0.8 µA
VRUN/SS RUN/SS Pin ON Threshold VRUN/SS Rising 1.0 1.5 1.9 V
VRUN/SSARM RUN/SS Pin Latchoff Arming VRUN/SS Rising from 3V 3.9 V
VRUN/SSLO RUN/SS Pin Latchoff Threshold VRUN/SS Ramping Negative 3.2 V
ISCL RUN/SS Discharge Current Soft Short Condition VFB = 0.375V, VRUN/SS = 4.5V –5 –1.5 µA
ISDLHO Shutdown Latch Disable Current VFB = 0.375V, VRUN/SS = 4.5V 1.5 5 µA
ISENSE Total Sense Pins Source Current VSENSE– = VSENSE
+ = 0V –85 –60 µA
DFMAX Maximum Duty Factor In Dropout 95 98.5 %
TG tr TG tf
Top Gate Transition Time: Rise Time Fall Time
(Note 6) CLOAD = 3300pF CLOAD = 3300pF
30 40
90 90
ns ns
BG tr BG tf
Bottom Gate Transition Time: Rise Time Fall Time
(Note 6) CLOAD = 3300pF CLOAD = 3300pF
60 50
90 90
ns ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time
CLOAD = 3300pF (Note 6) 50 ns
BG/TG t2D Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time
CLOAD = 3300pF (Note 6) 60 ns
tON(MIN) Minimum On-Time Tested with a Square Wave (Note 7) 100 ns
VID Parameters
RATTEN VID Top Resistance 5.33 kΩ
ATTENERR Resistive Divider Error (Note 8) l –0.25 0.25 %
VIDTHLOW VID0 to VID5 Logic Threshold Low 0.3 V
VIDTHHIGH VID0 to VID5 Logic Threshold High 0.7 V
VIDLEAK VID0 to VID5 Leakage ±1 µA
Oscillator
IFREQSET FREQSET Input Current VFREQSET = 0V –2 –1 µA
fNOM Nominal Frequency VFREQSET = 1.2V 320 355 390 kHz
fLOW Lowest Frequency VFREQSET = 0V 190 210 240 kHz
fHIGH Highest Frequency VFREQSET ≥ 2.4V 490 550 610 kHz
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA
VPG PGOOD Trip Level VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive
–7 7
–10 10
–13 13
% %
tMASK PGOOD Mask Timer 100 110 120 µs
tDELAY MCH_PG Delay Time 15 cycles
LTC3734
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TYPICAL PERFORMANCE CHARACTERISTICS
Active Mode Efficiency (VID = 1.186V, PSI = 0) (Figure 9)
Deeper Sleep Mode Efficiency(Figure 9)
Efficiency vs Input Voltage(Figure 9)
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VPVCC = VSVCC = 5V, VRUN/SS = 5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Operational Amp
IB Input Bias Current 15 200 nA
VOS Input Offset Voltage Magnitude VOA+ = VOA
– 1.2V, IOUT = 1mA 0.8 5 mV
CM Common Mode Input Voltage Range 0 PVCC – 1.4 V
CMRR Common Mode Rejection Ratio IOUT = 1mA 46 70 dB
ICL Output Source Current 10 35 mA
AVOL Open-Loop DC Gain IOUT = 1mA 30 V/mV
GBP Gain-Bandwidth Product IOUT = 1mA 2 MHz
SR Slew Rate RL = 2k 5 V/µs
VO(MAX) Maximum High Output Voltage IOUT = 1mA PVCC – 1.2 PVCC – 0.9 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The LTC3734E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls.Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3734EUH: TJ = TA + (PD • 34°C/W)Note 4: The LTC3734 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VFB.
Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information.Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels.Note 7: The minimum on-time condition corresponds to the on inductor peak-to-peak ripple current ≥40% IMAX (see Minimum On-Time Considerations in the Applications Information section).Note 8: The ATTENERR specification is in addition to the output voltage accuracy specified at VID code = 010110.
IOUT (A)0
EFFI
CIEN
CY (%
)
8
3735 GO1
2 4 6 10
100
90
80
70
60
VIN = 7.5V
VIN = 20V
90
80
70
60
IOUT (A)0.01
EFFI
CIEN
CY (%
)
3734 G02
0.1 1 10
VIN = 7.5V
VIN = 20V
INPUT VOLTAGE (V)5
EFFI
CIEN
CY (%
)
70
80
3734 G03
60
5010 15 20
100
90
IOUT = 20AVOUT = 1.6V
LTC3734
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TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense Threshold vs VRUN/SS (Soft-Start)
Maximum Current Sense Threshold vs Sense Common Mode Voltage
Current Sense Thresholdvs ITH Voltage
Load Regulation (without AVP) SENSE Pins Total Source Current
Supply Current vs SVCC Voltage and Mode
Maximum Current Sense Threshold vs Duty Factor
Maximum Current Sense Threshold vs Percent of Nominal Output Voltage (Foldback)
SVCC VOLTAGE (V)4
0
SUPP
LY C
URRE
NT (µ
A)
1000
2500
6
3734 G04
500
2000
1500
5 7
ON
SHUTDOWN
DUTY FACTOR (%)0
0
V SEN
SE (m
V)25
50
75
20 40 60 80
3734 G05
100PERCENT OF NOMINAL OUTPUT VOLTAGE (%)
0
V SEN
SE (m
V)
40
50
60
100
3734 G06
30
20
025 50 75
10
80
70
VRUN/SS (V)0
0
V SEN
SE (m
V)
20
40
60
80
10
30
50
70
1 2 3 4
3734 G07
5
VSENSE(CM) = 1.25V
COMMON MODE VOLTAGE (V)0
V SEN
SE (m
V)
76
72
68
64
604
3734 G08
1 2 3 5VITH (V)
0
V SEN
SE (m
V)
30
50
70
90
2
3734 G09
10
–10
20
40
60
80
0
–20
–300.5 1 1.5 2.5
LOAD CURRENT (A)0
NORM
ALIZ
ED V
OUT
(%)
–0.2
–0.1
20
3734 G10
–0.3
–0.45 10 15 25
0.0VPSIB = 5VVIN = 15VFIGURE 1
VSENSE COMMON MODE VOLTAGE (V)0
I SEN
SE (µ
A)
0
3734 G12
–50
–1002 4
50
100
6
LTC3734
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TYPICAL PERFORMANCE CHARACTERISTICS
Current Sense Pin Input Current vs Temperature
Oscillator Frequencyvs Temperature
VRUN/SS Shutdown Latch Thresholds vs Temperature
Maximum Current SenseThreshold vs Temperature RUN/SS Current vs Temperature Load Step (Figure 9)
TEMPERATURE (°C)–50 –25
V SEN
SE (m
V)
0 50 75
3734 G13
78
76
74
72
70
6825 100 125
TEMPERATURE (°C)–50 –25
0
RUN/
SS C
URRE
NT (µ
A)
0.2
0.6
0.8
1.0
75 10050
1.8
3734 G14
0.4
0 25 125
1.2
1.4
1.6
1530 G15
VOUT100mV/DIV
IOUT4A/DIV
20µs/DIV
1.2V
1.116V
12A
2.5A
TEMPERATURE (°C)–50 –25
–7
CURR
ENT
SENS
E IN
PUT
CURR
ENT
(µA)
–9
–12
0 50 75
3734 G16
–8
–11
–10
25 100 125
VOUT = 1.6V
TEMPERATURE (°C)–50
700
600
500
400
300
200
10025 75
3734 G17
–25 0 50 100 125
FREQ
UENC
Y (k
Hz)
VFREQSET = 2.4V
VFREQSET = 1.2V
VFREQSET = 0V
TEMPERATURE (°C)–50 –25
0
SHUT
DOW
N LA
TCH
THRE
SHOL
DS (V
)
0.5
1.5
2.0
2.5
75 10050
4.5
3734 G19
1.0
0 25 125
3.0
3.5
4.0 LATCH ARMING
LATCHOFFTHRESHOLD
LTC3734
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PIN FUNCTIONSVOA
+, VOA– (Pins 1, 2): Inputs to the Internal Operational
Amplifier.
OAOUT (Pin 3): Output of the Internal Operational Amplifier.
STP_CPUB (Pin 4): Deep Sleep State Input. When the signal to this pin is low, the voltage regulator enters deep sleep state and its output voltage is a certain percentage lower than the VID commands. This offset percentage is set by the resistor connected to the RDPSLP pin. When the signal to this pin is high, the voltage regulator exits deep sleep state.
SGND (Pin 5): Signal Ground. All small-signal components and compensation components should connect to this ground which, in turn, connects to PGND at one point.
SENSE+ (Pin 6): The (+) Input to the Differential Current Comparator. The ITH pin voltage and built-in offsets between SENSE– and SENSE+ pins in conjunction with RSENSE set the current trip threshold.
SENSE– (Pin 7): The (–) Input to the Differential Current Comparator.
RDPRSLP (Pin 8): Deeper Sleep State Resistor Pin. Connect a resistor from this pin to VOA
+. This resistor in conjunc-tion with the RDPSLP resistor sets the output voltage of the regulator in deeper sleep state.
RDPSLP (Pin 9): Deep Sleep Resistor Pin. Connect a resis-tor from this pin to VOA
+. This resistor sets the percentage offset of output voltage in deep sleep state.
RUN/SS (Pin 10): Combination of Soft-Start, Run Control Input and Short-Circuit Detection Timer. A capacitor to ground at this pin sets the ramp time to full current output. Forcing this pin below 1V causes the IC to shut down all internal circuitry. All functions are disabled in shutdown.
ITH (Pin 11): Error Amplifier Output and Switching Regulator Compensation Point. The current comparator’s threshold increases with this control voltage. The normal voltage range of this pin is from 0V to 2.4V
RBOOT (Pin 12): Boot-Up Resistor Pin. Connect a resistor from this pin to VOA
+. This resistor sets the output voltage during the initial boot-up.
VID0–VID5 (Pins 13, 14, 15, 17, 18, 19): VID Control Logic Input Pins.
NC (Pin 16): Not Connected.
PGND (Pin 20): Driver Power Ground. Connect to sources of bottom N-channel MOSFETs and the (–) terminals of CIN.
BG (Pin 21): High Current Gate Drive for Bottom N-Channel MOSFETs. Voltage swing at this pin is from ground to PVCC.
PVCC (Pin 22): Power Supply Pin. The on chip gate drivers are powered from this voltage source. Decouple to PGND with a minimum of 4.7µF X5R/X7R ceramic capacitor placed directly adjacent to the IC.
LTC3734
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PIN FUNCTIONSSW (Pin 23): Switch Node Connection to Inductor. Volt-age swing at this pin is from a Schottky diode (external) voltage drop below ground to VIN.
TG (Pin 24): High Current Gate Drive for Top N-Channel MOSFETs. This is the output of a floating driver with a voltage swing equal to PVCC superimposed on the switch node voltage SW.
BOOST (Pin 25): Bootstrapped Supply to the Topside Floating Driver. External capacitor is connected between the BOOST and SW pins, and a Schottky diode is connected between the BOOST and PVCC pins.
PGOOD (Pin 26): Power Good Indicator Output. This pin is open drain when output is within ±10% of its set point. When output is not within the ±10% window, this pin is pulled to ground. An internal timer watches over VID, state transitions, overvoltage or undervoltage conditions, then masks PGOOD from going low for 110µs.
MCH_PG (Pin 27): MCH Power Good Input. Output voltage remains VBOOT for 15 clock cycles after the assertion of MCH_PG. This delay is only sensitive to the rising edge of the MCH_PG logic signal.
VFB (Pin 28): Input to the error amplifier that compares the feedback voltage to the internal 0.6V reference voltage.
SVCC (Pin 29): Signal Power Pin. The internal control circuits are powered from this voltage source.
DPRSLPVR (Pin 30): Deeper Sleep State Input. When the signal to this pin is high, the voltage regulator enters deeper sleep state and its output is determined by the parallel resistor value of RDPRSLP and RDPSLP. When the signal is low, the voltage regulator exits deeper sleep state.
FREQSET (Pin 31): Frequency Set Pin. Apply a DC volt-age between 0V and 5V to set the operating frequency of the internal oscillator. This frequency is the switching frequency of the controller.
PSIB (Pin 32): Power Status Indicator Input. When the signal to this pin is high, the controller operates in fully synchronous switching mode for fastest transient and lowest ripple. When the signal is low, controller enters power saving mode, providing high efficiency at light load.
SGND (Exposed Pad Pin 33): Signal Ground. Must be soldered to the PCB.
LTC3734
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FUNCTIONAL DIAGRAM
SWITCHLOGIC
0.60V
5VSVCC
CLK
+
–VREF
SGND
+
SW
SHDN
TOP
BOOST
TG CB
CIND1
DB
PGND
BOTBG
PVCC
MD
RBOOTDPRSLPVRRDPRSLP
COMPOSITEPG
PVCC
VIN
+
3735 FD
VFB
DROPOUTDET
RUNSOFT-START
BOT PSI
TOP ONS
R
Q
Q
OSCILLATOR
110µs BLANKING
FREQSET
R3
EA
0.66V
1.5V
0.60V
OV
1.5µA
6V
–
+
RC
5.33(VFB)RST
RUN
SHDN
RUN/SS
ITHCC
CSS
5.33(VFB)
SLOPECOMP
+
–
+
–
SENSE–
SENSE+
LSVCC
36k
54k
2.4V
54k
RSENSE
36k
I1 I2
VFB
RATTEN5.33k
RVID
DPRSLPVRMD
VID0
VID CHANGE
VID1 VID2 VID3 VID4 VID5
CC2
+– + –
COUT
VOUT
+
A1
R2
R1
+
–
OAOUT
VOA–
VOA+
0.54V
0.66V
+
–
+
–VFB
PGOOD
RUN
STP_CPUB
–
+
6-BIT VID DECODER
–
+
0.5µA
PSI
3V
PSIB
DPRSLPVRVID CHANGE
DELAY
STP_CPUBRDPSLP
R4 R6 R5
MCH_PG
DPRSLPVR
PVCC
PVCC
LTC3734
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OPERATION (Refer to Functional Diagram)
Main Control Loop
The LTC3734 uses a constant frequency, current mode step-down architecture. During normal operation, the top MOSFET is turned on when the clock sets the RS latch, and turned off when the main current comparator, I1, resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of error amplifier EA. The VFB pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in EA inverting input node relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle.
The top MOSFET driver is biased from a floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external diode when the top MOSFET turns off. As VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 500ns every sixth cycle to allow CB to recharge.
The main control loop is shut down by pulling the RUN/SS pin low. Releasing RUN/SS allows an internal 1.5µA current source to charge soft-start capacitor CSS. When CSS reaches 1.5V, the main control loop is enabled with the internal ITH voltage clamped at approximately 30% of its maximum value. As CSS continues to charge, the internal ITH voltage is gradually released allowing normal, full-current operation.
Frequency Programming
The switching frequency of the LTC3734 is determined by the DC voltage at the FREQSET pin. A DC voltage ranging from 0V to 2.4V moves the internal oscillator frequency from 210kHz to 550kHz.
Low Current Operation (PSIB)
The PSIB pin selects between two modes of operation. When PSIB is above 0.6V, the controller operates in full synchronous switching mode. Bottom driver (BG) is kept on once it is turned on until the oscillator sets the RS latch. The inductor current can therefore go from output back to input power supply and could potentially boost the input supply to dangerous voltage levels—BEWARE! This mode of operation is also of lower efficiency and much current can circulate between input and output. However, this mode provides constant switching frequency.
When PSIB is below 0.6V, the bottom driver (BG) is turned off if the inductor current starts to reverse. This mode of operation prevents current going from output back to input and eliminates the conduction power loss related to circulating current. The circuit may skip switching cycles at very light load conditions.
Output Voltage at Start-Up and at Deeper Sleep State
Under normal conditions, the output voltage of the regula-tor is commanded by six VID bits, except at start-up and at deeper sleep state. At start-up, the RUN/SS capacitor starts to charge up and its voltage limits the inrush current from the input power source. This linearly rising current limit provides a controlled output voltage rise. During start-up, the VID command is ignored and the output set point is determined by the value of the resistor connected to the RBOOT pin. The VID bits continue to be ignored for 15 switching cycles after the completion of the following two conditions: 1) output voltage has risen up and has regulated 2) MCH_PG signal has asserted. After 15 switch-ing cycles, output voltage is fully commanded by VID bits.
In deeper sleep state, the VID command is also ignored and the output set point is determined by the parallel value of the resistors at the RDPRSLP pin and RDPSLP pin.
LTC3734
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OPERATION (Refer to Functional Diagram)
Operational Amplifier and Deep Sleep Offset
The internal operational amplifier provides a programmable output offset at deep sleep state (when the STP_CPUB signal is low). The offset percentage is programmed by the resistor from RDPSLP to VOA
+ and the resistor from output to VOA
+. The amplifier has an output slew rate of 5V/µs and is capable of driving capacitive loads with an output RMS current typically up to 40mA. The open-loop gain of the amplifier is >120dB and the unity-gain band-width is 2MHz.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient overshoots (>10%) as well as other more serious condi-tions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared.
Power Good
The PGOOD pin is connected to the drain of an internal N-channel MOSFET. The MOSFET turns on when the out-put voltage is not within ±10% of its nominal set point. When the output voltage is within ±10% of its nominal set point, the MOSFET turns off and PGOOD is high imped-ance. PGOOD monitors the VBOOT voltage when MCH_PG is not asserted. During VID, deep sleep or deeper sleep
transitions, PGOOD is masked from going low for 110µs, preventing the system from resetting during CPU mode changes. When VID bits, STP_CPUB or DPRSLPVR signals change again after a previous transition, but before the timer expires, the internal timer resets.
Short-Circuit Detection
The RUN/SS capacitor is used initially to limit the inrush current from the input power source. Once the control-ler has been given time, as determined by the capacitor on the RUN/SS pin, to charge up the output capacitors and provide full-load current, the RUN/SS capacitor is then used as a short-circuit timeout circuit. If the out-put voltage falls to less than 70% of its nominal output voltage the RUN/SS capacitor begins discharging as-suming that the output is in a severe overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the size of the RUN/SS capacitor, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overidden by providing a current >5µA to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor dur-ing a severe overcurrent and/or short-circuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled.
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APPLICATIONS INFORMATIONThe basic LTC3734 application circuit is shown in Figure 1 on the first page of this data sheet. External com-ponent selection begins with the selection of the inductors based on ripple current requirements and continues with the current sensing resistors using the calculated peak inductor current and/or maximum current limit. Next, the power MOSFET, D1 is selected. The operating frequency and the inductor are chosen based mainly on the amount of ripple current. Finally, CIN is selected for its ability to handle the input ripple current and COUT is chosen with low enough ESR to meet the output ripple voltage and load step specifications. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs).
RSENSE Selection For Output Current
RSENSE is chosen based on the required peak output cur-rent. The LTC3734 current comparator has a maximum threshold of 72mV/RSENSE and an input common mode range of SGND to SVCC. The current comparator threshold sets the peak inductor current, yielding a maximum aver-age output current IMAX equal to the peak value less half the peak-to-peak ripple current, ∆IL.
Allowing a margin for variations in the LTC3734 and external component values yields:
RSENSE = (40mV/IMAX)
Operating Frequency
The LTC3734 uses a constant frequency architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus an additional current which is proportional to the DC voltage applied to the FREQSET pin. The FREQSET voltage is internally set to 1.2V. It is recommended that this pin is actively biased with a resistor divider to prevent noise getting into the system.
A graph for the voltage applied to the FREQSET pin vs fre-quency is given in Figure 2. As the operating frequency is increased the gate drive and switching losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 550kHz.
Inductor Value Calculation and Output Ripple Current
The operating frequency and inductor selection are inter-related in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because MOSFET gate charge and transition losses increase directly with frequency. In addition to this basic tradeoff, the effect of inductor value on ripple current and low cur-rent operation must also be considered.
The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL, decreases with higher inductance or frequency and increases with higher VIN:
∆IL =
VOUTfL
1−VOUTVIN
where f is the individual output stage operating frequency.
Accepting larger values of ∆IL allows the use of low in-ductances, but can result in higher output voltage ripple. A reasonable starting point for setting ripple current is ∆IL = 0.4(IOUT), where IOUT is the maximum load current. Remember, the maximum ∆IL occurs at the maximum input voltage. The inductor ripple current is determined by the frequency, inductance, input and output voltages.
OPER
ATIN
G FR
EQUE
NCY
(kHz
)
600
550
500
450
400
350
300
250
200
150
1000 0.5 1.0 1.5 2.0 3.02.5
FREQSET PIN VOLTAGE (V)
3734 F02
Figure 2. Operating Frequency vs VFREQSET
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APPLICATIONS INFORMATIONInductor Core Selection
Once the value for L1 is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool Mµ cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductor type selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con-centrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that induc-tance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate!
A variety of inductors designed for high current, low volt-age applications are available from manufacturers such as Sumida, Coilcraft, Coiltronics, Toko and Panasonic.
Power MOSFET, D1 Selection
External power MOSFETs must be selected for output stage with the LTC3734: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the PVCC volt-age. This voltage typically ranges from 4.5V to 7V. Con-sequently, logic-level threshold MOSFETs must be used in most applications. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), gate charge QG, reverse transfer ca-pacitance CRSS, breakdown voltage BVDSS and maximum continuous drain current ID(MAX).
When the LTC3734 operates at continuous mode in a step-down configuration, the duty cycles for the top and bottom MOSFETs are approximately:
Top MOSFET Duty Cycle = VOUTVIN
(1)
Bottom MOSFET Duty Cycle = VIN – VOUT
VIN(2)
The conduction losses of the top and bottom MOSFETs are therefore:
PCONTOP =VOUTVIN
• IOUT( )2 • 1+ δ • ∆T( ) •RDS(ON) (3)
PCONBOT =VIN – VOUT
VIN• IOUT( )2 • 1+ δ • ∆T( ) (4)
• RDS(ON)
where IOUT is the maximum output current at full load, ∆T is the difference between MOSFET operating temperature and room temperature, and δ is the temperature depen-dency of RDS(ON). δ is roughly 0.004/°C ~ 0.006/°C for low voltage MOSFETs.
The power losses of driving the top and bottom MOSFETs are simply:
PDRTOP = QG • PVCC • f (5)
PDRBOT = QG • PVCC • f (6)
Use QG data at VGS = PVCC in MOSFET data sheets. f is the switching frequency as described previously. Please notice that the above gate driving losses are usually not dissipated by the MOSFETs. Instead they are mainly dis-sipated on the internal drivers of the LTC3734, if there are no resistors connected between the drive pins (TG, BG) and the gates of the MOSFETs.
The calculation of MOSFET switching loss is complicated by several factors including the wide distribution of power
LTC3734
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APPLICATIONS INFORMATIONMOSFET threshold voltage, the nonlinearity of current ris-ing/falling characteristic and the Miller Effect. Given the data in a typical power MOSFET data sheet, the switch-ing losses of the top and bottom MOSFETs can only be estimated as follows:
PSWTOP = VIN2 •
IOUT2
• f •CRSS •RDR • (7)
1VDR – VTH(MIN)
+ 1VTH(MIN)
PSWBOT ≈ 0 (8)
where RDR is the effective driver resistance (of approxi-mately 2Ω), VDR is the driving voltage (= PVCC) and VTH(MIN) is the minimum gate threshold voltage of the MOSFET. Please notice that the switching loss of the bottom MOSFET is effectively negligible because the current conduction of the antiparalleling diode. This effect is often referred as zero-voltage-transition (ZVT). Similarly when the LTC3734 converter works under fully synchronous mode at light load, the reverse inductor current can also go through the body diode of the top MOSFET and make the turn-on loss to be negligible. However, equations 7 and 8 have to be used in calculating the worst-case power loss, which happens at highest load level.
The selection criteria of power MOSFETs start with the stress check:
VIN < BVDSS
IMAX < ID(MAX)
and
PCONTOP + PSWTOP < top MOSFET maximum power dissipation specification
PCONBOT + PSWBOT < bottom MOSFET maximum power dissipation specification
The maximum power dissipation allowed for each MOSFET depends heavily on MOSFET manufacturing and pack-aging, PCB layout and power supply cooling method. Maximum power dissipation data are usually specified in MOSFET data sheets under different PCB mounting conditions.
The next step of selecting power MOSFETs is to minimize the overall power loss:
POVL = PTOP + PBOT
= (PCONTOP + PDRTOP + PSWTOP) + (PCONBOT + PDRBOT + PSWBOT)
For typical mobile CPU applications where the ratio between input and output voltages is higher than 2:1, the bottom MOSFET conducts load current most of the time while the main losses of the top MOSFET are for switching and driving. Therefore a low RDS(ON) part (or multiple parts in parallel) would minimize the conduction loss of the bottom MOSFET while a higher RDS(ON) but lower QG and CRSS part would be desirable for the top MOSFET.
The Schottky diode, D1 in Figure 1, conducts during the dead-time between the conduction of the top and bottom MOSFETs. This helps reduce the current flowing through the body diode of the bottom MOSFET. A body diode usu-ally has a forward conduction voltage higher than that of a Schottky and is thus detrimental to efficiency. The charge storage and reverse recovery of a body diode also cause high frequency rings at the switching nodes (the conjunc-tion nodes between the top and bottom MOSFETs), which are again not desired for efficiency or EMI. Some power MOSFET manufacturers integrate a Schottky diode with a power MOSFET, eliminating the need to parallel an external Schottky. These integrated Schottky-MOSFETs, however, have smaller MOSFET die sizes than conventional parts and are thus not suitable for high current applications.
CIN and COUT Selection
In continuous mode, the source current of each top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The RMS input ripple current is estimated to be:
IRMS ≅ IOUT(MAX)
VOUTVIN
VINVOUT
− 1
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX)/2
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APPLICATIONS INFORMATIONThis simple worst-case condition is commonly used for design, considering input/output variations and long term reliability. Note that capacitor manufacturer’s ripple cur-rent ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paral-leled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question.
The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR require-ment has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirements. The steady state output ripple (∆VOUT) is determined by:
∆VOUT ≈ ∆IL ESR + 1
8fCOUT
Where f = operating frequency of each stage, COUT = output capacitance and ∆IL is inductor peak-to-peak ripple current.
The LTC3734 employs OPTI-LOOP technique to compen-sate the switching regulator loop with external components (through ITH pin). OPTI-LOOP compensation speeds up regulator’s transient response, minimizes output capacitance and effectively removes constraints on output capacitor ESR. It opens a much wider selection of output capacitor types and a variety of capacitor manufactures are available for high current, low voltage switching regulators.
Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance through-hole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON type capacitors is recommended to reduce the inductance effects.
In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current han-dling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer (SP) surface
mount capacitors from Panasonic offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV or the KE-MET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo OS-CON, POSCAPs, Kemet AO-CAPs, Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. A combination of capacitors will often result in maximizing performance and minimizing overall cost and size.
PVCC and SVCC Decoupling
The PVCC pin supplies power to the bottom gate driver and therefore must be bypassed to power ground with a minimum of 4.7µF ceramic or tantalum capacitor. Since the gate driving currents are of high amplitude and high slew rate, this bypassing capacitor should be placed very close to the PVCC and PGND pins to minimize the parasitic inductance. Do NOT apply greater than 7V to the PVCC pin.
The SVCC pin supplies current to the internal control circuitry of the LTC3734. This supply current is much lower than that of the current for the external MOSFET gate drive. Ceramic capacitors are very good for high frequency filtering and a 0.1µF ~ 1µF ceramic capacitor should be placed adjacent to the SVCC and SGND pins.
Topside MOSFET Driver Supply (CB,DB) (Refer to Functional Diagram)
External bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though diode DB from PVCC when the SW pin is low. When the topside MOSFET turns on, the driver places the CB volt-age across the gate-source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin rises to VIN + PVCC. The value of the boost capacitor CB needs to be 30 to 100 times that of the total input capaci-tance of the topside MOSFET(s). The reverse breakdown of DB must be greater than PVCC(MAX).
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APPLICATIONS INFORMATIONVID Output Voltage Programming
After 27µs ~ 71µs tBOOT delay, the output voltage of the regulator is digitally programmed as defined in Table 1 using the VID0 to VID5 logic input pins. The VID logic inputs program a precision, 0.25% internal feedback re-sistive divider. The LTC3734 has an output voltage range of 0.700V to 1.708V in 16mV steps.
Refering to the Functional Diagram, there is a resistor, RVID, from VFB to ground. The value of RVID is controlled by the six VID input pins. Another internal resistor, 5.33k (RATTEN), completes the resistive divider. The output voltage is thus set by the ratio of (RVID + 5.33k) to RVID.
Each VID digital pin is a high impedance input. There-fore they must be actively pulled high or pulled low. The logic low threshold of the VID pins is 0.3V; the logic high threshold is 0.7V.
Soft-Start/Run Function
The RUN/SS pin provides three functions: 1) run/shutdown, 2) soft-start and 3) an optional short-circuit latchoff timer. Soft-start reduces the input power source’s surge currents by gradually increasing the controller’s current limit. The latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. A small pull-up cur-rent (>5µA) supplied to the RUN/SS pin will prevent the overcurrent latch from operating. The following paragraph describes how the functions operate.
An internal 1.5µA current source charges up the soft-start capacitor, CSS. When the voltage on RUN/SS reaches 1.5V, the controller is permitted to start operating. As the volt-age on RUN/SS increases from 1.5V to 3.0V, the internal current limit is increased from 25mV/RSENSE to 72mV/RSENSE. The output current thus ramps up slowly, elimi-nating the starting surge current required from the input power supply. If RUN/SS has been pulled all the way to ground there is a delay before starting of approximately:
tDELAY = 1.5V
1.5µACSS = 1s/µF( )CSS
The time for the output current to ramp up is then:
tIRAMP = 3V − 1.5V
1.5µACSS = 1s/µF( )CSS
By pulling the RUN/SS pin below 1V the LTC3734 is put into low current shutdown (IQ < 100µA). The RUN/SS pin can be driven directly from logic as shown in Figure 3. Diode D1 in Figure 3 reduces the start delay but allows CSS to ramp up slowly providing the soft-start function. The RUN/SS pin has an internal 6V zener clamp (see Functional Diagram).
3.3V OR 5V RUN/SS RUN/SSPVCC
D1
CSS
RSS*
CSS
3734 F03
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
Figure 3. RUN/SS Pin Interfacing
Start-Up Sequence (Refer to the Functional Diagram)
After soft-start, the output voltage of the regulator settles at a voltage level equal to VBOOT.
VBOOT = 0.6V •
R2 • R3 + R5( )R5 • R1+ R2( )
By using different R5 resistors, VBOOT can be programmed.
After the output voltage enters the ±10% regulation window centered at VBOOT, the internal power good comparator issues a logic high signal. Refer to the timing diagram in Figure 4. This signal then enters a logic AND gate, with MCH_PG being the other input, and the output of the gate is PG shown in Figure 4. This composite PG signal is then delayed by tBOOT amount of time and then becomes MD. As soon as MD is asserted, the output voltage changes from VBOOT to VVID, a voltage level totally controlled by the six VID bits. In the LTC3734, the time tBOOT is set to be 15 switching cycles:
tBOOT = 15
1fS
If fS is set at 210kHz, tBOOT = 71µs
If fS is set at 550kHz, tBOOT = 27µs
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APPLICATIONS INFORMATION
Output Voltage Set in Deep Sleep and Deeper Sleep States (Refer to the Functional Diagram)
The output voltage can be offset by the STP_CPUB signal. When STP_CPUB becomes low, the output voltage will be a certain percentage lower than that set by the VID bits in Table 1. This state is defined to be the deep sleep state. Referring to the Functional Diagram, we can calculate the STP_CPUB offset to be:
STP% = –
R3R3 + R4
•100%
By using different R4 resistors, STP_CPUB offset can be programmed.
The output voltage could also be set by external resistors R4 and R6 when DPRSLPVR input is high. This state is defined to be the deeper sleep state. The output voltage is set to VDPRSLPVR, regardless of the VID setting:
VDPRSLPVR = 0.6V •
R2 • R3 + R6 R4( )R6 R4( ) • R1+ R2( )
where R6||R4 is the parallel combination of R4 and R6.
By using different value R6 resistors, VDPRSLPVR can be programmed.
(The digital input threshold voltage is 1.8V for STP_CPUB, DPRSLPVR and MCH_PG inputs.)
Power Good Masking
The PGOOD output monitors VOUT. When VOUT is not within ±10% of the set point, PGOOD is pulled low with an internal MOSFET. When VOUT is within the regulation window, PGOOD is of high impedance. PGOOD should be pulled up by an external resistor.
During VID changes, deep sleep and deeper sleep transi-tions, the output voltage can initially be out of the ±10% window of the newly set regulation point. To avoid nui-sance indications from PGOOD, a timer masks PGOOD for 110µs. If output is still out of regulation after this blanking time, PGOOD goes low. Any overvoltage or undervoltage condition is also masked for 110µs before it is reported by PGOOD.
The masking circuitry also adaptively tracks VID and state changes. If a new change in VID or state happens before the 110µs masking timer expires, the timer resets and starts a fresh count of 110µs. This prevents the system from rebooting under frequent output voltage transitions. Refer to Figure 5 for the PGOOD timing diagram.
During start up, PGOOD is actively pulled low until the RUN/SS pin voltage reaches its arming voltage, which
INTERNAL PG(OUTPUT OF
INTERNALPOWER GOOD
COMPARATOR)
MCH_PG
COMPOSITE PG(=(INTERNAL PG)AND (MCH_PG))
MD
VOUT
VID BITSINVALID
VALID
RUN/SS1.5V
90% VBOOT
VBOOTVVID
tBOOT
TIME 3734 F04
Figure 4. Start-Up Timing Diagram
VID BITS
VOUT
INTERNAL PG(OUTPUT OF
INTERNALPOWER GOOD
COMPARATOR)
PGOODMASKING
PGOOD
110µs110µs
TIME 3734 F05
Figure 5. PGOOD Timing Diagram
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APPLICATIONS INFORMATION
is 4.2V typically. Only then is the PGOOD pull-low signal released.
When RUN/SS goes low, PGOOD goes low simultaneously.
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to latch off the controller when an overcurrent condition is detected. The
RUN/SS capacitor, CSS, is used initially to limit the inrush current. After the controller has been started and been given adequate time to charge up the output capacitors and provide full load current, the RUN/SS capacitor is used for a short-circuit timer. If the output voltage falls to less than 70% of its nominal value after CSS reaches 4.2V, CSS begins discharging on the assumption that the output is in an overcurrent condition. If the condition lasts for a long
VID5 VID4 VID3 VID2 VID1 VID0 LTC3734
0 0 0 0 0 0 1.708V
0 0 0 0 0 1 1.692V
0 0 0 0 1 0 1.676V
0 0 0 0 1 1 1.660V
0 0 0 1 0 0 1.644V
0 0 0 1 0 1 1.628V
0 0 0 1 1 0 1.612V
0 0 0 1 1 1 1.596V
0 0 1 0 0 0 1.580V
0 0 1 0 0 1 1.564V
0 0 1 0 1 0 1.548V
0 0 1 0 1 1 1.532V
0 0 1 1 0 0 1.516V
0 0 1 1 0 1 1.500V
0 0 1 1 1 0 1.484V
0 0 1 1 1 1 1.468V
0 1 0 0 0 0 1.452V
0 1 0 0 0 1 1.436V
0 1 0 0 1 0 1.420V
0 1 0 0 1 1 1.404V
0 1 0 1 0 0 1.388V
0 1 0 1 0 1 1.372V
0 1 0 1 1 0 1.356V
0 1 0 1 1 1 1.340V
0 1 1 0 0 0 1.324V
0 1 1 0 0 1 1.308V
0 1 1 0 1 0 1.292V
0 1 1 0 1 1 1.276V
0 1 1 1 0 0 1.260V
0 1 1 1 0 1 1.244V
0 1 1 1 1 0 1.228V
0 1 1 1 1 1 1.212V
VID5 VID4 VID3 VID2 VID1 VID0 LTC3734
1 0 0 0 0 0 1.196V
1 0 0 0 0 1 1.180V
1 0 0 0 1 0 1.164V
1 0 0 0 1 1 1.148V
1 0 0 1 0 0 1.132V
1 0 0 1 0 1 1.116V
1 0 0 1 1 0 1.100V
1 0 0 1 1 1 1.084V
1 0 1 0 0 0 1.068V
1 0 1 0 0 1 1.052V
1 0 1 0 1 0 1.036V
1 0 1 0 1 1 1.020V
1 0 1 1 0 0 1.004V
1 0 1 1 0 1 0.988V
1 0 1 1 1 0 0.972V
1 0 1 1 1 1 0.956V
1 1 0 0 0 0 0.940V
1 1 0 0 0 1 0.924V
1 1 0 0 1 0 0.908V
1 1 0 0 1 1 0.892V
1 1 0 1 0 0 0.876V
1 1 0 1 0 1 0.860V
1 1 0 1 1 0 0.844V
1 1 0 1 1 1 0.828V
1 1 1 0 0 0 0.812V
1 1 1 0 0 1 0.796V
1 1 1 0 1 0 0.780V
1 1 1 0 1 1 0.764V
1 1 1 1 0 0 0.748V
1 1 1 1 0 1 0.732V
1 1 1 1 1 0 0.716V
1 1 1 1 1 1 0.700V
Table 1. VID Output Voltage Programming
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APPLICATIONS INFORMATIONenough period as determined by the size of the CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. If the overload occurs during start-up, the time can be approximated by:
tLO1 ≈ (CSS • 0.7V)/(1.5µA) = 4.6 • 105 (CSS)
If the overload occurs after start-up, the voltage on CSS will continue charging and will provide additional time before latching off:
tLO2 ≈ (CSS • 2V)/(1.5µA) = 1.3 • 106 (CSS)
This built-in overcurrent latchoff can be overridden by providing a pull-up resistor, RSS, to the RUN/SS pin as shown in Figure 3. This resistance shortens the soft-start period and prevents the discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. When deriving the 5µA current from PVCC as in the figure, current latchoff is always defeated.
Why should you defeat current latchoff? During the pro-totyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off the controller. Defeating this feature allows troubleshooting of the circuit and PC layout. The internal short-circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. A decision can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor.
The value of the soft-start capacitor CSS may need to be scaled with output voltage, output capacitance and load current characteristics. The minimum soft-start capaci-tance is given by:
CSS > (COUT )(VOUT)(10-4)(RSENSE)
A recommended soft-start capacitor of CSS = 0.1µF will be sufficient for most applications.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration that the LTC3734 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that:
tON MIN( ) <
VOUTVIN f( )
If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3734 will begin to skip cycles resulting in variable frequency operation. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase.
The minimum on-time for the LTC3734 is generally less than 150ns. However, as the peak sense voltage decreases, the minimum on-time gradually increases. This is of par-ticular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger ripple current and ripple voltage.
If an application can operate close to the minimum on-time limit, an inductor must be chosen that has a low enough inductance to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule, keep the inductor ripple current equal to or greater than 15% of IOUT(MAX) at VIN(MAX).
Active Voltage Positioning
Active voltage positioning can be used to minimize peak-to-peak output voltage excursion under worst-case transient loading conditions. The open-loop DC gain of the control loop is reduced depending upon the maximum load step specifications. Active voltage positioning can easily be added to the LTC3734. Figure 6 shows the equivalent circuit for implementing AVP. The load line slope is estimated to be:
AVP ≅ –35.5 •RSENSE
m•
R3RAVP
,
if gm •R3 > 10 •VOUT0.6V
(9)
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APPLICATIONS INFORMATIONwhere
AVP is the slope, in mV/A
RSENSE is the current sense resistor
m is the number of phases, m = 1 for LTC3734
R3 and RAVP are defined in Figure 6
gm is the transconductance gain for the error amplifier, it is about 4.5mmho for LTC3734.
Rewriting this equation, we can estimate the RAVP value to be:
RAVP ≅ 35.5 •R3m • | AVP|RSENSE
–1
(12)
Typically the calculation results based on these equations have ±10% tolerance. So the resistor values need to be fine tuned.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-age of input power.
Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3734 circuits: 1) I2R losses, 2) Topside MOSFET transition losses, 3) PVCC supply current and 4) CIN loss.
1) I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, and current sense resistor. In continuous mode the average output current flows through L and RSENSE, but is “chopped” between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For example, if each RDS(ON) = 10mΩ, RL = 10mΩ, and RSENSE = 5mΩ, then the total resistance is 25mΩ. This results in losses ranging from 2% to 8% as the output current increases from 3A to 15A per output stage for a 5V output, or a 3% to 12% loss per output stage for a 3.3V
–
+
–
+0.6V
VOUT+
R3
R2
RAVP
R1
ITHVID
OAOUT
VOA+
VOA–
FB
3735 F09
Figure 6. Simplified Schematic Diagram for AVP Design in LTC3734
Rewriting equation (9) we can estimate the AVP resistor to be:
RAVP ≅
35.5 •R3 •RSENSEm • | AVP|
(10)
We also adopt the current sense resistors as part of voltage positioning slopes. So the total load line slope is estimated to be:
AVP ≅ –35.5 •RSENSE
m•
R3RAVP
–RSENSE
m,
if gm •R3 >>VOUT0.6V
(11)
LTC3734
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APPLICATIONS INFORMATIONoutput. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system!
2) Transition losses apply only to the topside MOSFET(s), and are significant only when operating at high input volt-ages (typically 12V or greater). Transition losses can be estimated from:
TransitionLoss = VIN2 •
IOUT2
• f •CRSS •RDR •
1VDR – VTH(MIN)
+ 1VTH(MIN)
3) PVCC drives both top and bottom MOSFETs. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from PVCC to ground. The resulting dQ/dt is a current out of PVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = (QT + QB)f, where QT and QB are the gate charges of the topside and bottom side MOSFETs and f is the switching frequency.
4) The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries.
Other losses, including COUT ESR loss, Schottky diode conduction loss during dead time, inductor core loss and internal control circuitry supply current generally account for less than 2% additional loss.
Checking Transient Response
The regulator loop response can be checked by look-ing at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD(ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time, and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon first because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of <1µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step result-ing from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance.
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APPLICATIONS INFORMATIONAutomotive Considerations: Plugging into the Cigarette Lighter
As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main battery line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery and double-battery.
Load-dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alterna-tor can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse-battery is just what it says, while double-battery is a consequence of tow truck operators finding that a 24V jump start cranks cold engines faster than 12V.
The network shown in Figure 7 is the most straightforward approach to protect a DC/DC converter from the ravages of an automotive power line. The series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the LTC3734 has a maximum input voltage of 32V, most applications will be limited to 30V by the MOSFET BVDSS.
+
LTC3734
PVCC
PVCC
VBAT12V
3734 F07
Figure 7. Automotive Application Protection
Design Example
As a design example, assume VIN = 12V (nominal), VIN = 21V (max), VOUT = 1.5V, IMAX = 20A, and f = 350kHz.
The inductance value is chosen first based on a 40% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. The minimum inductance for 40% ripple current is:
L ≥VOUTf • ∆I
• 1–VOUTVIN
= 1.5V350kHz • 40% •20A( ) •
1–1.5V21V
= 0.5µH
The peak inductor current will be the maximum DC current plus one half of the ripple current, or 24A.
Tie the FREQSET pin to 1.2V, resistively divided down from SVCC to have 350kHz operation.
The minimum on-time also occurs at maximum input voltage:
tON(MIN) =
VOUTVIN • f
= 1.5V21V •350kHz
= 204ns
which is larger than 150ns, the typical minimum on time of the LTC3734.
RSENSE can be calculated by using a conservative maximum sense voltage threshold of 40mV and taking into account of the peak current:
RSENSE = 40mV
24A= 0.002Ω
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APPLICATIONS INFORMATIONThe power loss dissipated by the top MOSFET can be cal-culated with equations 3 and 7. Using a Fairchild FDS7760 as an example: RDS(ON) = 8mΩ, QG = 55nC at 5V VGS, CRSS = 307pF, VTH(MIN) = 1V. At maximum input voltage with TJ(estimated) = 85°C at an elevated ambient temperature:
PTOP =1.5V21V
• 20A2 • 1+ 0.005 • 85°C – 25°C( )( ) •
0.008Ω + 21V2 •20A
2• 350kHz • 307pF •
2Ω •1
5V – 1V+
11V
= 1.48W
Equation 4 gives the worst-case power loss dissipated by the bottom MOSFET (assuming FDS7760 and TJ = 85°C again):
PBOT = 21V –1.5V21V
•20A2 •
1+ 0.005 • 85°C – 25°C( )( ) •0.008Ω
= 3.86W
Therefore, it is necessary to have two FDS7760s in par-allel to split the power loss for both the top and bottom MOSFETS.
A short-circuit to ground will result in a folded back cur-rent of about:
ISC = 25mV
0.002Ω+ 1
2•
200ns •21V0.5µH
= 16.7A
The worst-case power dissipation by the bottom MOSFET under short-circuit conditions is:
PBOT =
1350kHz
– 200ns
1350kHz
•16.7A2 •
1+ 0.005 • 85°C – 25°C( )( ) •0.008Ω
= 2.7W
which is less than normal, full load conditions.
The RMS input ripple current will be:
IINRMS = 20A/2 = 10A
An input capacitor(s) with a 10A RMS current rating is required.
The output capacitor ripple current is calculated. The out-put ripple will be highest at the maximum input voltage:
∆IOUT(MAX) = 1.5V
350kHz •0.5µH• 1− 1.5
2.1
= 8AP-P
Assuming the ESR of output capacitor(s) is 5mΩ, the output ripple voltage is:
∆VOUT ≈ 8AP-P 5mΩ + 18 •350kHz • 4 •270µF( )
= 42.6mVP-P
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PC Board Layout Checklist
When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3734. Check the following in your layout:
1) Are the signal and power grounds segregated? Keep the SGND at one end of a PC board to prevent MOSFET currents from traveling under the IC. The IC signal ground pin (Pin 5) should be used to hook up all control circuitry on one side of the IC, routing the copper through SGND, under the IC covering the “shadow” of the package, con-necting to the PGND pin (Pin 20) and then continuing on to the (–) plate of COUT.
2) Is the PVCC decoupling capacitor connected immedi-ately adjacent to the PVCC and PGND pins? A 1µF ceramic capacitor of the X7R or X5R material is small enough to fit very close to the IC to minimize the ill effects of the large current pulses drawn to drive the power MOSFETs. An additional 4.7µF ~ 10µF of ceramic, tantalum or other low ESR capacitor is recommended in order to keep PVCC stable. The power ground returns to the sources of the bot-tom N-channel MOSFETs, anodes of the Schottky diodes, and (–) plates of CIN, which should have the shortest trace length possible.
3) Are the SENSE – and SENSE+ leads routed together with minimum PC trace spacing? The filter capacitors between SENSE+ and SENSE– pin pairs should be as close as possible to the LTC3734. Ensure accurate cur-rent sensing with Kelvin connections at the current sense resistor. See Figure 8.
APPLICATIONS INFORMATION4) Does the (+) plate of CIN connect to the drains of the topside MOSFETs as closely as possible? This capacitor provides the AC current to the MOSFETs. Keep the input current path formed by the input capacitor, top and bot-tom MOSFETs, and the Schottky diode on the same side of the PC board in a tight loop to minimize conducted and radiated EMI.
5) Keep the “noisy” nodes, SW, BOOST, TG and BG away from sensitive small-signal nodes. Ideally the switch nodes should be placed at the furthest point from the LTC3734.
It is critical to keep the high-switching-current paths to a small physical size. High electric and magnetic fields will radiate from these “loops” just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise to the “noise” gener-ated by a switching regulator. The ground terminations of the sychronous MOSFETs and Schottky diodes should return to the negative plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. A separate isolated path from the negative plate(s) of the input capacitor(s) should be used to tie in the IC power ground pin (PGND) and the signal ground pin (SGND). This technique keeps inherent signals generated by high current pulses from taking alternate current paths that have finite impedances during the total period of the switching regulator. External OPTI-LOOP compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure.
SENSE+ SENSE –
TRACE TO INDUCTOR TRACE TO OUTPUT CAP (+)
PADS OF SENSE RESISTOR
3734 F08
Figure 8. Proper Current Sense Connections
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TYPICAL APPLICATIONFigure 9 shows a typical application using the LTC3734 to power the mobile CPU core. The input can vary from 5V to 24V; the output voltage can be programmed from 0.7V to 1.708V with a maximum current of 20A. By only modifying the external MOSFET and inductor selection, higher load current capability can be achieved.
The power supply in Figure 9 receives a VRON signal for ON/OFF control. After soft-start, the output voltage is set at 1.2V until the assertion of the MCH_PG signal. After about a 50µs delay, the VID5-VID0 bits gain the control over the output voltage and program it between 0.7V and
1.708V. When the STP_CPUB signal is low, a deep sleep state is indicated and the output voltage is decreased by about 1.04%. When the DPRSLPVR signal is high, a deeper sleep state is indicated and the output voltage becomes 0.748V regardless of the states of the VID bits. Active voltage positioning is accomplished with a resistive divider across the ITH pin. Lower resistance yields a steeper AVP slope while higher resistance provides a flatter slope. Finally, the PGOOD output is masked for 110µs during VID change or state transition.
Figure 9. 5V to 24V Input, 0.7V to 1.708V Output, 20A IMVP-IV Compatible Power Supply
MCH_PG
DPRSLPVR
STP_CPUB
PSIB
FREQSET
VID0
VID1
VID2
VID3
VID4
VID5
PGOOD
ITH
RUN/SS
SGND
VFB
PVCC
BOOST
TG
SW
BG
PGND
SENSE+
SENSE–
RBOOT
RDPRSLP
RDPSLP
VOA+
OAOUT
VOA–
MCH_PG
DPRSLPVR
STP_CPUB
PSIB
VID0
VID1
VID2
VID3
VID4
VID5
27
30
4
32
31
13
14
15
17
18
19
26
11
10
5
28
22
25
24
23
21
20
6
7
12
8
9
1
3
2
1M1%
PGOOD
249k
3.3V3.3V
1M3k
100pF
0.47µF
BAT54
SW
680pF
100pF
5V4.7µFX5R
1µFX5R
VOUT
VOA+
3.3V
VOA+
5V
LTC3734
0.002Ω
1µFQ1
Q2 D1
L10.8µH
C5: PANASONIC SP EEFSX0R181R OR SANYO POSCAP 2R5TPE220MGD1: B340AL1: SUMIDA CEP125-0R8Q1: IRF7811W(SO8) OR FDS7860DPQ2: IRF7811W OR FDS7856DP(SO8) ×2
13.3k
10Ω
10Ω
12.7k1%
1.27M
56.2k
13.3k
1.27M
3734 F09
1nF
C110µF ×535V X5R
VIN5V TO 24V
VOUT0.7V TO 1.708VAT 20A
C5270µF ×32V
1µF+
SVCC0.1µFX5R
5V29
RBOOT
1000pF100k
2k
VRON
VRON
Si1034X
470pF
MMBT3904 MMBT3904
2N7002
80.6k
2k
PGOOD
1.9k
RBOOT
1M
1µF
CLKEN#
4.12k43.2k
IMPV4_PG
LTC3734
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PACKAGE DESCRIPTION
5.00 ± 0.10(4 SIDES)
NOTE:1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED)2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1TOP MARK(NOTE 6)
0.40 ± 0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.50 REF(4-SIDES)
3.45 ± 0.10
3.45 ± 0.10
0.75 ± 0.05 R = 0.115TYP
0.25 ± 0.05(UH32) QFN 0406 REV D
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 ±0.05
3.50 REF(4 SIDES)
4.10 ±0.05
5.50 ±0.05
0.25 ± 0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUTAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH R = 0.30 TYPOR 0.35 × 45° CHAMFERR = 0.05
TYP
3.45 ± 0.05
3.45 ± 0.05
UH Package32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
LTC3734
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORYREV DATE DESCRIPTION PAGE NUMBER
A 4/11 Updated Figure 9Updated Related Parts
2528
LTC3734
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Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2002
LT 0411 REV A • PRINTED IN USA
RELATED PARTSPART NUMBER DESCRIPTION COMMENTS
LTC3816 Single Phase DC/DC Controller for Intel IMVP-6/6+/6.5 CPUs 7-Bit IMVP-6 VID: 0.00V ≤ VOUT ≤ 1.50V, 4.5V ≤ VIN ≤ 36V, Very Low Duty Cycle Capable
LTC3732 3-Phase, 5-Bit VID, 600kHz, Synchronous Controller 5-Bit VRM 9/9.1: 1.10V ≤ VOUT ≤ 1.85V, 4.5V ≤ VIN ≤ 32V, Stage Shedding™ or Burst Mode® Operation
LTC3735 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs 6-Bit IMVP-4 VID: 0.70V ≤ VOUT ≤ 1.708V, 4.5V ≤ VIN ≤ 30V, Lossles Voltage Positioning
LTC3869/LTC3869-2 Dual, 2-Phase Synchronous Step-Down DC/DC Controllers with Excellent Current Share when Paralleled
Phase-Lockable Fixed 250kHz to 780kHz Frequency, 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 12.5V
LTC3856 2-Phase, Single Output Synchronous Step-Down DC/DC Controller with Diff Amp and DCR Temperature Compensation
Phase-Lockable Fixed 250kHz to 770kHz Frequency, 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5V
LTC3850/LTC3850-1 LTC3850-2
Dual 2-Phase, High Efficiency Synchronous Step-Down DC/DC Controller, RSENSE or DCR Current Sensing and Tracking
Phase-Lockable Fixed 250kHz to 780kHz Frequency, 4V ≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V
LTC3860 Dual, Multiphase, Synchronous Step-Down DC/DC Controller with Diff Amp and Three-State Output Drive
Operates with Power Blocks, DRMOS Devices or External Drivers/MOSFETs, 3V ≤ VIN ≤ 24V, tON(MIN) = 20ns
LTC3855 Dual, Multiphase, Synchronous Step-Down DC/DC Controller with Diff Amp and DCR Temperature Compensation
Phase-Lockable Fixed Frequency 250kHz to 770kHz, 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 12V
LTC3829 3-Phase, Single Output Synchronous Step-Down Controller with Diff Amp and DCR Temperature Compensation
Phase-Lockable Fixed 250kHz to 770kHz Frequency, 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5V
LTC3853 Triple Output, Multiphase Synchronous Step-Down DC/DC Controller, RSENSE or DCR Current Sensing and Tracking
Phase-Lockable Fixed 250kHz to 750kHz Frequency, 4V ≤ VIN ≤ 24V, VOUT3 Up to 13.5V