ltm2892 - spi/digital or i2c µmodule isolator

LTM2892

12892fa

For more information www.linear.com/LTM2892

Typical applicaTion

FeaTures DescripTion

SPI/Digital or I2CµModule Isolator

The LTM®2892 is a complete galvanic digital µModule® (micromodule) isolator. No external components are re-quired. Individual 3V to 5.5V supplies power each side of the digital isolator. Separate logic supply pins allow easy interfacing with different logic levels from 1.62V to 5.5V, independent of the main supply.

Module options are available with compatibility to SPI (LTM2892-S) and I2C (LTM2892-I), master mode only, specifications.

Coupled inductors provide 3500VRMS of isolation between the input and output logic interface. This device is ideal for systems where the ground loop is broken, allowing uninterrupted communication through large common mode transients faster than 50kV/μs. L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks and HotSwap is a trademark of of Linear Technology Corporation. All other trademarks are the property of their respective owners.

Isolated 4MHz SPI Interface

applicaTions

n 6-Channel Logic Isolator: 3500VRMS for 1 Minute n UL-CSA Recognized File #E151738 n 3V to 5.5V Supply Operation n No External Components Required n SPI/Digital (LTM2892-S) or I2C (LTM2892-I) Options n High Common Mode Transient Immunity: 50kV/μs n High Speed Operation:

n 10MHz Digital Isolation n 4MHz/8MHz SPI Isolation n 400kHz I2C Isolation

n Operation Up to 125°C (H-Grade) n 1.62V to 5.5V Logic Supplies for Flexible Digital Inter-

facing n ±15kV ESD HBM Across the Isolation Barrier n Maximum Continuous Working Voltage: 850VPEAK n Low Current Shutdown Mode (<10µA) n Small (9mm × 6.25mm × 2.91mm) BGA Package

n Isolated SPI or I2C Interfaces n Industrial Systems n Test and Measurement Equipment n Breaking Ground Loops

LTM2892 Operating Through 50kV/µs CM Transients

VCC1VL1ON1EOUTDINAINBINC

OUTDOUTEOUTF

3V TO 5.5V

MISO

SCKMOSI

SS

3V TO 5.5V

MISO

SCKMOSISS

VCC2VL2ON2

EOUTAOUTAOUTBOUTC

INDINEINF

LTM2892-S

GND2GND1

ISOL

ATIO

N BA

RRIE

R

2892 TA01a

20ns/DIV

5V/DIV

200V/DIV

5V/DIV

2892 TA01b

INAOUTD

GND2-GND1

OUTA CONNECTED TO IND

http://www.linear.com/LTM2892


LTM2892

22892fa


absoluTe MaxiMuM raTings

VCC1 to GND1 ............................................... –0.3V to 6VVL1 to GND1 ................................................. –0.3V to 6VVCC2 to GND2 ............................................... –0.3V to 6VVL2 to GND2 ................................................. –0.3V to 6VLogic Inputs INA, INB, INC, SCLIN, SDA1, EOUTD,

ON1 to GND1 ............................ –0.3V to (VL1 + 0.3V) INB, INC, IND, INE, INF, SDA2, EOUTA,

ON2 to GND2 ............................–0.3V to (VL2 + 0.3V)

(Note 1)

LTM2892-I LTM2892-S

BGA PACKAGE24-PIN (9mm × 6.25mm × 2.91mm)

TOP VIEW

OUTB SDA1 OUTC

SCLIN SDA1 INA ON1 VL1 VCC1

GND1

INB SDA2

SDA2

INC

SCLOUT OUTA

ON2 VL2 VCC2

GND2

F

G

H

J

E

A

B

C

D

5 63 421

TJMAX = 125°C, θJA = 30°C/W, θJC(bottom) = 15.7°C/W,

θJC(top) = 25°C/W, θJB = 14.5°C/W θ VALUES DETERMINED PER JESD 51-9, WEIGHT = 0.3g

BGA PACKAGE24-PIN (9mm × 6.25mm × 2.91mm)

TOP VIEW

OUTD OUTE OUTF EOUTD

INA INB INC ON1 VL1 VCC1

GND1

IND INE

OUTB

INF

OUTA OUTC EOUTA

ON2 VL2 VCC2

GND2

F

G

H

J

E

A

B

C

D

5 63 421

TJMAX = 125°C, θJA = 30°C/W, θJC(bottom) = 15.7°C/W,

θJC(top) = 25°C/W, θJB = 14.5°C/W θ VALUES DETERMINED PER JESD 51-9, WEIGHT = 0.3g

pin conFiguraTion

Logic Outputs OUTB, OUTC, OUTD, OUTE, OUTF to GND1 ......................... – 0.3V to (VL1 + 0.3V) OUTA, OUTB, OUTC, SCLOUT to GND2 ..................... – 0.3V to (VL2 + 0.3V)

Operating Temperature Range (Note 4) LTM2892C ............................................... 0°C to 70°C LTM2892I ............................................–40°C to 85°C LTM2892H ......................................... –40°C to 125°C

Maximum Internal Operating Temperature ............ 125°CStorage Temperature Range .................. –55°C to 150°CPeak Body Reflow Temperature ............................ 260°C


LTM2892

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elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted.

orDer inForMaTion

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supplies

VCC1, VCC2 Input Supply Range l 3 5.5 V

VL1, VL2 Logic Supply Range LTM2892-S LTM2892-I

l

l

1.62 3

5.5 5.5

V V

ICC1, ICC2 Input Supply Current ON1 = ON2 = 0V ON1 = VL1, ON2 = VL2

l

l

0 3.2

10 4.5

µA mA

IL1, IL2 Logic Supply Current ON1 = ON2 = 0V LTM2892-S, ON1 = VL1, ON2 = VL2 IL1, LTM2892-I, ON1 = VL1, ON2 = VL2 IL2, LTM2892-I, ON1 = VL1, ON2 = VL2

l

l

0 10

10

150 300

µA µA µA µA

Logic/SPI

VITH Input Threshold Voltage ON1, INx, EOUTD, 1.62V ≤ VL1 < 2.35V ON1, INx, EOUTD, 2.35V ≤ VL1 ON2, INx, EOUTA, 1.62V ≤ VL2 < 2.35V ON2, INx, EOUTA, 2.35V ≤ VL2

l

l

l

l

0.25 •VL1 0.33•VL1 0.25•VL2 0.33 •VL2

0.75 •VL1 0.67•VL1 0.75•VL2 0.67•VL2

V V V V

IINL Input Current l ±1 µA

VHYS Input Hysteresis (Note 2) 150 mV

VOH Output High Voltage OUTx, ILOAD = –1mA, 1.62V ≤ VL1 < 3V OUTx, ILOAD = –4mA, 3V ≤ VL1 ≤ 5.5V OUTB (LTM2892-I), ILOAD = –2mA, 3V ≤ VL1 ≤ 5.5V

l VL1 – 0.4 V

OUTx, ILOAD = –1mA, 1.62V ≤ VL2 < 3V OUTx, ILOAD = –4mA, 3V ≤ VL2 ≤ 5.5V

l VL2 – 0.4 V

LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTM2892CY-I#PBF LTM2892CY-I#PBF LTM2892Y-I 24-Lead (9mm × 6.25mm × 2.91mm) BGA 0°C to 70°C

LTM2892IY-I#PBF LTM2892IY-I#PBF LTM2892Y-I 24-Lead (9mm × 6.25mm × 2.91mm) BGA –40°C to 85°C

LTM2892HY-I#PBF LTM2892HY-I#PBF LTM2892Y-I 24-Lead (9mm × 6.25mm × 2.91mm) BGA –40°C to 125°C

LTM2892CY-S#PBF LTM2892CY-S#PBF LTM2892Y-S 24-Lead (9mm × 6.25mm × 2.91mm) BGA 0°C to 70°C

LTM2892IY-S#PBF LTM2892IY-S#PBF LTM2892Y-S 24-Lead (9mm × 6.25mm × 2.91mm) BGA –40°C to 85°C

LTM2892HY-S#PBF LTM2892HY-S#PBF LTM2892Y-S 24-Lead (9mm × 6.25mm × 2.91mm) BGA –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ This product is moisture sensitive. For more information go to: http://www.linear.com/packaging/

http://www.linear.com/product/LTM2892#orderinfo


http://www.linear.com/leadfree/

http://www.linear.com/packaging/

http://www.linear.com/packaging/

http://www.linear.com/product/LTM2892#orderinfo

LTM2892

42892fa


elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted.


VOL Output Low Voltage OUTx, ILOAD = 1mA, 1.62V ≤ VL1 < 3V OUTx, ILOAD = 4mA, 3V ≤ VL1 ≤ 5.5V OUTB (LTM2892-I), ILOAD = 2mA, 3V ≤ VL1 ≤ 5.5V

l 0.4 V

OUTx, ILOAD = 1mA, 1.62V ≤ VL2 < 3V OUTx, ILOAD = 4mA, 3V ≤ VL2 ≤ 5.5V

l 0.4 V

ISC Short-Circuit Current 0V ≤ OUTx ≤ VL1 0V ≤ OUTB (LTM2892-I) ≤ VL1 0V ≤ OUTx ≤ VL2

l

l

±30

±85

±85

mA mA mA

I2C

VIL Low Level Input Voltage SCLIN, SDA1 SDA2

l

l

0.3•VL1 0.3•VL2

V V

VIH High Level Input Voltage SCLIN, SDA1 SDA2

l

l

0.7•VL1 0.7•VL2

V V

IINL Input Current SCLIN, SDA1 = VL1 or 0V SDA2 = VL2, SDA2 = VL2 = 0V

l

l

±1 ±1

µA µA

VHYS Input Hysteresis SCLIN, SDA1 SDA2

0.05 •VL1 0.05•VL2

mV mV

VOH Output High Voltage SCLOUT, ILOAD = –2mA l VL2 – 0.4 V

VOL Output Low Voltage SDA1, ILOAD = 3mA, SCLOUT, ILOAD = 2mA SDA2 = No Load, SDA1 = 0V, 4.5V ≤ VL2 < 5.5V SDA2 = No Load, SDA1 = 0V, 3V ≤ VL2 < 4.5V

l

l

l

0.3

0.4 0.45 0.55

V V V

CIN Input Pin Capacitance SCLIN, SDA1, SDA2 (Note 2) l 10 pF

CB Bus Capacitive Load SCLOUT, Standard Speed (Note 2) SCLOUT, Fast Speed SDA1, SDA2, SR ≥ 1V/μs, Standard Speed (Note 2) SDA1, SDA2, SR ≥ 1V/μs, Fast Speed

l

l

l

l

400 200 400 200

pF pF pF pF

SDA, SDA2 Slew Rate l 1 V/µs

ISC Short-Circuit Current SDA2 = 0, SDA1 = VL1 0V ≤ SCLOUT ≤ VL2 SDA1 = 0, SDA2 = VL2 SDA1 = VL1, SDA2 = 0

l ±30 6

–1.8

100 mA mA mA mA

ESD (HBM) (Note 2)

Isolation Boundary GND2 to GND1 (VCC2, VL2, GND2) to (VCC1, VL1, GND1)

±15 ±10

kV kV


LTM2892

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swiTching characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted.


Logic/SPI

Maximum Data Rate INx → OUTx, CL = 15pF (Note 3) Bidirectional SPI Communication Unidirectional SPI Communication

l

l

l

10 4 8

MHz MHz MHz

tPHL, tPLH Propagation Delay INx → OUTx, CL = 15pF (Figure 1) l 35 60 100 ns

tR, tF Rise and Fall Time OUTx, CL = 15pF (Figure 1) LTM2892-I, OUTB, CL = 15pF (Figure 1)

l

l

3 20

12.5 35

ns ns

tPWU Output Pulse Width Uncertainty OUTB, OUTC, OUTE, OUTF (Note 2) –20 50 ns

tPZH, tPZL Output Enable Time EOUTx = ↓ to OUTx, RL = 1k, CL = 15pF (Figure 2) l 50 ns

tPHZ, tPLZ Output Disable Time EOUTx = ↑ to OUTx, RL = 1k, CL = 15pF (Figure 2) l 50 ns

tPZH, tPZL ONx Enable Time ONx = ↑ to OUTx, RL = 1k, CL = 15pF (Figure 4) l 60 μs

tPHZ, tPLZ ONx Disable Time ONx = ↓ to OUTx, RL = 1k, CL = 15pF (Figure 4) l 50 ns

I2C

Maximum Data Rate (Note 3) l 400 kHz

tPHL, tPLH Propagation Delay SCLIN → SCLOUT, CL = 15pF (Figure 1) SDA1 → SDA2, RL = Open, CL = 15pF (Figure 3) SDA2 → SDA1, RL = 1.1k, CL = 15pF (Figure 3)

l

l

l

150 150 300

225 250 500

ns ns ns

tR Rise Time SDA2, CL = 200pF (Figure 3) SDA2, CL = 200pF (Figure 3) SDA1, RL = 1.1k, CL = 200pF (Figure 3) SCLOUT, CL = 200pF (Figure 3)

l

l

l

40 40 40

300 250 250 250

ns ns ns ns

tF Fall Time SDA2, CL = 200pF (Figure 3) SDA1, RL = 1.1k, CL = 200pF (Figure 3) SCLOUT, CL = 200pF (Figure 3)

l

l

l

40 40

250 250 250

ns ns ns

tPWU Output Pulse Width Uncertainty SDA1, SDA2 (Note 2) –20 50 ns

tPZH, tPZL ONx Enable Time ON1 = ↑ to SDA1, RL = 1k, CL = 15pF (Figure 4) ON2 = ↑ to (SCLOUT, SDA2), CL = 15pF (Figure 4)

l

l

60 μs

tPHZ, tPLZ ONx Disable Time ON1 = ↓ to SDA1, RL = 1k, CL = 15pF (Figure 4) ON2 = ↓ to SCLOUT, RL = 1k, CL = 15pF (Figure 4) ON2 = ↓ to SDA2, RL = Open, CL = 15pF (Figure 4)

l

l

l

50 50

225

ns ns ns

tSP Pulse Width of Spikes Suppressed by Input Filter

l 0 50 ns


LTM2892

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VISO Rated Dielectric Insulation Voltage 1 Minute, Derived from 1 Second Test 1 Second (Notes 5, 6)

3500 4200

VRMS VRMS

Common Mode Transient Immunity VCC1 = VL1 = ON1 = 5V, VCC2 = VL2 = ON2 = 5V VCM = 1kV, ∆t = 20ns (Note 2)

50 kV/µs

VIORM Maximum Continuous Working Voltage

(Notes 2, 5) 850 600

VPEAK VRMS

Partial Discharge VPD = 1590VPEAK (Note 5) 5 pC

CTI Comparative Tracking Index IEC 60112 (Note 2) 600 VRMS

Depth of Erosion IEC 60112 (Note 2) 0.1 mm

DTI Distance Through Insulation (Note 2) 0.1 mm

Input to Output Resistance (Notes 2, 5) 1012 Ω

Input to Output Capacitance (Notes 2, 5) 3 pF

Creepage Distance (Note 2) 5 mm

isolaTion characTerisTics TA = 25°C

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: Guaranteed by design and not subject to production test.Note 3: Maximum data rate is guaranteed by other measured parameters and is not tested directly.

Note 4: This µModule isolator includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above specified maximum operating junction temperature may result in device degradation or failure.Note 5: Device is considered a 2-terminal device. Pin group A1 through B6 shorted together and pin group H1 through J6 shorted together.Note 6: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating.


LTM2892

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Typical perForMance characTerisTics

SDA1 Low Level Output Voltage vs Temperature

SDA2 Low Level Output Voltage vs Temperature

Supply Current vs INA to OUTA Data Rate


VCCx and VLx Supply Current vs Temperature

VCCx Supply Current vs Temperature

VLx Supply Current vs Temperature

TA = 25°C, VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2, unless otherwise noted.

Logic Input Threshold vs VLx Supply Voltage

Logic Output Voltage vs Load Current

TEMPERATURE (°C)–50

SUPP

LY C

URRE

NT (m

A)

3.8

3.6

3.4

3.2

3.0

2.8

2.6

2.4500 100

2892 G01

12525–25 75

LTM2892-SNO LOAD, REFRESH DATA ONLY

VCC1 = VL1 = 3.3VVCC2 = VL2 = 3.3VVCC1 = VL1 = 5VVCC2 = VL2 = 5V


SUPP

LY C

URRE

NT (m

A)

3.8

3.6

3.4

3.2

3.0

2.8

2.6

2.4500 100

2892 G02

12525–25 75

LTM2892-INO LOAD, REFRESH DATA ONLY

VCC1 = 3.3VVCC2 = 3.3VVCC1 = 5VVCC2 = 5V


SUPP

LY C

URRE

NT (µ

A)

350

300

250

200

150

100500 100

2892 G03

12525–25 75

LTM2892-INO LOAD, REFRESH DATA ONLY

VL1 = 3.3VVL2 = 3.3VVL1 = 5VVL2 = 5V

VLx SUPPLY VOLTAGE (V)1

THRE

SHOL

D VO

LTAG

E (V

)

3.5

2.5

0.5

1.0

2.0

3.0

1.5

04 52

2892 G04

63

INPUT RISING

INPUT FALLING

|LOAD CURRENT| (mA)0

OUTP

UT V

OLTA

GE (V

)

6

1

2

3

4

5

021 3

2892 G05

10987654

VLx = 5.5VVLx = 3.3VVLx = 1.62V


OUTP

UT V

OLTA

GE (V

)

0.5

0.4

0.3

0.2

0.1

0500 100

2892 G06

12525–25 75

LTM2892-ISDA1 RPU = 1.1k

VL1 = 3.3VVL1 = 5V


OUTP

UT V

OLTA

GE (V

)

0.5

0.4

0.3

0.2

0.1

0500 100

2892 G07

12525–25 75

LTM2892-I

VL2 = 3.3VVL2 = 5V

FREQUENCY (kHz)1

SUPP

LY C

URRE

NT (m

A)

16

14

12

10

6

8

4

2

0100

2892 G08

10000100010

LTM2892-SVCC1 = VL1 = 3.3VVCC2 = VL2 = 3.3V

ICC1, OUTA = ANY LOADICC2, OUTA = ANY LOADIL2, OUTA = NO LOADIL2, OUTA = 100pF LOAD

FREQUENCY (kHz)1

SUPP

LY C

URRE

NT (m

A)

16

14

12

10

6

8

4

2

0100

2892 G09

10000100010

LTM2892-SVCC1 = VL1 = 3.3VVCC2 = VL2 = 5V



LTM2892

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Typical perForMance characTerisTics

Supply Current vs Data Rate, All Channels






TA = 25°C, VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2, unless otherwise noted.

FREQUENCY (kHz)1

SUPP

LY C

URRE

NT (m

A)

16

14

12

10

6

8

4

2

0100

2892 G10

10000100010

LTM2892-SVCC1 = VL1 = 5VVCC2 = VL2 = 3.3V


FREQUENCY (kHz)1

SUPP

LY C

URRE

NT (m

A)

16

14

12

10

6

8

4

2

0100

2892 G11

10000100010

LTM2892-SVCC1 = VL1 = 5VVCC2 = VL2 = 5V


FREQUENCY (kHz)1

SUPP

LY C

URRE

NT (m

A)

20

14

16

18

12

10

6

8

4

2

0100

2892 G12

10000100010

LTM2892-SVCC1 = VL1 = 3.3VVCC2 = VL2 = 3.3V

ICC1 OR ICC2, ANY LOAD ALL CHANNELSIL1 OR IL2, NO LOAD EACH CHANNELIL1 OR IL2, 100pF LOAD ALL CHANNELS

FREQUENCY (kHz)1

SUPP

LY C

URRE

NT (m

A)

20

14

16

18

12

10

6

8

4

2

0100

2892 G13

10000100010

LTM2892-SVCC1 = VL1 = 3.3VVCC2 = VL2 = 5V

ICC1 OR ICC2, ANY LOAD, ALL CHANNELSIL1, NO LOAD, EACH CHANNELIL2, NO LOAD, EACH CHANNELIL1, 100pF LOAD, ALL CHANNELSIL2, 100pF LOAD, ALL CHANNELS

FREQUENCY (kHz)1

SUPP

LY C

URRE

NT (m

A)

20

14

16

18

12

10

6

8

4

2

0100

2892 G14

10000100010

LTM2892-SVCC1 = VL1 = 5VVCC2 = VL2 = 3.3V

ICC1 OR ICC2, ANY LOAD,ALL CHANNELSIL1, NO LOAD, EACH CHANNELIL2, NO LOAD, EACH CHANNELIL1, 100pF LOAD, ALL CHANNELSIL2, 100pF LOAD, ALL CHANNELS

FREQUENCY (kHz)1

SUPP

LY C

URRE

NT (m

A)

20

14

16

18

12

10

6

8

4

2

0100

2892 G15

10000100010

LTM2892-SVCC1 = VL1 = 5VVCC2 = VL2 = 5V

ICC1 OR ICC2, ANY LOAD, ALL CHANNELSIL1 OR IL2, NO LOAD, EACH CHANNELIL1 OR IL2, 100pF LOAD, ALL CHANNELS


LTM2892

92892fa


pin FuncTionsLogic Side

SCLIN (A1): Serial I2C Clock Input, Referenced to VL1 and GND1. Logic input connected to isolated side SCLOUT pin through the isolation barrier. Clock is unidirectional from logic to isolated side. Pull up to VL1 if not used.

SDA1 (A2, B2): Serial I2C Data Pins, Referenced to VL1 and GND1. Bidirectional logic pins connected to isolated side SDA2 pins through the isolation barrier. Under the condition of an isolation communication failure pins are in a high impedance state. Pins connected internally. Pull up to VL1 if not used.

INA (A3): Digital Input, Referenced to VL1 and GND1. Logic input connected to OUTA through the isolation barrier. The logic state on INA translates to the same logic state on OUTA. Connect to GND1 or VL1 if not used.

ON1 (A4): Enable, Referenced to VL1 and GND1. Enables data communication through the isolation barrier. If ON1 is high the part is enabled and communications are func-tional to the isolated side. If ON1 is low the logic side is held in reset, all digital outputs are in a high impedance state. Connect to VL1 if not driven.

VL1 (A5): Logic Supply. Interface supply voltage for pins SCLIN, INA, OUTB, OUTC, and ON1. Operating voltage is 3V to 5.5V. Internally bypassed with 0.22μF.

VCC1 (A6): Supply Voltage. Operating voltage is 3V to 5.5V. Internally bypassed with 1.0μF.

OUTB (B1): Digital Output, Referenced to VL1 and GND1. Logic output connected to INB through the isolation bar-rier. Under the condition of an isolation communication failure this output is in a high impedance state.

OUTC (B3): Digital Output, Referenced to VL1 and GND1. Logic output connected to INC through the isolation bar-rier. Under the condition of an isolation communication failure this output is in a high impedance state.

GND1 (B4 to B6): Circuit Ground.

Isolated Side

SCLOUT (H1): Serial I2C Clock Output, Referenced to VL2 and GND2. Logic output connected to logic side SCLIN pin through the isolation barrier. Clock is unidirectional from logic to isolated side. SCLOUT has a push-pull output stage; do not connect an external pull-up device. Under the condition of an isolation communication failure this output defaults to a high state.

SDA2 (H2, J2): Serial I2C Data Pins, Referenced to VL2 and GND2. Bidirectional logic pins connected to logic side SDA1 pins through the isolation barrier. Output is biased high by a 1.8mA current source. Do not connect an external pull-up device to SDA2. Under the condition of an isolation communication failure outputs default to a high state. Pins connected internally.

OUTA (H3): Digital Output, Referenced to VL2 and GND2. Logic output connected to INA through the isolation bar-rier. Under the condition of an isolation communication failure OUTA defaults to a high state.

GND2 (H3 to H5): Isolated Ground.

INB (J1): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTB through the isolation barrier. The logic state on INB translates to the same logic state on OUTB. Connect to GND2 or VL2 if not used.

INC (J3): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTC through the isolation barrier. The logic state on INC translates to the same logic state on OUTC. Connect to GND2 or VL2 if not used.

ON2 (J4): Enable, Referenced to VL2 and GND2. Enables data communication through the isolation barrier. If ON2 is high the part is enabled and communications are functional to the logic side. If ON2 is low the isolated side is held in reset, all digital outputs are in a high state. Connect to VL2 if not driven.

VL2 (J5): Logic Supply, Referred to GND2. Interface sup-ply voltage for pins SCLOUT, SDA2, INB, INC, OUTA, and ON2. Operating voltage is 3V to 5.5V. Internally bypassed with 0.22μF.

VCC2 (J6): Supply Voltage, Referred to GND2. Operating voltage is 3V to 5.5V. Internally bypassed with 1.0μF.

(LTM2892-I)


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pin FuncTionsLogic Side

INA (A1): Digital Input, Referenced to VL1 and GND1. Logic input connected to OUTA through the isolation barrier. The logic state on INA translates to the same logic state on OUTA. Connect to GND1 or VL1 if not used.

INB (A2): Digital Input, Referenced to VL1 and GND1. Logic input connected to OUTB through the isolation barrier. The logic state on INB translates to the same logic state on OUTB. Connect to GND1 or VL1 if not used.

INC (A3): Digital Input, Referenced to VL1 and GND1. Logic input connected to OUTC through the isolation barrier. The logic state on INC translates to the same logic state on OUTC. Connect to GND1 or VL1 if not used.

ON1 (A4): Enable, Referenced to VL1 and GND1. Enables data communication through the isolation barrier. If ON1 is high the part is enabled and communications are func-tional to the isolated side. If ON1 is low the logic side is held in reset, all digital outputs are in a high impedance state. Connect to VL1 if not driven.

VL1 (A5): Logic Supply. Interface supply voltage for pins INA, INB, INC, OUTD, OUTE, OUTF, EOUTD, and ON1. Operating voltage is 1.62V to 5.5V. Internally bypassed with 0.22μF.

VCC1 (A6): Supply Voltage. Operating voltage is 3V to 5.5V. Internally bypassed with 1.0μF.

OUTD (B1): Digital Output, Referenced to VL1 and GND1. Logic output connected to IND through the isolation bar-rier. Under the condition of an isolation communication failure this output is in a high impedance state.

OUTE (B2): Digital Output, Referenced to VL1 and GND1. Logic output connected to INE through the isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state.

OUTF (B3): Digital Output, Referenced to VL1 and GND1. Logic output connected to INF through the isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state.

EOUTD (B4): Digital Output Enable, Referenced to VL1 and GND1. A logic high on EOUTD places the logic side OUTD pin in a high impedance state, a logic low enables the output. Connect to GND1 or VL1 if not used.

GND1 (B5, B6): Circuit Ground.

(LTM2892-S)

Isolated Side

OUTA (H1): Digital Output, Referenced to VL2 and GND2. Logic output connected to INA through the isolation bar-rier. Under the condition of an isolation communication failure OUTA defaults to a low state.

OUTB (H2): Digital Output, Referenced to VL2 and GND2. Logic output connected to INB through the isolation bar-rier. Under the condition of an isolation communication failure OUTB defaults to a low state.

OUTC (H3): Digital Output, Referenced to VL2 and GND2. Logic output connected to INC through the isolation bar-rier. Under the condition of an isolation communication failure OUTC defaults to a high state.

EOUTA (H4): Digital Output Enable, Referenced to VL2 and GND2. A logic high on EOUTA places the logic side OUTA pin in a high impedance state, a logic low enables the output. Connect to GND2 or VL2 if not used.

GND2 (H5, H6): Isolated Ground.

IND (J1): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTD through the isolation barrier. The logic state on IND translates to the same logic state on OUTD. Connect to GND2 or VL2 if not used.

INE (J2): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTE through the isolation barrier. The logic state on INE translates to the same logic state on OUTE. Connect to GND2 or VL2 if not used.

INF (J3): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTF through the isolation barrier. The logic state on INF translates to the same logic state on OUTF. Connect to GND2 or VL2 if not used.

ON2 (J4): Enable, Referenced to VL2 and GND2. Enables data communication through the isolation barrier. If ON2 is high the part is enabled and communications are functional to the logic side. If ON2 is low the isolated side is held in reset, OUTA and OUTB are in a low state, and OUTC is in a high state. Connect to VL2 if not driven.

VL2 (J5): Logic Supply, Referred to GND2. Interface supply voltage for pins OUTA, OUTB, OUTC, IND, INE, INF, EOUTA, and ON2. Operating voltage is 1.62V to 5.5V. Internally bypassed with 0.22μF.

VCC2 (J6): Supply Voltage, Referred to GND2. Operating voltage is 3V to 5.5V. Internally bypassed with 1.0μF.


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block DiagraMs

LTM2892-I

LTM2892-I

2892 BD1

ISOL

ATED

COM

MUN

ICAT

IONS

INTE

RFAC

E

ISOL

ATED

COM

MUN

ICAT

IONS

INTE

RFAC

E

0.22µF 0.22µF

VL1

VCC1

GND1

ON1

SCLIN

SDA1

INA

1µF 1µF

OUTB

SDA1

OUTC

VL2

VCC2

GND2

ON2

SCLOUT

SDA2

OUTA

INB

SDA2

INC


LTM2892

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LTM2892-S

block DiagraMs

ISOL

ATED

COM

MUN

ICAT

IONS

INTE

RFAC

E

ISOL

ATED

COM

MUN

ICAT

IONS

INTE

RFAC

E

0.22µF 0.22µF

VL1

VCC1

GND1

ON1

INA

EOUTD

INB

INC

1µF 1µF

OUTD

OUTE

OUTF

VL2

VCC2

GND2

ON2

OUTA

EOUTA

OUTB

OUTC

IND

INE

INF

LTM2892-S

2892 BD2


LTM2892

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TesT circuiTs

Figure 1. Logic Timing Measurements

Figure 2. Logic Enable/Disable Time

INx

OUTPUT

CLtPLH tPHL

tR tF

90%

10%

10%

90%½VL2

½VL1

VL1

VOL

VOH

0V

INx

OUTx

INx

OUTx

CL

2892 F01

tPLH tPHL

tR tF

90%

10%

10%

90%½VL1

½VL2

VL2

VOL

VOH

0V

INx

OUTx

2892 F02

EOUTD

tPZH

tPZL

tPHZ

tPLZ

VOL + 0.5V

VOH – 0.5V

½VL1

VL1

VOH

VOL

0V

0VVL1

OUTD

OUTD

EOUTD

½VL1

½VL1

OUTD

VL1 OR 0V

IND

CL

RL

EOUTA

tPZH

tPZL

tPHZ

tPLZ

VOL + 0.5V

VOH – 0.5V

½VL2

VL2

VOH

VOL

0V

0VVL2

OUTA

OUTA

EOUTA

½VL2

½VL2

INA

VL2 OR 0V

OUTA

CL

RL


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TesT circuiTs

Figure 4. ONx Enable/Disable Time

Figure 3. I2C Timing Measurements

tPHL tPLH

tF tR

30%½VL1 70%

70%

30%VOL

VOH

SDA1

SDA2

CL

VL1

VOL

VOH

0V

SDA1

SDA2

VL1

RL

2892 F03

½VL2

tPHL tPLH

tF tR

30%½VL2 70%

70%

30%

½VL1

VL2

0V

SDA2

SDA1

SDA1

CL

VL1

RL

SDA2

2892 F04

ON1

tPZH

tPZL

tPHZ

tPLZ

VOL + 0.5V

VOH – 0.5V

½VL1

VL1

VOH

VOL

0V

0VVL1

OUTx

OUTx

ON1

½VL1

½VL1

OUTx

VL1 OR 0V

INx

CL

RL

ON2

tPZH

tPZL

tPHZ

tPLZ

VOL + 0.5V

VOH – 0.5V

½VL2

VL2

VOH

VOL

0V

0VVL2

OUTx

OUTx

ON2

½VL2

½VL2

INx OUTx

CL

VL2 OR 0V

RL


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applicaTions inForMaTion

Figure 5. Supplies Are Independent

Logic Supplies (VL1, VL2)

Separate logic supply pins, VL1 and VL2, allow the LTM2892 to interface with any logic signal from 1.62V to 5.5V for the SPI version and 3V to 5.5V for the I2C version, as shown in Figure 5. Simply connect the desired logic supplies to VL1 and VL2.

There is no interdependency between VCC1, VCC2, VL1, and VL2; they may simultaneously operate at any voltage within their specified operating ranges and sequence in any order. VL1 and VL2 are bypassed internally by 0.22µF capacitors.

Hot Plugging Safely

Caution must be exercised in applications where power is plugged into the LTM2892’s power supplies, VCC1, VCC2, VL1, or VL2 due to the integrated ceramic decoupling capacitors. The parasitic cable inductance along with the high Q characteristics of ceramic capacitors can cause substantial ringing which could exceed the maximum voltage ratings and damage the LTM2892. Refer to Ap-plication Note 88, entitled “Ceramic Input Capacitors Can Cause Overvoltage Transients” for a detailed discussion and mitigation of this phenomenon.

VCC1VL1ON1EOUTDINAINBINC

OUTDOUTEOUTF

3V TO 5.5V3V TO 5.5V

1.62V TO 5.5VVCC2VL2ON2

EOUTAOUTAOUTBOUTC

INDINEINF

LTM2892-S

GND2GND1

ISOL

ATIO

N BA

RRIE

R

2892 F05

MISO

SCKMOSISS

EXTERNALDEVICE

1.62V TO 5.5V

EXTERNALDEVICE

SCKMOSI

SS

MISO

Overview

The LTM2892 digital µModule isolator provides a gal-vanically-isolated robust logic interface, complete with decoupling capacitors. The LTM2892 is ideal for use in networks where grounds can take on different voltages. Isolation in the LTM2892 blocks high voltage differences and eliminates ground loops, and is extremely tolerant of common mode transients between ground planes. Error-free operation is maintained through common mode events as fast as 50kV/μs providing excellent noise isolation.

Input Supplies (VCC1, VCC2)

The LTM2892 is powered by 3V to 5.5V supplies on each side of the isolation interface. The input supplies provide power to the internal isolated communications interface and are completely independent of the logic power sup-plies. VCC1 and VCC2 are each bypassed with 1.0µF ceramic capacitors.


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applicaTions inForMaTionChannel Timing Uncertainty

Multiple channels are supported across the isolation bound-ary by encoding and decoding of the inputs and outputs. Up to three signals in each direction are assembled as serial packets and transferred across the isolation barrier. The time required to transfer all three bits is 100ns maximum, and sets the limit for how often a signal can change on the opposite side of the barrier. Encoding and transmission is independent for each data direction. The technique used assigns INA(-S) or SCL(-I) on the logic side, and IND(-S) or INB(-I) on the isolated side, the highest priority such that there is no jitter on the associated output channels, only delay. This preemptive scheme will produce a certain amount of uncertainty on the other isolation channels. The resulting pulse width uncertainty on these low priority channels is typically ±6ns, but may vary up to ±44ns if the low priority channels are not encoded within the same high priority serial packet.

Serial Peripheral Interface (SPI) Bus

The LTM2892-S provides an SPI compatible isolated interface. The maximum data rate is a function of the inherent channel propagation delays, channel to channel pulse width uncertainty, and data direction requirements. Channel timing is detailed in Figures 6 through 9 and Tables 2 and 3. The SPI protocol supports four unique timing configurations defined by the clock polarity (CPOL) and clock phase (CPHA) summarized in Table 1.

Table 1. SPI ModeCPOL CPHA DATA TO (CLOCK) RELATIONSHIP

0 0 Sample (Rising) Setup (Falling)

0 1 Setup (Rising) Sample (Falling)

1 0 Sample (Falling) Setup (Rising)

1 1 Setup (Falling) Sample (Rising)

The maximum data rate for bidirectional communication is 4MHz, based on a synchronous system, as detailed in the timing waveforms. Slightly higher data rates may be achieved by skewing the clock duty cycle and minimizing the SDO to SCK setup time, however the clock rate is still dominated by the system propagation delays. A discussion of the critical timing paths relative to Figures 6 and 7 fol-lows. For SPI communication INA = SCK, INB = SDI, INC

= CS, IND = SDO2, OUTA = SCK2, OUTB = SDI2, OUTC = CS2, and OUTD = SDO.

• CS to SCK (master sample SDO, 1st SDO valid)

t0 → t1 ≈50ns, CS to CS2 propagation delay t1 → t1+ Isolated slave device propagation

(response time), asserts SDO2 t1 → t3 ≈50ns, SDO2 to SDO propagation delay

t3 → t5 Setup time for master SDO to SCK

• SDI to SCK (master data write to slave) t2 → t4 ≈50ns, SDI to SDI2 propagation delay t5 → t6 ≈50ns, SCK to SCK2 propagation delay t2 → t5 ≥50ns, SDI to SCK, separate packet

non-zero setup time t4 → t6 ≥50ns, SDI2 to SCK2, separate packet

non-zero setup time

• SDO to SCK (master sample SDO, subsequent SDO valid)

t8 Setup data transition SDI and SCK t8 → t10 ≈50ns, SDI to SDI2 and SCK to SCK2

propagation delay t10 SDO2 data transition in response to

SCK2 t10 → t11 ≈50ns, SDO2 to SDO propagation delay

t11 → t12 Setup time for master SDO to SCK

Maximum data rate for single direction communication, master to slave, is 8MHz, limited by the systems encod-ing/decoding scheme or propagation delay. Timing details for both variations of clock phase are shown in Figures 8 and 9 and Table 3.

Additional requirements to insure maximum data rate are:

• CS is transmitted prior to (asynchronous) or within the same (synchronous) data packet as SDI

• SDI and SCK setup data transition occur within the same data packet. Referencing Figure 6, SDI can pre-cede SCK by up to 13ns (t7 → t8) or lag SCK by 3ns (t8 → t9) and not violate this requirement. Similarly in Figure 8, SDI can precede SCK by up to 13ns (t4 → t5) or lag SCK by 3ns (t5 → t6).


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Figure 6. SPI Timing, Bidirectional, CPHA = 0

Figure 7. SPI Timing, Bidirectional, CPHA = 1

2892 F06

CPHA = 0

CS = EOUTD

CS2

SDI

SDI2

SDO

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14

INVALID

SDO2

SCK (CPOL = 0)

SCK2 (CPOL = 0)

SCK (CPOL = 1)

SCK2 (CPOL = 1)

t15 t17 t18

2892 F07

INVALID

CPHA = 1

CS = EOUTD

CS2

SDI

SDI2

SDO

SDO2

SCK (CPOL = 0)

SCK2 (CPOL = 0)

SCK (CPOL = 1)

SCK2 (CPOL = 1)

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t17t16 t18



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Table 2. Bidirectional SPI Timing Event DescriptionTIME CPHA EVENT DESCRIPTION

t0 0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output enabled, initial data is not equivalent to slave device data output.

t0-t1, t17-t18 0, 1 Propagation delay chip select, logic to isolated side, 50ns typical.

t1 0, 1 Slave device chip select output data enable.

t2 0 Start of data transmission, data setup.

1 Start of transmission, data and clock setup. Data transition must be within –13ns to 3ns of clock edge.

t1-t3 0, 1 Propagation delay of slave data, isolated to logic side, 50ns typical.

t3 0, 1 Slave data output valid, logic side.

t2-t4 0 Propagation delay of data, logic side to isolated side.

1 Propagation delay of data and clock, logic side to isolated side.

t5 0, 1 Logic side data sample time, half clock period delay from data setup transition.

t5-t6 0, 1 Propagation delay of clock, logic to isolated side.

t6 0, 1 Isolated side data sample time.

t8 0, 1 Synchronous data and clock transition, logic side.

t7-t8 0, 1 Data to clock delay, must be ≤ 13ns.

t8-t9 0, 1 Clock to data delay, must be ≤ 3ns.

t8-t10 0, 1 Propagation delay clock and data, logic to isolated side.

t10, t14 0, 1 Slave device data transition.

t10-t11, t14-t15 0, 1 Propagation delay slave data, isolated to logic side.

t11-t12 0, 1 Slave data output to sample clock setup time.

t13 0 Last data and clock transition logic side.

1 Last sample clock transition logic side.

t13-t14 0 Propagation delay data and clock, logic to isolated side.

1 Propagation delay clock, logic to isolated side.

t15 0 Last slave data output transition logic side.

1 Last slave data output and data transition, logic side.

t15-t16 1 Propagation delay data, logic to isolated side.

t17 0, 1 Asynchronous chip select transition, end of transmission. Disable slave data output logic side.

t18 0, 1 Chip select transition isolated side, slave data output disabled.



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Figure 8. SPI Timing, Unidirectional, CPHA=0

Figure 9. SPI Timing, Unidirectional, CPHA=1

2892 F06

CPHA = 0

CS = EOUTD

CS2

SDI

SDI2

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t11 t12

SCK (CPOL = 0)

SCK2 (CPOL = 0)

SCK (CPOL = 1)

SCK2 (CPOL = 1)

2892 F09

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t11t10 t12

CPHA = 1

CS = EOUTD

CS2

SDI

SDI2

SCK (CPOL = 0)

SCK2 (CPOL = 0)

SCK (CPOL = 1)

SCK2 (CPOL = 1)


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Table 3. Unidirectional SPI Timing Event DescriptionTIME CPHA EVENT DESCRIPTION

t0 0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns.

t0-t1 0, 1 Propagation delay chip select, logic to isolated side.

t2 0 Start of data transmission, data setup.

1 Start of transmission, data and clock setup. Data transition must be within –13ns to 3ns of clock edge.

t2-t3 0 Propagation delay of data, logic side to isolated side.

1 Propagation delay of data and clock, logic side to isolated side.

t3 0, 1 Logic side data sample time, half clock period delay from data setup transition.

t3-t5 0, 1 Clock propagation delay, clock and data transition.

t4-t5 0, 1 Data to clock delay, must be ≤ 13ns.

t5-t6 0, 1 Clock to data delay, must be ≤ 3ns.

t5-t7 0, 1 Data and clock propagation delay.

t8 0 Last clock and data transition.

1 Last clock transition.

t8-t9 0 Clock and data propagation delay.

1 Clock propagation delay.

t9-t10 1 Data propagation delay.

t11 0, 1 Asynchronous chip select transition, end of transmission.

t12 0, 1 Chip select transition isolated side.



LTM2892

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Inter-IC Communication (I2C) Bus

The LTM2892-I provides an isolated I2C compatible inter-face supporting master mode only, with a unidirectional clock (SCLIN), and bidirectional data (SDA1). The maxi-mum data rate is 400kHz which supports fast-mode I2C. Timing is detailed in Figure 10. The data rate is limited by the slave acknowledge setup time (tSU;ACK), consisting of the I2C standard minimum setup time (tSU;DAT) of 100ns, maximum clock propagation delay of 225ns, glitch filter and isolated data delay of 500ns maximum, and the combined isolated and logic data fall time of 300ns at maximum bus loading. The total setup time reduces the I2C data hold time (tHD;DAT) to a maximum of 175ns, guaranteeing sufficient data setup time (tSU;ACK).

applicaTions inForMaTionThe isolated side bidirectional serial data pin, SDA2, simplified schematic is shown in Figure 11. An internal 1.8mA current source provides a pull-up for SDA2. Do not connect any other pull-up device to SDA2. This current source is sufficient to satisfy the system requirements for bus capacitances greater than 200pF in fast mode and greater than 400pF in standard mode.

Additional proprietary circuitry monitors the slew rate on the SDA1 and SDA2 signals to manage directional control across the isolation barrier. Slew rates on both pins must be greater than 1V/μs for proper operation.

Figure 10. I2C Timing Diagram

Figure 11. Isolated SDA2 Pin Schematic

2892 F11

SDA2

1.8mAGLITCHFILTER

TO LOGIC SIDE

FROM LOGIC SIDE

2892 F10

tPROPtSU;DAT

SDA1

SDA2

SCLIN

SCLOUT

tHD;DAT

tSU;ACKSTOPSTART

SLAVE ACK

981


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The logic side bidirectional serial data pin, SDA1, requires a pull-up resistor or current source connected to VL1. Follow the requirements in Figures 12 and 13 for the appropriate pull-up resistor on SDA1 that satisfies the desired rise time specifications and VOL maximum limits for fast and standard modes. The resistance curves represent the maximum resistance boundary; any value may be used to the left of the appropriate curve.

The isolated side clock pin, SCLOUT, has a weak push-pull output driver; do not connect an external pull-up device. SCLOUT is compatible with I2C devices without clock stretching. On lightly loaded connections, a 100pF

applicaTions inForMaTioncapacitor from SCLOUT to GND2 or RC lowpass filter (R = 500Ω, C = 100pF) can be used to decrease the rise and fall times and minimize noise.

Some consideration must be given to signal coupling between SCLOUT and SDA2. Separate these signals on a printed circuit board or route with ground between. If these signals are wired off board, twist SCLOUT with VL2 and/or GND2 and SDA2 with GND2 and/or VL2; do not twist SCLOUT and SDA2 together. If coupling between SCLOUT and SDA2 is unavoidable, place the aforementioned RC filter at the SCLOUT pin to reduce noise injection onto SDA2.

Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA1

Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA1

CBUS (pF)10

R PUL

L-UP

(kΩ

)

30

25

15

10

20

5

0100

2892 F12

1000

VL1 = 3.0VVL1 = 3.3VVL1 = 3.6VVL1 = 4.5V TO 5.5V

CBUS (pF)10

R PUL

L-UP

(kΩ

)

10

9

7

6

8

5

3

2

4

1

0100

2892 F13

1000

VL1 = 3.0VVL1 = 3.3VVL1 = 3.6VVL1 = 4.5V TO 5.5V


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applicaTions inForMaTionCommon Mode Transient Immunity (CMTI)

The minimum specified common mode transient immunity for the LTM2892 is 50kV/µs, with typical performance of 70kV/µs. This rating applies to the LTM2892 while actively transmitting data across the isolation barrier as shown in Figures 14 through 16.

The following oscilloscope screen capture characteristics apply to all figures related to the discussion of CMTI. The topmost trace input signal on INA, the trace immediately below is output signal on OUTD, data is looped on the isolated side (OUTA tied to IND), and the bottom trace is the common mode transient applied from GND2 to GND1. All data was captured using infinite persistence unless oth-erwise noted. The common mode transient repetition rate is 10Hz. Measurements were done using the LTM2892-S with VCC1 = VL1 = 5V, and VCC2 = VL2 at approximately 4.7V under battery power. Figures 16 and 18 show the actual transient rate of change using data averaging.

This exceptional level of transient immunity is a direct result of the differential receiver and center tapped data coils employed in the isolated data communication system. Figure 17 shows the LTM2892 in a static data state in the presence of 200kV/µs transients with no state change or system latch-up. The system is known to be in a static state since the data changed approximately 600ns prior to the transient; the internal data refresh which guarantees the correct DC state does not occur until 1.2µs after the last transition.

Figure 18 shows 200kV/µs transients occurring in a data communication interval, just prior to data transmission across the isolation barrier.

For transients greater than 70kV/µs it is possible to corrupt the dynamic data communication. In this case the output

data may be incorrect for up to one data refresh period. This situation is shown in Figure 19. The output state is automatically corrected after approximately 1.2µs.

The output data states may also be corrupted for transients greater than 70kV/µs, if the common mode transient aligns with the refresh data transmission. Figures 20 and 21 show data corruption for one refresh period with common mode transients of 200kV/µs.

RF, Magnetic Field Immunity

The isolator µModule technology used within the LTM2892 has been independently evaluated, and successfully passed the RF and magnetic field immunity testing requirements per European Standard EN 55024, in accordance with the following test standards:

EN 61000-4-3 Radiated, radio-frequency, electromagnetic field immunity

EN 61000-4-8 Power frequency magnetic field immunity

EN 61000-4-9 Pulsed magnetic field immunity

Tests were performed using an unshielded test card de-signed per the data sheet PCB layout recommendations. Specific limits per test are detailed in Table 4.

Table 4. EMC Immunity TestsTEST FREQUENCY FIELD STRENGTH

EN 61000-4-3 Annex D 80MHz to 1GHz 10V/m

1.4MHz to 2GHz 3V/m

2GHz to 2.7GHz 1V/m

EN 61000-4-8 Level 4 50Hz and 60Hz 30A/m

EN 61000-4-8 Level 5 60Hz 100A/m*

EN 61000-4-9 Level 5 Pulse 1000A/m

* Non IEC method.


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Figure 14. Operation with Repetitive Bursts of Common Mode Transients, 50kV/µs

Figure 16. Transient dV/dT, 70kV/µsFigure 15. 70kV/µs Transient Operation Coincident with Data Transmission/Reception

Figure 17. Static Operation with 200kV/µs Transients

Figure 18. 200kV/µs Transient Prior to Data Transmission

Figure 20. Common Mode Transient (200kV/µs) Coincident with Data Refresh, Data Low

Figure 21. Common Mode Transient (200kV/µs) Coincident with Data Refresh, Data High

Figure 19. Data Refresh Recovery for 200kV/µs Transient

20ns/DIV

5V/DIV

200V/DIV

5V/DIV

2892 F14

INAOUTD

CMT

20ns/DIV

5V/DIV

200V/DIV

5V/DIV

2892 F15

INA

OUTD

CMT

100ns/DIV

5V/DIV

500V/DIV

5V/DIV

2892 F17

INA

OUTD

CMT

200ns/DIV

5V/DIV

500V/DIV

5V/DIV

2892 F19

INA

OUTD

CMT

400ns/DIV

5V/DIV

500V/DIV

5V/DIV

2892 F20

INA

OUTD

CMT

400ns/DIV

5V/DIV

500V/DIV

5V/DIV

2892 F21

INA

OUTD

CMT

20ns/DIV

5V/DIV

200V/DIV

20kV/µs/DIV

5V/DIV

2892 F16

INA OUTD

dV/dT

CMT

20ns/DIV

5V/DIV

500V/DIV

50kV/µs/DIV

5V/DIV

2892 F18

INA OUTD

CMT

dV/dT


LTM2892

252892fa


applicaTions inForMaTionPCB Layout

The high integration of the LTM2892 makes PCB layout very simple. However, to optimize its electrical isolation characteristics and EMI performance, some layout con-siderations are necessary.

• Input and output supply decoupling is not required, since these components are integrated within the package. An additional polarized bulk capacitor with a value of 3.3µF to 10µF is recommended. The high ESR of this capacitor reduces board resonances and minimizes voltage spikes caused by hot plugging of the supply voltage. For EMI sensitive applications, an additional low ESL ceramic capacitor of 1µF to 4.7µF, placed as close to the power and ground terminals as possible, is recommended. Alternatively, a number of smaller value parallel capacitors may be used to reduce ESL and achieve the same net capacitance.

• Do not place copper on the PCB between the inner columns of pads. This area must remain open to withstand the rated isolation voltage.

• The use of solid ground planes for GND1 and GND2 is recommended for non-EMI critical applications to optimize signal fidelity, and minimize RF emissions due to uncoupled PCB trace conduction. The drawback of using ground planes, where EMI is of concern, is the creation of a dipole antenna structure which can radiate differential voltages formed between GND1 and GND2. If ground planes are used it is recommended to minimize their area, and use contiguous planes as any openings or splits can exacerbate RF emissions.

• For large ground planes a small capacitance (≤ 330pF) from GND1 to GND2, either discrete or embedded within the substrate, provides a low impedance cur-rent return path for the module parasitic capacitance, minimizing any high frequency differential voltages and substantially reducing radiated emissions. Discrete capacitance will not be as effective due to parasitic ESL. In addition, voltage rating, leakage, and clear-ance must be considered for component selection. Embedding the capacitance within the PCB substrate provides a near ideal capacitor and eliminates com-ponent selection issues; however, the PCB must be 4 layers. Care must be exercised in applying either technique to ensure the voltage rating of the barrier is not compromised.

• In applications without an embedded PCB substrate capacitance, a slot may be added between the logic side and isolated side device pins. The slot extends the creepage path between terminals on the PCB side, and may reduce leakage caused by PCB contamination. The slot should be placed in the middle of the device and extend beyond the package perimeter.

The PCB layout in Figures 22a and 22b shows the demo boards for the LTM2892.

EMI performance is shown in Figure 23, measured using a gigahertz transverse electromagnetic (GTEM) cell and method detailed in IEC 61000-4-20, “Testing and Mea-surement Techniques – Emission and Immunity Testing in Transverse Electromagnetic Waveguides.”


LTM2892

262892fa


Figure 22a. LTM2892-S Demo Board Layout (DC1957A)



LTM2892

272892fa



Figure 22b. LTM2892-I Demo Board Layout (DC1986A)


LTM2892

282892fa


Figure 23. LTM2892 Demo Board Emissions


FREQUENCY (MHz)0

dVµV

/m

60

50

30

40

20

10

0

–10

–20

–30500200 700

2892 F23

1000300 400100 600 900800

DETECTOR = PEAK HOLD, RBW = 120kHz, VBW = 300kHzSWEEP TIME = 680ms, ≥10 SWEEPS# OF POINTS = 501

DUT

CISPR 22 CLASS B LIMIT


LTM2892

292892fa


Typical applicaTions

VCCVL

ONSDOECSSDISCKDO2SDODO1GND

V+

AV+

V–

AV–

VCC2AVCC2

CS2SDI2SCK2

I2SDO2

I1GND2

B8A8

A7A6A5A4A3A2A1B1B2

L8K8L7K7L6K6L5L4L3L2L1K1K2

5V1.62V TO 5V

C2C1C0

C5C4C3

C7C6

E2E1E0

E5E4E3

E7E6

D5D4D3

D7D6

D2D0D1

F5F4F3

F7F6

F2F0F1

DIGITALOUTPUTS

LTM2883-5S

ISOL

ATIO

N BA

RRIE

RVCCVL1ON1OUTFOUTEOUTDINCINBINAEOUTDGND1GND1

VCC2VL2

ON2INFINEIND

OUTCOUTBOUTA

EOUTAGND2GND2

A6A5A4B3B2B1A3A2A1B4B5B6

J6J5J4J3J2J1H3H2H1H4H5H6

LTM2892-S

ISOL

ATIO

N BA

RRIE

R

VCC1VL1ON1OUTFOUTEOUTDINCINBINAEOUTDGND1GND1

VCC2VL2

ON2INFINEIND

OUTCOUTBOUTA

EOUTAGND2GND2

A6A5A4B3B2B1A3A2A1B4B5B6

J6J5J4J3J2J1H3H2H1H4H5H6

LTM2892-S

ISOL

ATIO

N BA

RRIE

R

2892 F16

C0C1C2C3C4C5C6C7

D0D1D2D3D4D5D6D7

E0E1E2E3E4E5E6E7

F0F1F2F3F4F5F6F7

DIGITALINPUTS

DIGITALINPUTS

DIGITALOUTPUTS

D[0:

7]

F[0:

7]

C[0:

7]

E[0:

7]

Figure 24. High Speed Bidirectional 8-Bit Parallel Isolator


LTM2892

302892fa



VCCVL

ONSDOECSSDISCKDO2SDODO1GND

V+

AV+

V–

AV–

VCC2AVCC2

CS2SDI2SCK2

I2SDO2

I1GND2

B8A8

A7A6A5A4A3A2A1B1B2

L8K8L7K7L6K6L5L4L3L2L1K1K2

5V

SSAMOSI

SCK

MISO

SSD

SSC

SSB

LTM2883-5S

ISOL

ATIO

N BA

RRIE

R

VCC1VL1ON1OUTFINCOUTEINBOUTDINAEOUTDGND1GND1

VCC2VL2

ON2INF

OUTCINE

OUTBIND

OUTAEOUTAGND2GND2

A6A5A4B3A3B2A2B1A1B4B5B6

J6J5J4J3H3J2H2J1H1H4H5H6

LTM2892-S

ISOL

ATIO

N BA

RRIE

R

2892 F17

SSMOSIMISOSCK

DEVICE A4.7k

SSMOSIMISOSCK

DEVICE B

SSMOSIMISOSCK

DEVICE C

SSMOSIMISOSCK

DEVICE D

Figure 25. Isolated SPI Interface with Multiple Chip Select


LTM2892

312892fa



VCC1VL1ON1OUTCINASDA1SDA1OUTBSCLINGND1GND1GND1

VCC2VL2

ON2INC

OUTASDA2SDA2

INBSCLOUT

GND2GND2GND2



LTM2892-I

D2

ISOL

ATIO

N BA

RRIE

R

2892 F18

•

•

•C510µF

C42.2nF

D11N4148W

R82k

5V1

COM1

SDA1

SCL1

5k


VCC2VL2

ON2INC

OUTASDA2SDA2

INBSCLOUT

GND2GND2GND2



LTM2892-I

ISOL

ATIO

N BA

RRIE

R

C610µF

5V2

COM2

SDA2

SCL2

•


VCC2VL2

ON2INC

OUTASDA2SDA2

INBSCLOUT

GND2GND2GND2



LTM2892-I

ISOL

ATIO

N BA

RRIE

R

C710µF

5V3

COM3

SDA3

SCL3

•

VCC1VL1

ON1OUTC

INASDA1SDA1OUTBSCLINGND1GND1GND1

VCC2VL2ON2INCOUTASDA2SDA2INBSCLOUTGND2GND2GND2



LTM2892-I

D6

D5 D4

D3

ISOL

ATIO

N BA

RRIE

R

5V5

COM5

SDA5

SCL5

5k

SHDNTCRILIMSSVC

1314

4

715111012

RFBRREF

SW

TEST

GND

GND

GND

GND

GND

GND

5 6

2 3 1 16 17 8 9

VIN

BIAS

C110µF

R1200k

R290.9k

R86.04k

R326.1k

R756.2kR6

10k

R526.1k

C31.5nF

C410nF

LT3574

C910µF

•

VCC1VL1

ON1OUTC

INASDA1SDA1OUTBSCLINGND1GND1GND1

VCC2VL2ON2INCOUTASDA2SDA2INBSCLOUTGND2GND2GND2



LTM2892-I

ISOL

ATIO

N BA

RRIE

R

5V4

COM4

SDA4

SCL4

C810µF

5V

5V

5V

5V

TR1:E

TR1:F

TR1: WÜRTH ELEKTRONIK 749196111D2-D6: DIODES, INC. B0520LW

TR1:D

TR1:C

5V

5V

SDA

SCL

TR1:BTR1:A

Figure 26. Parallel Multi-Zone Isolated I2C Interface


LTM2892

322892fa



D2ES1D

•

• 50V

50V

VCC1VL1

ON1OUTF

INCOUTE

INBOUTD

INAEOUTDGND1GND1

VCC2VL2ON2INFOUTCINEOUTBINDOUTAEOUTAGND2GND2



LTM2892-S

ISOL

ATIO

N BA

RRIE

R

SHDNTCRILIMSSVC

1314

4

715111012

RFBRREF

SW

TEST

GND

GND

GND

GND

GND

GND

5 6

OxCS

MOSI

SCKMISO

Ox

2 3 1 16 17 8 9

V IN

BIAS

C110µF

C54.7nF

R46.04k

R3124k

D1

R320k

R610k

R5249k

C2220pF

R750k

C32.2nF

C410nF

LT3574

5V

T1

1:2

150µH C61µF

5V

VCC

µC

GND

1µF

CSSDOSDISCKA3A2A1A0GPIO2GPIO1WDTMMTOSVREGVREFVTEMP2VTEMP1NCV–S1C1S2

12345678910111213141516171819202122

44434241403938373635343332313029282726252423

V+

C12S12C11S11C10S10C9S9C8S8C7S7C6S6C5S5C4S4C3S3C2

1M

100k

1M 1M

1µF

1µF

100k

100k

100k

LTC6803-2

2892 F19T1: BH ELECTRONICS L10-0111D1: DIODES INC. 1N4148WT-7

Figure 27. Battery Stack Monitor with Isolated SPI Interface


LTM2892

332892fa



Figure 28. –48V, 200W Hot Swap™ Controller with Isolated I2C Interface


VCC2VL2

ON2INC

OUTASDA2SDA2

INBSCLOUT

GND2GND2GND2



LTM2892-I

ISOL

ATIO

N BA

RRIE

R

OX

SDAIX

SCL

10k

5V

VCC

µC

GND

1µF

2892 F20

10k

UVLUVH

ADIN2OVSSTMRENPGIADR1ADR0

2265432

282723

PWRGD2PWRGD1

89

10111920261

2524

FLTINSCL

SDAISDAO

ALERTON

PGIOPG

ADIN

INTVCC VIN

SENSE47nF

VEE DRAIN RAMPGATE

LTC4261CGN

0.1µF

220nF

0.1µF

13 14 15

7 21

16 18

47nF

1µF

4× 1k IN SERIES1/4W EACH

100nF

–48V RTN

–48V INPUT

0.008Ω1%

10nF100V

1k1M

10k 402k

10Ω

IRF1310NS

453k

16.9k

11.8k

VEE

VOUT

VEE

+ 330µF100V

10k


LTM2892

342892fa




VCC2VL2

ON2INC

OUTASDA2SDA2

INBSCLOUT

GND2GND2GND2



LTM2892-I

ISOL

ATIO

N BA

RRIE

R2k

3.3V

SDA

SCL

VCCADR1ADR0SCLSDA

12345

109876

V1V2V3V4

GND

LTC2990

3V TO 5V0.01Ω

ILOAD0A TO 1A

2892 F21

2k

470pF

MMBT3904

Figure 29. Isolated I2C Voltage, Current and Temperature Power Supply Monitor


LTM2892

352892fa


Typical applicaTionsV C

C1V L

1ON

1OU

TCIN

ASD

A1SD

A1OU

TBSC

LIN

GND1

GND1

GND1

V CC2 V L

2ON

2IN

COU

TASD

A2SD

A2 INB

SCLO

UTGN

D2GN

D2GN

D2

J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6

A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6

LTM

2892

-I

ISOLATION BARRIER

10k

5V

ENAB

LESD

A

INTE

RRUP

TSC

LIN

SHUT

DOW

N

2892

F22

10k

RESE

TSD

AIN

SCL

SDAO

UTAU

TOIN

TAD

0AD

1AD

2AD

3

BYP

DETE

CT1

SHDN

VDO

AGND

SENS

E

¼ L

TC42

66

V EE

DGND

OUT

GATE

1µF

–48V

SMAJ

58A

Q1S1

B

0.25

Ω

100k

S1B

0.22

µF

3.3V

0.1µ

F

0.1µ

F

CMPD

3003

••

• •

• •

FB1

FB2

10nF

75Ω

10nF

RJ45

CONN

ECTO

R

75Ω

••

• •

• •

10nF

T1

PHY

(NET

WOR

KPH

YSIC

ALLA

YER

CHIP

)

75Ω

10nF

75Ω

1 2 3 4 5 6 7 8

1nF

Q1: F

AIRC

HILD

IRFM

120A

OR

PHIL

IPS

PHT6

NQ10

TFB

1, F

B2: T

DK M

PZ20

12S6

01A

T1: P

ULSE

H60

96NL

OR

COIL

CRAF

T ET

H1-2

30LD

Figu

re 3

0. O

ne C

ompl

ete

Isol

ated

Pow

er O

ver E

ther

net (

PoE)

Por

t


LTM2892

362892fa


BGA

Pack

age

24-L

ead

(9m

m ×

6.2

5mm

× 2

.91m

m)

(Ref

eren

ce LT

C DW

G #

05-0

8-18

98 R

ev A

)

package DescripTion

NOTE

S:1.

DIM

ENSI

ONIN

G AN

D TO

LERA

NCIN

G PE

R AS

ME

Y14.

5M-1

994

2. A

LL D

IMEN

SION

S AR

E IN

MIL

LIM

ETER

S

BAL

L DE

SIGN

ATIO

N PE

R JE

SD M

S-02

8 AN

D JE

P95

5. P

RIM

ARY

DATU

M -Z

- IS

SEAT

ING

PLAN

E

6. S

OLDE

R BA

LL C

OMPO

SITI

ON IS

96.

5% S

n/3.

0% A

g/0.

5% C

u

43

DETA

ILS

OF P

IN #

1 ID

ENTI

FIER

ARE

OPT

IONA

L,BU

T M

UST

BE L

OCAT

ED W

ITHI

N TH

E ZO

NE IN

DICA

TED.

THE

PIN

#1 ID

ENTI

FIER

MAY

BE

EITH

ER A

MOL

D OR

M

ARKE

D FE

ATUR

E

PACK

AGE

TOP

VIEW

4

PIN

“A1”

CORN

ER

X

Y

aaa

Z

aaa Z

PACK

AGE

BOTT

OM V

IEW

3

SEE

NOTE

S

SUGG

ESTE

D PC

B LA

YOUT

TOP

VIEW

BGA

24 0

911

REV

A

LTM

XXXX

XXµM

odul

e

TRAY

PIN

1BE

VEL

PACK

AGE

IN T

RAY

LOAD

ING

ORIE

NTAT

ION

COM

PONE

NTPI

N “A

1”

DETA

IL A

PIN

1

0.0000.5

0.5

1.5

1.5

2.5

2.5

3.87

5

3.87

5

2.87

5

2.87

5

0.00

0

DETA

IL A

Øb (2

4 PL

ACES

)

F G H JEA B C D

21

43

56

DETA

IL B

SUBS

TRAT

E

// bbb Z

D

AA1

b1

ccc

Z

DETA

IL B

PACK

AGE

SIDE

VIE

W

MOL

DCA

P

Z

MX

YZ

ddd

MZ

eee

0.5

±0.0

25 Ø

24x

SYM

BOL

A A1 A2 b b1 D E e F G H1 H2 aaa

bbb

ccc

ddd

eee

MIN

2.71

0.40

2.31

0.50

0.45

0.36

1.95

NOM

2.91

0.50

2.41

0.60

0.50

9.00

6.25

1.00

7.75

5.00

0.41

2.00

MAX

3.11

0.60

2.51

0.70

0.55

0.46

2.05

0.15

0.10

0.20

0.15

0.08

NOTE

S

DIM

ENSI

ONS

TOTA

L NU

MBE

R OF

BAL

LS: 2

4

E

b

e

e

b

A2

F

G

BGA

Pack

age

24-L

ead

(9m

m ×

6.2

5mm

× 2

.91m

m)

(Ref

eren

ce L

TC D

WG

# 05

-08-

1898

Rev

A)

H1H2

Please refer to http://www.linear.com/product/LTM2892#packaging for the most recent package drawings.


http://www.linear.com/product/LTM2892#packaging

LTM2892

372892fa


Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisToryREV DATE DESCRIPTION PAGE NUMBER

A 08/16 Addd UL-CSA File #Revised propagation delay when SDA2 → SDA1, and I2C Data Hold Time

15, 21


LTM2892

382892fa

For more information www.linear.com/LTM2892 LINEAR TECHNOLOGY CORPORATION 2013

LT 0816 REV A • PRINTED IN USALinear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTM2892

relaTeD parTs

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

LTM2881 Isolated RS485/RS422 µModule Transceiver with Integrated DC/DC Converter 20Mbps 2500VRMS Isolation and Integrated Termination with Power in LGA/BGA Package

LTM2882 Dual Isolated RS232 µModule Transceiver with Integrated DC/DC Converter 2500VRMS Isolation with Power in LGA/BGA Package

LTM2883 SPI/Digital or I2C Isolated µModule with Adjustable 5V, and ±12.5V Nominal Voltage Rails

2500VRMS Isolation with Power in BGA Package

LTC1535 Isolated RS485 Transceiver 2500VRMS Isolation with External Transformer Drive

LTC4310 Hot-Swappable I2C Isolators Isolation with External Transformer or Capacitors

LTC6803 Multistack Battery Monitor Individual Battery Cell Monitoring of High Voltage Battery Stacks, Multiple Devices Interconnected via SPI

LTC2990 Quad I2C Temperature, Voltage and Current Monitor Remote and Internal Temperatures, 14-Bit Voltages and Current, Internal 10ppm/°C Reference

••


VCC2VL2

ON2INC

OUTASDA2SDA2

INBSCLOUT

GND2GND2GND2



LTM2892-I

ISOL

ATIO

N BA

RRIE

RSHDN

SYNCCTRT

14

4

11

567

COL B

RSL

GND

GND

PGND

PGND

13

10 17 1 16

10µF

150pF

D1-D6: MBR0520T1: MURATA 782485/55CT2-3: MURATA 78615/9C

16.9k 3.4k

LT3439

VIN

5V

T11:1.5

1µF

5V

SDA

SCL

2892 F23

3COL A

5k 5k

OUT

BYP

INSH

DN

GND

LT1761-5

D2D1


VCC2VL2

ON2INC

OUTASDA2SDA2

INBSCLOUT

GND2GND2GND2



LTM2892-I

ISOL

ATIO

N BA

RRIE

R

1µF

OUT

BYP

INSH

DN

GND

LT1761-5

D4D3

••

•• •

•

T21:1

••

T31:1

••


VCC2VL2

ON2INC

OUTASDA2SDA2

INBSCLOUT

GND2GND2GND2



LTM2892-I

ISOL

ATIO

N BA

RRIE

R

1µF

OUT

BYP

INSH

DN

GND

LT1761-5

D6D5

5M

1nF

5M

1nF

5M

1nF

5M

1nF

5M

1nF

5M

1nF

SCL3

SDA3

SCL2

SDA2

SCL1

SDA1

45

3

2 2 2

1

45

31

45

31

Figure 31. Series Multi-Zone Isolated I2C Interface, Working Voltage Multiplier






http://www.linear.com/LTC1535


http://www.linear.com/LTC6803-1


ltm2892 - spi/digital or i2c µmodule isolator

Documents