lvds interface ics system diagram and pcb design guide...

1/12 www.rohm.com 2011.03 - Rev.A

© 2011 ROHM Co., Ltd. All rights reserved.

LVDS Interface ICs

System Diagram and PCB Design Guide Line BU8254KVT, BU90R104

35bit LVDS Transmitter 35:5 Serializer

BU8254KVT

35bit LVDS Receiver 5:35 Deserializer

BU90R104

No.11057EAY01

Application Note



BU8254KVT,BU90R104

●LVDS Data Timing Diagram

Tx6 Tx5 Tx4 Tx3 Tx2 Tx1 Tx0

Current Pixel DataPrevious Pixel Data

Tx+/-x=A,B,C,D,E

TCLK OUT(Differential)

Vdiff=0V Vdiff=0V

BU8254KVT/BU90R104 Pixel Data Assign (6bit, 8bit, 10bit Application) 6bit Color 8bit Color 10bit Color

TA0 R4 R4 R4 TA1 R5 R5 R5 TA2 R6 R6 R6 TA3 R7 R7 R7 TA4 R8 R8 R8 TA5 R9 R9 R9 TA6 G4 G4 G4 TB0 G5 G5 G5 TB1 G6 G6 G6 TB2 G7 G7 G7 TB3 G8 G8 G8 TB4 G9 G9 G9 TB5 B4 B4 B4 TB6 B5 B5 B5 TC0 B6 B6 B6 TC1 B7 B7 B7 TC2 B8 B8 B8 TC3 B9 B9 B9 TC4 Hsync Hsync Hsync TC5 Vsync Vsync Vsync TC6 DE DE DE TD0 - R2 R2 TD1 - R3 R3 TD2 - G2 G2 TD3 - G3 G3 TD4 - B2 B2 TD5 - B3 B3 TD6 - N/A N/A TE0 - - R0 TE1 - - R1 TE2 - - G0 TE3 - - G1 TE4 - - B0 TE5 - - B1 TE6 - - N/A

Note : N/A=Not Assigned Note : For 6bit application, use A _ C channel and open TD+/-,TE+/- pin. : For 8bit application, use A _ D channel and open TE+/- pin.

Application Note



BU8254KVT,BU90R104

●10bit Data 3.3V LVCMOS Level Input Example: BU8254KVT ： 3.3V LVCMOS level input/Falling edge/Normal swing BU90R104 ： Falling edge

VDD

GND

0.1uF

LVDS VDD

0.01uF

0.1uF0.01uF

CLKIN

VDD F.Bead

CLKIN

BU8254KVT

TA0TA1TA2TA3TA4TA5TA6TB0TB1TB2TB3TB4TB5TB6

TC0D0TC1D1TC2D2TC3D3TC4D4TC5D5TC6D6TD0TD1TD2TD3TD4TD5TD6TE0TE1TE2TE3TE4TE5TE6

XRSTXRSTVDD

RS

R/F

*2

LVDS GND

PLL VDD

PLL GND0.1uF

0.01uF

TAN

TAP

TBN

TBP

TCN

TCP

TCLKN

TCLKP

TDN

TDP

TEN

TEP

PCB(Transmitter) PCB(Receiver)

100Ω

100Ω

100Ω

RA-

RA+

RB-

RB+

RC-

RC+

RCLK-

RCLK+

RD-

RD+

RE-

RE+

0.1uF

0.01uF

0.1uF

0.01uF

LVDD

LGND

PVDD

PGND

F.Bead

BU90R104

VDD

GND 0.1uF0.01uF

VDD

CLKOUTCLKOUTRA0RA1RA2RA3RA4RA5RA6RB0RB1RB2RB3RB4RB5RB6RC0RC1RC2RC3RC4RC5RC6RD0RD1RD2RD3RD4RD5RD6RE0RE1RE2RE3RE4RE5RE6

PD

DK

R/F

PDOE OE

0.1uF

*1 *1

OPEN

OPEN

OPEN OPEN

OPEN

D7D8D9

D0D1D2D3D4D5D6D7D8D9

OPEN

OPEN OPEN

*1 : Recommended Parts: F.Bead : BLM18A-Series (Murata Manufacturing) *2 : If RS pin is tied to VDD, LVDS swing is 350m V. If RS pin is tied to GND, LVDS swing is 200m V.

100Ωtwist pair Cable

or PCB trace

Application Note



BU8254KVT,BU90R104

●10bit Data Low Level Swing Input Example: BU8254KVT ： 1.2V/1.5V/1.8V/2.5V LVCMOS level input/Falling edge/Normal swing BU90R104 ： Falling edge

VDD

GND

0.1uF

LVDS VDD

0.01uF

0.1uF0.01uF

CLKIN

VDD F.Bead

CLKIN

BU8254KVT

TA0TA1TA2TA3TA4TA5TA6TB0TB1TB2TB3TB4TB5TB6

TC0D0TC1D1TC2D2TC3D3TC4D4TC5D5TC6D6TD0TD1TD2TD3TD4TD5TD6TE0TE1TE2TE3TE4TE5TE6

XRSTXRSTVDD

RS

R/F

*2

LVDS GND

PLL VDD

PLL GND0.1uF

0.01uF

TAN

TAP

TBN

TBP

TCN

TCP

TCLKN

TCLKP

TDN

TDP

TEN

TEP


100Ω

100Ω

100Ω

RA-

RA+

RB-

RB+

RC-

RC+

RCLK-

RCLK+

RD-

RD+

RE-

RE+

0.1uF

0.01uF

0.1uF

0.01uF

LVDD

LGND

PVDD

PGND

F.Bead

BU90R104

VDD

GND 0.1uF0.01uF

VDD

CLKOUTCLKOUTRA0RA1RA2RA3RA4RA5RA6RB0RB1RB2RB3RB4RB5RB6RC0RC1RC2RC3RC4RC5RC6RD0RD1RD2RD3RD4RD5RD6RE0RE1RE2RE3RE4RE5RE6

PD

DK

R/F

PDOE OE

0.1uF

*1 *1

OPEN

OPEN

OPEN OPEN

OPEN

D7D8D9

D0D1D2D3D4D5D6D7D8D9

OPEN

OPEN OPEN

*3 : Recommended Parts: Bead : BLM18A-Series (Murata Manufacturing) *4 : S pin acts as VREF input pin when input voltage is set to half of high level signal input. We recommend to locate by-pass condenser near the RS pin.


or PCB trace

Example for LVCMOS(1.2V input):(R1,R2)=(22kΩ,5.1kΩ) LVCMOS(1.5V input):(R1,R2)=(18kΩ,5.1kΩ) LVCMOS(1.8V input):(R1,R2)=(15kΩ,5.6kΩ) LVCMOS(2.5V input):(R1,R2)=(10kΩ,6.2kΩ)

RS pin.

VDD

R1

R2 C1=0.1uF

Application Note



BU8254KVT,BU90R104

●10bit Color Depth 3.3V LVCMOS Level Input (QVGA, VGA, SVGA ,XGA, WXGA, SXGA) Example: BU8254KVT ： 3.3V LVCMOS level input/Falling edge/Normal swing BU90R104 ： Falling edge

VDD

GND

0.1uF

LVDS VDD

0.01uF

0.1uF0.01uF

CLKIN

VDD F.Bead

CLKIN

BU8254KVT

TA0R4TA1R5TA2R6TA3R7TA4R8TA5R9TA6G4TB0G5TB1G6TB2G7TB3G8TB4G9TB5B4TB6B5TC0B6TC1B7TC2B8TC3B9TC4HSYNCTC5VSYNCTC6DETD0R2TD1R3TD2G2TD3G3TD4B2TD5B3TD6TE0R0TE1R1TE2G0TE3G1TE4B0TE5B1TE6

XRSTXRSTVDD

RS

R/F

*2

LVDS GND

PLL VDD

PLL GND0.1uF

0.01uF

TAN

TAP

TBN

TBP

TCN

TCP

TCLKN

TCLKP

TDN

TDP

TEN

TEP


100Ω

100Ω

100Ω

100Ω

100Ω

100Ω

RA-

RA+

RB-

RB+

RC-

RC+

RCLK-

RCLK+

RD-

RD+

RE-

RE+

100Ωtwistpair Cable

or PCB trace

0.1uF

0.01uF

0.1uF

0.01uF

LVDD

LGND

PVDD

PGND

F.Bead

BU90R104

VDD

GND 0.1uF0.01uF

VDD

CLKOUTR4R5R6R7R8R9G4G5G6G7G8G9B4B5B6B7B8B9HSYNCVSYNCDER2R3G2G3B2B3

R0R1G0G1B0B1

CLKOUTRA0RA1RA2RA3RA4RA5RA6RB0RB1RB2RB3RB4RB5RB6RC0RC1RC2RC3RC4RC5RC6RD0RD1RD2RD3RD4RD5RD6RE0RE1RE2RE3RE4RE5RE6

PD

DK

R/F

OPEN

OPEN

PDOE OE

0.1uF

*1 *1

*1 : Recommended Parts: F.Bead : BLM18A-Series (Murata Manufacturing) *2 : If RS pin is tied to VDD, LVDS swing is 350m V. If RS pin is tied to GND, LVDS swing is 200m

Application Note



BU8254KVT,BU90R104

●10bit Color Depth Low Level Swing Input (QVGA, VGA, SVGA ,XGA, WXGA, SXGA) Example: BU8254KVT ： 1.2V/1.5V/1.8V/2.5V LVCMOS level input/Falling edge/Normal swing BU90R104 ： Falling edge

VDD

GND

0.1uF

LVDS VDD

0.01uF

0.1uF0.01uF

CLKIN

VDD F.Bead

CLKIN

BU8254KVT

TA0R4TA1R5TA2R6TA3R7TA4R8TA5R9TA6G4TB0G5TB1G6TB2G7TB3G8TB4G9TB5B4TB6B5TC0B6TC1B7TC2B8TC3B9TC4HSYNCTC5VSYNCTC6DETD0R2TD1R3TD2G2TD3G3TD4B2TD5B3TD6TE0R0TE1R1TE2G0TE3G1TE4B0TE5B1TE6

XRSTXRSTVDD

RS

R/F

*2

LVDS GND

PLL VDD

PLL GND0.1uF

0.01uF

TAN

TAP

TBN

TBP

TCN

TCP

TCLKN

TCLKP

TDN

TDP

TEN

TEP


100Ω

100Ω

100Ω

100Ω

100Ω

100Ω

RA-

RA+

RB-

RB+

RC-

RC+

RCLK-

RCLK+

RD-

RD+

RE-

RE+

100Ωtwistpair Cable

or PCB trace

0.1uF

0.01uF

0.1uF

0.01uF

LVDD

LGND

PVDD

PGND

F.Bead

BU90R104

VDD

GND 0.1uF0.01uF

VDD


R0R1G0G1B0B1


PD

DK

R/F

OPEN

OPEN

PDOE OE

0.1uF

*1 *1

*3 : Recommended Parts: F.Bead : BLM18A-Series (Murata Manufacturing) *4: RS pin acts as VREF input pin when input voltage is set to half of high level signal input. We recommend to locate by-pass condenser near the RS pin.

RS pin.

VDD

R1

R2 C1=0.1uF


Application Note



BU8254KVT,BU90R104

●8bit Color Depth 3.3V LVCMOS Level Input (QVGA, VGA, SVGA ,XGA, SXGA, SXGA+) Example: BU8254KVT ： 3.3V LVCMOS level input/Falling edge/Normal swing BU90R104 ： Falling edge

VDD

GND

0.1uF

LVDS VDD

0.01uF

0.1uF0.01uF

CLKIN

VDD F.Bead

CLKIN

BU8254KVT

TA0R4TA1R5TA2R6TA3R7TA4R8TA5R9TA6G4TB0G5TB1G6TB2G7TB3G8TB4G9TB5B4TB6B5TC0B6TC1B7TC2B8TC3B9TC4HSYNCTC5VSYNCTC6DETD0R2TD1R3TD2G2TD3G3TD4B2TD5B3TD6TE0TE1TE2TE3TE4TE5TE6

XRSTXRSTVDD

RS

R/F

*2

LVDS GND

PLL VDD

PLL GND0.1uF

0.01uF

TAN

TAP

TBN

TBP

TCN

TCP

TCLKN

TCLKP

TDN

TDP

TEN

TEP


100Ω

100Ω

100Ω

100Ω

100Ω

RA-

RA+

RB-

RB+

RC-

RC+

RCLK-

RCLK+

RD-

RD+

RE-

RE+

0.1uF

0.01uF

0.1uF

0.01uF

LVDD

LGND

PVDD

PGND

F.Bead

BU90R104

VDD

GND 0.1uF0.01uF

VDD



PD

DK

R/F

PDOE OE

0.1uF

*1 *1

OPEN OPEN OPEN



or PCB trace

Application Note



BU8254KVT,BU90R104

●8bit Color Depth Low Level Swing Input (QVGA, VGA, SVGA ,XGA, SXGA, SXGA+) Example: BU8254KVT ： 1.2V/1.5V/1.8V/2.5V LVCMOS level input/Falling edge/Normal swing BU90R104 ： Falling edge

VDD

GND

0.1uF

LVDS VDD

0.01uF

0.1uF0.01uF

CLKIN

VDD F.Bead

CLKIN

BU8254KVT

TA0R4TA1R5TA2R6TA3R7TA4R8TA5R9TA6G4TB0G5TB1G6TB2G7TB3G8TB4G9TB5B4TB6B5TC0B6TC1B7TC2B8TC3B9TC4HSYNCTC5VSYNCTC6DETD0R2TD1R3TD2G2TD3G3TD4B2TD5B3TD6TE0TE1TE2TE3TE4TE5TE6

XRSTXRSTVDD

RS

R/F

*2

LVDS GND

PLL VDD

PLL GND0.1uF

0.01uF

TAN

TAP

TBN

TBP

TCN

TCP

TCLKN

TCLKP

TDN

TDP

TEN

TEP


100Ω

100Ω

100Ω

100Ω

100Ω

RA-

RA+

RB-

RB+

RC-

RC+

RCLK-

RCLK+

RD-

RD+

RE-

RE+

0.1uF

0.01uF

0.1uF

0.01uF

LVDD

LGND

PVDD

PGND

F.Bead

BU90R104

VDD

GND 0.1uF0.01uF

VDD



PD

DK

R/F

PDOE OE

0.1uF

*1 *1

OPEN OPEN OPEN

*3 : Recommended Parts: F.ead : BLM18A-Series (Murata Manufacturing) *4 : RS pin acts as VREF input pin when input voltage is set to half of high level signal input. We recommend to locate by-pass condenser near the RS pin.

RS pin.

VDD

R1

R2 C1=0.1uF



or PCB trace

Application Note



BU8254KVT,BU90R104

●6bit Color Depth 3.3V LVCMOS Level Input (QVGA, VGA, SVGA ,XGA, SXGA, SXGA+)

Example: BU8254KVT ： 3.3V LVCMOS level input/Falling edge/Normal swing BU90R104 ： Falling edge

VDD

GND

0.1uF

LVDS VDD

0.01uF

0.1uF0.01uF

CLKIN

VDD F.Bead

CLKIN

BU8254KVT

TA0R4TA1R5TA2R6TA3R7TA4R8TA5R9TA6G4TB0G5TB1G6TB2G7TB3G8TB4G9TB5B4TB6B5TC0B6TC1B7TC2B8TC3B9TC4HSYNCTC5VSYNCTC6DETD0TD1TD2TD3TD4TD5TD6TE0TE1TE2TE3TE4TE5TE6

XRSTXRSTVDD

RS

R/F

*2

LVDS GND

PLL VDD

PLL GND0.1uF

0.01uF

TAN

TAP

TBN

TBP

TCN

TCP

TCLKN

TCLKP

TDN

TDP

TEN

TEP


100Ω

100Ω

100Ω

100Ω

RA-

RA+

RB-

RB+

RC-

RC+

RCLK-

RCLK+

RD-

RD+

RE-

RE+

0.1uF

0.01uF

0.1uF

0.01uF

LVDD

LGND

PVDD

PGND

F.Bead

BU90R104

VDD

GND 0.1uF0.01uF

VDD

CLKOUTR4R5R6R7R8R9G4G5G6G7G8G9B4B5B6B7B8B9HSYNCVSYNCDE


PD

DK

R/F

PDOE OE

0.1uF

*1 *1

OPEN

OPEN

OPEN OPEN

OPEN



or PCB trace

Application Note



BU8254KVT,BU90R104

●6bit Color Depth Low Level Swing Input (QVGA, VGA, SVGA ,XGA, SXGA, SXGA+)

Example: BU8254KVT ： 1.2V/1.5V/1.8V/2.5V LVCMOS level input/Falling edge/Normal swing BU90R104 ： Falling edge

VDD

GND

0.1uF

LVDS VDD

0.01uF

0.1uF0.01uF

CLKIN

VDD F.Bead

CLKIN

BU8254KVT

TA0R4TA1R5TA2R6TA3R7TA4R8TA5R9TA6G4TB0G5TB1G6TB2G7TB3G8TB4G9TB5B4TB6B5TC0B6TC1B7TC2B8TC3B9TC4HSYNCTC5VSYNCTC6DETD0TD1TD2TD3TD4TD5TD6TE0TE1TE2TE3TE4TE5TE6

XRSTXRSTVDD

RS

R/F

*2

LVDS GND

PLL VDD

PLL GND0.1uF

0.01uF

TAN

TAP

TBN

TBP

TCN

TCP

TCLKN

TCLKP

TDN

TDP

TEN

TEP


100Ω

100Ω

100Ω

100Ω

RA-

RA+

RB-

RB+

RC-

RC+

RCLK-

RCLK+

RD-

RD+

RE-

RE+

0.1uF

0.01uF

0.1uF

0.01uF

LVDD

LGND

PVDD

PGND

F.Bead

BU90R104

VDD

GND 0.1uF0.01uF

VDD

CLKOUTR4R5R6R7R8R9G4G5G6G7G8G9B4B5B6B7B8B9HSYNCVSYNCDE


PD

DK

R/F

PDOE OE

0.1uF

*1 *1

OPEN

OPEN

OPEN OPEN

OPEN

*3 : Recommended Parts: F.Bead : BLM18A-Series (Murata Manufacturing) *4 : RS pin acts as VREF input pin when input voltage is set to half of high level signal input. We recommend to locate by-pass condenser near the RS pin.

RS pin.

VDD

R1

R2 C1=0.1uF



or PCB trace

Application Note



BU8254KVT,BU90R104

●PCB Design Guide Line for LVDS • Interconnecting media between Transmitter and Receiver (i.e. PCB trace, connector, and cable) should be well

balanced.(Keep all these differential impedance and the length of media as same as possible.). • Locate by-pass capacitors adjacent to the device pins as close as possible. • Minimize the distance between traces of a pair (S1) to maximize common mode rejection.

See following figure. • Place adjacent LVDS trace pair at least twice (>2 x S1) as far away. • Avoid 90 degree bends. • Minimize the number of VIA on LVDS traces. • Match impedance of PCB trace, connector, media (cable) and termination to minimize reflections (emissions) for cabled

applications (typically 100. differential mode characteristic impedance). • Use 4 layer PCB (minimum).

Recommend the CITS series or Si series of Polar Instruments company to the calculation of impedance

Monitor Pad

Stub

Layer1 Layer2

Signal Via

GND Via

GND

GND

Good No Good

Application Note



BU8254KVT,BU90R104

●Ordering part number

B U 8 2 5 4 K V T - E 2

Part No. Part No. 8254

Package KVT: TQFP64V

Packaging and forming specification E2: Embossed tape and reel

B U 9 0 R 1 0 4 - E 2

Part No. Part No. 90R104 Package TQFP64V

Packaging and forming specification E2: Embossed tape and reel

Direction of feed

Reel ∗ Order quantity needs to be multiple of the minimum quantity.

Embossed carrier tape (with dry pack)Tape

Quantity

Direction of feed The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

1000pcs

E2

( )

1pin

(Unit : mm)

TQFP64V

0.1

3348

161

12.0±0.3

10.0±0.2

0.125±0.1

0.5 0.2 ± 0.10.1±

0.1

1.0±

0.1

0.5

49

64

32

17

10.0

±0.2

12.0

±0.3

R1120Awww.rohm.com© 2011 ROHM Co., Ltd. All rights reserved.

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lvds interface ics system diagram and pcb design guide...

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