m. tech core ve - i year

8/3/2019 m. Tech Core Ve - i Year

1/17

GYAN VIHAR SCHOOL OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

TEACHING AND EXAMINATION SCHEMEAND

DETAILED SYLLABUS FOR

M. Tech Full-Time (Core) (VLSI and Embedded Systems) (2 Year Course)

2009-10(New Batch)

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Teaching and Examination Scheme for M. Tech. FULL-TIME (Core) (VLSI and Embedded Systems)

2009-10

Year I Semester I

S.

No

Code Subject Hrs./week Exa

m

Hrs.

Maximum Marks

A. Theory Papers L T P Internal

Assessment/

Sessionals

Semester

End

Exams

Total

1 1 MT VE 1 MOS VLSI 3 - - 3 30 70 100

2 1 MT VE 2 VLSI Technology 3 - - 3 30 70 100

3 1 MT VE 3 System Level Design andModeling of Digital System

3 - - 3 30 70 100

4 1 MT VE 4 Elective I (any one of the

following)

3 - - 3 30 70 100

1 MT VE 4.1 Advanced Computer

Communication

1 MT VE 4.2 Testing and Fault Tolerance

1 MT VE 4.3 Memory design and testing

B. Practical & Sessional:

5 1 MT VE 5 Digital System Design Lab - - 2 3 30 20 50

6 1 MT VE 6 M Tech Seminar I - - 1 3 30 20 50

TOTAL 1

2

0 3 - - - 500

TOTAL TEACHING

LOAD

1

5

Year I Semester II

S.

No.

Code Subject Hrs./week Exam

Hrs.

Maximum Marks

A. Theory Papers L T P Internal

Assessment/

Sessionals

Semester

End

Exams

Total

1 2 MT VE 1 E Commerce 3 - - 3 30 70 100

2 2 MT VE 2 Analog ICs 3 - - 3 30 70 100

3 2 MT VE 3 Advanced Digital Signal Processing 3 - - 3 30 70 1004 2 MT VE 4 Elective II (any one of the following) 3 - - 3 30 70 100

2 MT VE

4.1

Synthesis of Digital System

2 MT VE

4.2

Issues in Deep Sub-micron CMOS IC

Design

2 MT VE

4.3

Computer-Aided VLSI Design

B. Practical & Sessional:

5 2 MT VE 5 VLSI Design Lab - - 2 3 30 20 50

6 2 MT VE 6 M Tech Seminar II - - 1 3 30 20 50

TOTAL 1

2

0 3 - - - 500

TOTAL TEACHING LOAD 15

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DETAILED SYLLABUS

2009-10

MOS VLSI [1 MT VE 1]

CLASS 1st Sem M. Tech (Core) VLSI & ES EVALUATION

SCHEDULE PER WEEK

LECTURES:3

EXAMINATION TIME = THREE (3) HOURS

MAX. MARKS =100

[ INTERNAL ASSESMENT (30) & SEMESTER

END EXAM (70)]

Two questions will be set from each unit and students will be required to answer one question from each unit

UNIT CONTENTS OF THE SUBJECT No. of Hours

Required

1 PROCESS FLOW AND MASKING STEPS FOR MOS AND CMOS

TECHNOLOGIES, Lambda based design rules. (1) Electrical behavior

of MOS transistors, (2) Latch up in CMOS technology

7

II Layer properties of various conducting layers in MOS technology

(diffusion, poly-silicon and metal): Sheet resistance, relative capacitance.

7

III Fundamental time constant ( ) for a technology. Design and analysis of

NMOS (enhancement and depletion) and CMOS inverters; rationing of

transistor size, logic threshold, logic low voltage level, rise and fall of

delays.

7

IV DESIGN OF BASIC GATES IN NMOS TECHNOLOGY. CMOS

logic design styles: static CMOS logic(AND, NOR gates), complex gates,

domino logic, pseudo NMOS logic ,clocked CMOS(C2 MOS) logic.

7

V STRUCTURED LOGIC DESIGN: Programmable arrays. Design of

latches and flip-flops, static memory cell and dynamic memory cell. MOS

scaling theory and scaling of interconnection.

7

Recommended Books:

1. Sung-Mo Kang & Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis and Design, McGraw-Hill,

1998.

2. Neil H.E.Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Addison Wesley, 1998.3. Rabaey et al., Digital Integrated Circuits, Pearson India, 2002.

4. K. Martin, Digital Integrated circuit design, Oxford University press, 2001.

5. A.Mukherji, Introduction to nMOS and CMOS VLSI system design, Prentice Hall Inc.,

6. C.Mead and L.Conway, Introduction to VLSI systems, Addison Wesley, 1986.

7. Glasser and Dobberpuhl, Design and analysis of VLSI circuits, Addison Wesley, 1985.

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GYAN VIHAR SCHOOL OF ENGINEERING AND TECHNOLOGYDEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

DETAILED SYLLABUS

2009-10

VLSI TECHNOLOGY [1 MT VE 2]


SCHEDULE PER WEEK

LECTURES:3


MAX. MARKS =100


END EXAM (70)]



Required

1 Basic IC processing steps. Crystal growth and wafer preparation.

Epitaxy-basics of vacuum deposition, MBE. CVD- low and high

temp/pressure depositions.

7

II Diffusion kinetics, Ficks law, sheet resistivity methods of diffusion.

Oxidation properties of oxides, theory of oxidation, oxidation under

different ambients.

7

III Ion implantation.

Etching techniques.

7

IV CVD of polysilicon, oxides and nitrides.

Integrated circuit structures in bipolar and MOS.

7

V Introduction to process simulation, SUPREM. 7

Recommended Books:

1. S. M. Sze, VLSI Technology, McGRAW-HILL, 1988.

2. D. Nagchoudhuri, Principles Of Microelectronic Technology, Wheeler Publishing, 1998.

3. Stephen A. Campbell, The Science and Engineering of Microelectronic Fabrication, Oxford University Press,

1996.

4. Hong Xiao, Introduction to Semiconductor Manufacturing, Prentice Hall, 2001.

5. SK Gandhi, VLSI fabrication principles, John Wiley 1983.

6. AB Glaser, GE Subak-Sharpe, Integrated circuit engineering, Reading MA, Addison Wesley 1977

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DETAILED SYLLABUS

2009-10

SYSTEM LEVEL DESIGN AND MODELING OF DIGITAL SYSTEM [1 MT VE 3]


SCHEDULE PER WEEK

LECTURES:3


MAX. MARKS =100


END EXAM (70)]


UNIT CONTENTS OF THE SUBJECT No. of

Hours

Required

1 Sequential Logic Design- Introduction, Basic Bistable Memory Devices,additional

bistable devices, reduced characteristics and excitation table for bistable devices.

7

II Synchronous Sequential Logic Circuit Design: Introduction, Moore, Mealy and

Mixed type Synchronous State Machines. Synchronous sequential design of

Moore, Melay Machines, Synchronous Counter Design.

7

III Data path and Control design. Algorithmic State Machine: An Algorithm with

inputs, digital solution, Implementation of traffic light controller, ASM charts,

Design Procedure for ASMs.

7

IV Introduction to programmable logic devices: PALs, PLDs, CPLDs and FPGAs. 7

V Introduction to VHDL: Data types, Concurrent statements, sequential statements,

behavioral modeling.

7

Recommended Books:

1. Digital System Design, Ercegovic, Wiley.

2. Richard S. Sandige, Modern Digital Design, McGraw-Hill, 1990.

3. Zvi Kohavi, Switching and Finite Automata Theory, Tata McGraw-Hill.

4. Navabi. Analysis and modeling of digital systems. McGraw Hill, 1998.

5. Perry. Modeling with VHDL. McGraw Hill, 1994.

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DETAILED SYLLABUS

2009-10

ADVANCED COMPUTER COMMUNICATION [1 MT VE 4.1]


SCHEDULE PER WEEK

LECTURES:3


MAX. MARKS =100


END EXAM (70)]


Units Contents of the Subject Hours

1 Introduction to Reference Models: Introduction to data communication. Concept of

analog and digital signals. Bandwidth. Network architecture. Basics of OSI and

TCP/IP reference models. Example architecture of other reference models.

6

2

Transmission media: Wired and wireless connectivity. FDM, TDM and CDMA.

Circuit and packet switching. Frame relay and ATM switching. ISDN.

Local area network protocols. IEEE standards for LAN. Fibre optic networks. Satellite

networks. Data link layer design issues: its functions and protocols.

8

3

Protocol and Packet format:

Internet protocol. Routing algorithms. Congestion control algorithms. IP addressing

schemes. Internetworking and sub-netting. Transport and application layer designissues. Connection management. Transport protocol on top of X.25. File transfer and

access management.

7

4

Quality of Services:

In ATM, IETF integrated services model, Differentiated services Model. Flow

identification, Packet Classifiers and Filters, Scheduling. Factors affecting QOS

parameters and service categories. QOS classes.

8

5

Network Management:

Network Management protocol; SNMP, CMIP, Issues in the management of large

networks. Multicast: IGMP, PIM, DVMRP.Concept of Traffic and service. Traffic

and service characteristics of voice and video data. ATM Traffic descriptors and QOS

parameters. Elements of ATM Traffic management-Traffic contracting, policing and

shaping.

6

Text & Reference Book:

1. Charle Kaufman, Radia Perlman, Mike Specines, Uyless Black "Computer Networks: Protocols Standards

and Interfaces " PHI.

2. K.C. Mansfield,J.L. Antonakos " An introduction to computer networking" PHI.

3. Network Systems Design using Network Processor, Douglas Comer, Pearson Education, ISBN 81-7808-

994-7

4 IXP 1200 programming, Erik J. Johnson and Aaron Kunze, Intel Press.

5. Stallings: Data communication & Networking

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DETAILED SYLLABUS

2009-10

TESTING AND FAULT TOLERANCE [1 MT VE 4.2]


SCHEDULE PER WEEK

LECTURES:3


MAX. MARKS =100


END EXAM (70)]



Hours

Required

1 PHYSICAL FAULTS AND THEIR MODELING; Stuck at Faults, Bridging

Faults; Fault collapsing; Fault Simulation: Deductive, Parallel, and Concurrent

Fault Simulation. Critical Path Tracing;

7

II ATPG FOR COMBINATIONAL CIRCUITS: D-Algorithm, Boolean

Differences, PODEM Random, Deterministic and Weighted Random Test Pattern

Generation; Aliasing and its effect on Fault Coverage. PLA Testing, Cross Point

Fault Model and Test Generation.

7

III MEMORY TESTING Permanent Intermittent and Pattern Sensitive Faults,

Marching Tests; Delay Faults. ATPG for Sequential Circuits: Time FrameExpansion ; Controllability and Observability Scan Design, BILBO , Boundary

Scan for Board Level Testing ;

7

IV BIST AND TOTALLY SELF CHECKING CIRCUITS. System Level

Diagnosis: Introduction; Concept of Redundancy, Spatial Redundancy, Time

Redundancy, Error Correction Codes.

7

V RECONFIGURATION TECHNIQUES; Yield Modeling, Reliability and

effective area utilization.

7

Recommended Books:

1. Abramovici, M., Breuer, M. A. and Friedman, A. D. Digital systems testing and testable design. IEEE press

(Indian edition available through Jayco Publishing house), 2001.2. Bushnell and Agarwal, V. D. VLSI Testing. Kluwer.

3. Agarwal, V. D. and Seth, S. C. Test generation for VLSI chips. IEEE computer society press.

4. Hurst, S. L. VLSi testing: Digital and mixed analog/digital techniques. INSPEC/IEE, 1999.

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DETAILED SYLLABUS

2009-10

MEMORY DESIGN AND TESTING [1 MT VE 4.3]


SCHEDULE PER WEEK

LECTURES:3


MAX. MARKS =100

[ INTERNAL ASSESMENT (30) &

SEMESTER END EXAM (70)]



Hours

Required

1 Review of MOS Structure, Scaled Down MOSFET and CMOS Processing. 7

II Processing for Memories: Multipoly Floating Gate and Control Gate, Trench

Capacitors and thin Oxide. Inverter Design: Choice of W/L and Noise Margin

Calculation, Cascode and Differential Inverters.

7

III SRAM and DRAM Cell Design: Basic Cell Structures, modeling and design

Equations.

7

IV Sense Amplifiers: Necessity for Sense Amplifiers, Voltage and Current Sense

Amplifiers, Reference Voltage Generation, Influence of Sense Amplifier on cellArchitecture.

7

V Peripheral Circuits. Memory Testing: Modeling, Introduction to Functional

Testing and Built in Self-Test.

7

Recommended Books:

1.Sung-Mo Kang & Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis and Design, McGraw-Hill,

1998.

2. A.Mukherji, Introduction to nMOS and CMOS VLSI system design, Prentice Hall Inc

3. Glasser and Dobberpuhl, Design and analysis of VLSI circuits, Addison Wesley, 1985.

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DETAILED SYLLABUS

2009-10

DIGITAL SYSTEM DESIGN LAB [1 MT VE 5]


SCHEDULE PER WEEK

PRACTICALS :2


MAX. MARKS = 50

[SESSIONALS (30) & SEMESTER END EXAM

(20)]

S. No. List of Experiments

PART-I:

1-6

Design, implement and experiment with digital system, this will include ASIC design, FPGA based

design. design of relevant hardware and software for microcontroller ,processor and DSP based

embedded system.

PART-II:

7-12.Custom design and simulation of different higher level analog and digital circuits using advance

EDA tools like Tanner Spice S-edit and L- edit

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DETAILED SYLLABUS

2009-10

E-COMMERCE [2 MT VE 1]


SCHEDULE PER WEEK

LECTURES:3


MAX. MARKS =100





Hours

Required

1 INTRODUCTION AND BUSINESS STRATEGY IN AN ELECTRONIC

AGE: Scope of electronic commerce, trade cycle, electronic markets, electronic

data interchange, Internet commerce and e-commerce in perspective. Value chain -

supply chains, Porter's value chain model and inter - organizational value chains.

Competitive Advantage - Competitive strategy, Porter's Model, First Mover

advantage and competitive advantage using e-commerce Business strategy-

Introduction to Business Strategy, Strategic Implications of it of IT Technology, e-

commerce Implementation and evaluation.

7

II BUSINESS TO BUSINESS ELECTRONIC COMMERCE:Inter organizationalTransactions, The credit Transaction Trade cycle. A variety of transactions,

Electronic markets - markets and electronic markets,usage of electronic markets,

Advantages and disadvantages of electronic markets.

7

III ELECTRONIC DATA INTERCHANGE (EDI) : Definition and benefits of

EDI. EDI technology, standards, communications, implementation, agreements

and securities. EDI trading patterns and transactions.

7

IV BUILDING AN E-COMMERCE SITE :Introduction to object

behaviour,components, active scripting. Object models, Infrastructure

objects,service objects and data objects,choosing the objects. Building a scalable

application,Adding the configure method,connecting to the database.Accessing

and versioning the database. Building the catalog object with example. Creating

shopping basket-Holding state,creating the tables for a shopping basket,modifying

the object model and making the basket accessible.

7

V J2EE ARCHITECTURE OVERVIEW :Enterprise components. Information

technology in the enterprises. Introduction to enterprise objects and enterprise

component model. The J2EE model features J2EE components - container

architecture. Enterprises Java and J2EE architecture.

7

Recommended Books :

1. David Whiteley - E-Commerce Strategy,Technology and Application, Tata McGraw Hill.

2. Mathew Reynolds - Beginning E-commerce with Visual Basic ASP, SQL Server 7.0 and MTS, Shroff

Publishers & Distributors Pvt. Ltd.3. Perrone & Chaganti - Building Java Enterprises System with J2EE, Techmedia.

4. Kalakota - Frontiers of Electronic Commerce, Pearson Education.

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DETAILED SYLLABUS

2009-10

ANALOG ICS [2 MT VE 2]

CLASS 2ND Sem M. Tech (Core) VLSI & ES EVALUATION

SCHEDULE PER WEEK

LECTURES:3


MAX. MARKS =100





Hours

Required

1 REVIEW OF MOS TRANSISTOR operation models and equivalent circuits.

Single-Stage Amplifiers, Differential Amplifiers. Passive and Active Current

Mirrors: Cascode Current mirror, Wilson Current mirror.

7

II THEORY AND DESIGN OF MOS OPERATIONAL AMPLIFIER, Complete

CMOS operational amplifier including frequency compensation. Comparators and

Voltage Reference Sources.

7

III SWITCHED CAPACITOR CIRCUITS: Principles of operation of Switched

Capacitor Circuits, Switched Capacitor Filters.

7

IV D/A AND A/D CONVERTERS. 7V NONLINEAR ANALOG CIRCUITS: Timers, Function generators, Multipliers

and PLL

7

Recommended Books:

1. P. R. Gray and R. G. Meyer. Analysis and Design of Analog Integrated Circuits. McGraw Hill, NY, 1994.

2. A. B. Grebene, Bipolar and MOS analog integrated circuits design. John Wiley, 1984.

3. S. Soclof. Analog Integrated Circuits. Prentice Hall Inc. , 1985.

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DETAILED SYLLABUS

2009-10

ADVANCEDDIGITAL SIGNAL PROCESSING [2 MT VE 3]


SCHEDULE PER WEEK

LECTURES:3

TUTORIAL:0


MAX. MARKS =100


END EXAM (70)]



Hours

Required

1 DFT & ITS PROPERTIES. Decimation in time and decimation in frequency

FFT algorithms, discrete cosine transform.

7

II IIR FILTER DESIGN: Butterworth design, bilinear transformation. Low Pass,

High Pass, Band Pass and Band, Stop digital filters. Spectral transformation of IIR

filters.

7

III FIR FILTERS DESIGN: Symmetric and antisymmetric linear phase. FIR filter

by rectangular, triangular and Blackman window functions.

7

IV FINITE WORD LENGTH EFFECTS IN FIR AND IIR DIGITAL FILTERS:

Quantization, round off errors and overflow errors.

7

V MULTI RATE DIGITAL SIGNAL PROCESSING: Concepts, design of

practical sampling rate converters, Decimators, interpolators. Polyphase

decompositions.

7

Recommended Books:

1. Schafer, Buck-Discrete Time signal Processing, Pearson Education Asia.

2. Prokis & Monolakis-Digital Signal Processing: Principles, Algorithms & Application, Prentice hall of India.

3. S.K. Mitra-Digital Signal Processing. Tata Mc-Graw Hill.

4. Rabiner & Gold-Theory & Applications of Digital Signal Processing, Prentice Hall of India.

5. Lathi-Signal Processing & Linear System, Oxford Univ Pren

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DETAILED SYLLABUS

2009-10

SYNTHESIS OF DIGITAL SYSTEM [2 MT VE 4.1]


SCHEDULE PER WEEK

LECTURES:3


MAX. MARKS =100





Hours

Required

1 ROLE OF CAD IN DIGITAL SYSTEM DESIGN, levels of design and

description such as behavioral, structural and physical;

7

II TECHNOLOGICAL ALTERNATIVES; languages for design description and

modeling at various levels;

7

III SRAM AND DRAM CELL DESIGN: Basic Cell Structures, modeling and

design Equations.

7

IV CAD TOOLS FOR SYNTHESIS,OPTIMIZATION, simulation and

verification of design at various levels as well as for PLAs, gate arrays etc.

7

V SPECIAL REALIZATIONS AND STRUCTURES such as microprogrammes 7

Recommended Books:

1. G. D. Micheli. Synthesis and optimization of digital systems.

2. Dutt, N. D. and Gajski, D. D. High level synthesis, Kluwer, 2000.

3. T. H. Cormen, C. E. Leiserson and R. L. Rivest, Introduction to Algorithms, McGraw-Hill, 1990.

4. N. Deo, Graph Theory, PH India.

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DETAILED SYLLABUS

2009-10

ISSUES IN DEEP SUB-MICRON CMOS IC DESIGN [2 MT VE 4.2]


SCHEDULE PER WEEK

LECTURES:3


MAX. MARKS =100


END EXAM (70)]



Hours

Required

1 Introduction to concept of design,

design methodologies,

semi-custom and custom design approaches.

7

II Data path & control design. 7

III Elements of device and circuit simulation,

logic simulation.

Stick diagram and representation

7

IV layout of ICs,

lambda based design rules.Deep submicron interconnects modeling and synthesis.

7

V Topics in design-yield and redundancy,

low power design techniques.

7

Recommended Books:

1. Raguram, R. Modeling and Simulation of Electronic circuits. PHIndia, 1996.

2. Weste and Eshraghian. Principles of CMOS VLSI design. Addison Wesley, 1998.

3. Kang, S. M. and Leblebici, Y. CMOS Digital Integrated Circuits: Analysis and Design. Mc Graw Hill,

2000.

4. Chandrakasan, A. P. Low-power design methodologies. IEEE Press, 1998.

5. A.Mukherji. Introduction to NMOS and CMOS VLSI system design. Prentice Hall Inc., 1986

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DETAILED SYLLABUS

2009-10

COMPUTER-AIDED VLSI DESIGN [2 MT VE 4.3]

CLASS 2ND Sem M. Tech (Core) VLSI

& ES

EVALUATION

SCHEDULE PER WEEK

LECTURES:3


MAX. MARKS =100

[ INTERNAL ASSESMENT (30) & SEMESTER END

EXAM (70)]



Required

1 INTRODUCTION :Why design ICs? Technology and economics for

IC manufacturing. COMOS technology-circuit techniques,Power

consumption,Design and testability. IC Design Techniques-Hierarchical

design,Data abstraction and computer aided design

7

II TRANSISTORS AND LAYOUT : Design Rules-Fabrication

Errors,Scalable design rules, SCMOS design rules and typical process

parameters. Layout Design and Tools-Layout for Circuits,Stick

Diagrams,Hierarchical Stick Diagrams,Layout Design and Analysis

Tools and Automated Layout.

7

III SEQUENTIAL MACHINES: Latches and FlipFlops-Categories of

memory elements,Latches and Flip-Flops. Sequential Systems and

clocking disciplines-One phase systems for Flip-Flops, Two-phase

systems for Latches,Advanced clocking analysis and clock

generation.Sequential system Design-structural specification,State

Transition Graph,Tables and State assignment.Power optimization.

Design validation and sequential testing.

7

IV SUBSYSTEM DESIGN :Subsystem Design Principles-Pipelining and

Data paths. Combinational shifter,Adders ALUs and Multipliers.High

Density Memory-ROM,Static RAM, Three-Transistor DRAM and one

transistor DRAM.

7

V CHIP DESIGN :Design Methodologies.Kitchen Timer chip-Timer

specification and Architecture,Architecture Design.Logic design,layout

design and Design Validation.

7

Recommended Books:

1. Wayne Wolf: CMOS VLSI Design, PHI, 2008

2. J Bhaskar: VHDL Design,

3. Nawabi: VHDL Design,

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DETAILED SYLLABUS

2009-10

VLSI DESIGN LAB [2 MT VE 5]


SCHEDULE PER WEEK

PRACTICALS :2


MAX. MARKS = 50

[SESSIONALS (30) & SEMESTER END EXAM

(20)]

S. No. List of Experiments

PART-I:

1-6

Draw the Layout; do circuit partitioning, placement and routing, circuit compaction, check DRC,

Circuit extraction and finally post layout simulation for different combinational and sequential

circuits.

PART-II:

7-12.

Use the feature of automation test program generation, multilevel logic synthesis for design smaller

application chips like multi bit parallel adder priority encoder, general purpose register, ALU,

microcontroller/ dsp processor/ traffic light controller /sequential adder etc.

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m. tech core ve - i year

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