making asynchronous signals acceptable in a synchronous ...shams/elec3500/asynchronous.pdf ·...

Making Asynchronous Signals Acceptable In A

9/19/02

eptable In A

able from magic.” Clarke

© John Knight Electronics Department, Carleton University

p.1

Making Asynchronous Signals AccSynchronous Society

“Any sufficiently advanced technology is indistinguish

Aa+


9/19/02

Normal D flip-flop operation.

ip-flop. edge.edge.

edge:

around the clock edge.

edge to output

ample to clock edge

ere data must hold still


p.2

Timing Properties of Flip-Flops


FIG. 2-1 The normal operation of the rising-edge edge-triggered D flThe input is sampled just before and during the active clockThe stored data output appears a short time after the clock

FIG. 2-2 If the D input changes just before or during the rising clockthe flip-flop may store the old input,the new input,or even half-way in between.

To avoid ambiguity disallow input changes in a time region

1D

C1

QCLOCKINPUT INPUT

Q

CLOCK

Time from clock

Time from input s

Rising edgeis active

1DC1

QCLOCKINPUT INPUT

Q

CLOCK

Region wh


9/19/02


e clock edge in D flip-flops:

held stable.

held stable.

ime. before the clock edge.

be negative.

st hold still

Hold timeSetup time

negative


p.3

Setup, Propagation and Hold Times

There are three time intervals associated with the activ• The setup time,

the interval before the clock where the data must be

• The hold time,the interval after the clock where the data must be

Most modern flip-flops have a zero or a negative hold tA negative hold time allows the data to change slightly

• the clock to output propagation delay. tCHQV (time from Clock High to Q Valid).

FIG. 2-3 The setup and hold times for a flip-flop. The hold time may

1DC1

QCLOCKINPUT INPUT

Q

CLOCKHold time

Setup time

Region where data mu

tCHQV

Clock High to Q Valid


9/19/02


s one uses in most designs.

old time

etup time

where data should not change

tCHQV, Prop Delay


p.4

Example: Setup, Hold and tCHQV

FIG. 2-4 Setup time, hold time, and propagation delay.For a 74AC74 CMOS flip-flop.The D INPUT signal shows several possible legal transitions.

In the table, the minimum/maximum delays are the oneThe manufacturer will guarantee those.The typical delay is not very rigorously defined.

D INPUT

Q

CLOCK

0 ns H

3 ns S

Region74AC74

Setuptime

Holdtime

PropDelaytCHQV

min

typ

1 ns

6.5 max

0 ns

-1.5ns

3 ns

1.5 ns 1 ns


9/19/02

Summary of the Restricted Region

unning near their maximum


p.5

Summary of the Restricted RegionThe setup and hold times define a restricted timeregion around the active clock-edge.The flip-flop’s input signal must not change in thatregion or the flip-flop’s output may:1) follow the change in D.2) not follow D.3) follow it halfway (go metastable).

MetastabilityMetastability is when a flip-flop balances at “1/2”trying to make up its mind whether to go to a 1 or 0.

The flip-flop will eventually go to either a 1 or a 0.Usually this will happen in less than a clock cyle.

Normally metastability is a problem only for flip-flops rspeed.

D INPUT

Q

CLOCKHold time

Setup time

Q followed D

Q did not follow DQ

Q metastableQ went


9/19/02

Synchronous and Asynchronous Signals

he restricted region around

e.

they don’tbecome

off stage.

Assume

asynchronous


p.6

Synchronous and Asynchronous SignalsA synchronous signal is one which cannot change in tthe clock edge.

An asynchronous signal can and will change anywher

FIG. 2-5 Three different D inputs.The upper two are synchronous;

they do not change in the restricted region.The lower one is asynchronous;

it has a transition inside the restricted region.

1DC1

QCLOCKD in D in; Synchronous

CLOCK

Restricted Region

D in; Asynchronous

D in; Synchronous


9/19/02

Making an Asynchronous Signal Synchronous

s.

restricted region.

m sending the upper

will sychronize it provided:

flip-flop designed since ‘75

ning close to


p.7

Any signal which passes through a flip-flop is synchronou

The clock-to-output propagation delay, tCHQV,

will give enough delay to move the Q edges out of the

The Q signal in FIG. 2-6 is synchronous and results frosignal through a D flip-flop.

FIG. 2-6 The Q output of a flip-flop is synchronous.The exceptions are unlikely and mentioned below.


Conditions to assure synchronous output

Sending an asynchronous signal through a D flip-flop

a) t CHQV)Min > tHOLD This should not happen in any

b) Metastability is not a problem.It is a problem for flip-flops runmaximum clock speed.

1DC1

QCLOCK

D D; Asynchronous

CLOCK

Restricted Region

Q; Synchronous

tCHQV


9/19/02


cle,

egion,

the 1st, or on the 2nd edge.

Fast pulseClk

aught on 2nd edge

me

aught on 1st edge

a D flip-flop


p.8

When is an Input In the Restricted Region Captured?

Don’t consider inputs with pulses shorter than a clock cyone must use an asynchronous pulse-catching circuit.

Consider inputs over 2 clock cycles long.Then an asynchronous input change in the restricted r

• will be captured on this clock edge• or the next clock edge.

FIG. 2-7 Synchronizing an asynchronous input.The change in the restricted region will either be caught on

1DC1

Q

CLOCK

DCLOCK

c

D; Asynchronous

Q; Synchronous

Nonhousebrokenasynchronousinput

Hold ti

tCHQV,

c

cleansynchronizedoutput

SYNCHRONOUSCIRCUIT

An asynchronous input may be synchronized by sending it throughbefore allowing it into a synchronous circuit.


9/19/02

Input Races Into Synchronous Circuits

o different flipflops.n around the clock edge.ividual flip-flops timing. did not.

is not what was desired.

flipflops may cause an error.

State Next State

A B X=0 X=1

00 01 10

01 01 00

10 00 10

11 00 00

B = 11 as the next state, thiscompletely wrong as would0


p.9


A race between an input and the clock

The state machine shown has the x input going into twThis is satisfactorily until x rises in the restricted regioThen, whether x is captured or not, depends on the indSince there are two flipflops, A might capture x while BThis would send the machine to state A,B = 1,1 which

FIG. 2-8 This illustrates how feeding an asynchronous input into two

1D

C1

B

This might give A = 0 or 1

11

00

1001

X=1X=0

1D

C1

ADA

DB

Asynch

A+ = A X B+ = B X

DB

DA

X

CLK

This might give B = 0 or 1

If it gave A

Restricted Region

would be be AB = 0

Asynchronous

X


9/19/02


problem.

100

110001

X=1X=0-11

000XSAN=0 XSAN=1

State graphincluding FF-X


p.10

Feeding X to a single synchronizing flip-flop, removes the

FIG. 2-9 The problem is cured by synchronizing the signal X.Then both flipflops react to the same X.The only states that can be reached from 00 are 01 and 10.

1DC1

B

XSANITARY IS A GOOD SYNCHRONOUS SIGNAL

1DC1

ADA

DB

X

A+ = A XSAN B+ = B XSAN

DB

DA

X

CLK

DA AND DB ARE NOW SYNCHRONOUS

Restricted Region

1DC1

(Sanitary X)XSAN

XSAN

00

1001

XSAN=1XSAN=0

11

FF-XUsing XSAN as inputinstead of X.FF-X is not included in these states.


9/19/02

Synchronization Without Extra Flipflops.

variables.

iable.). to.

les.h map (one variable different).

is sensed..

State Next State

A B X=0 X=1

00 01 11

01 00 00

10 00 00

11 00 00


p.11

Synchronization Without Extra Flipflops.An extra synchronizing flip-flop may not be necessary.

The two child states 01 and 10 in FIG. 2-9. differ by twoThus the X input affects two flip-flops.

In FIG. 2-10 the two children differ in only one state varThe X input affects only one flip-flop (one state variableThis flip-flop (state variable) is the one X is connected

The parent and the child can differ in many state variabThe children must have adjacent states on the Karnaug

FIG. 2-10 This state table has a branch where the asynchronous inputThe two child states of the branch differ in only one variableThis makes the input directly affect only one flip-flop.There will be no race if X changes near the clock edge.

1DC1

B

10

00

1101

X=1X=0

1DC1

ADA

DB

X

A+ = A B X B+ = A B

CHILD STATES

PARENTSTATE


9/19/02


at a time.

put.

only one flip-flop.

ble.gh map.

S0

S2S1

X=1X=0

=101 S2=111∆=1


p.12

Assigning State Variables With Asynchronous Inputs

An asynchronous input must change only one flip-flopIt must not simultaneously feed two flipflops.

Often a single D-flip-flop is added to synchronize the inHowever this is usually unnecessary.Proper state assignment will allow the input to change

A single bit difference in the statesis equivalent to a single flip-flop changing.

FIG. 2-11 This state assignment is safe if X only changes one flip-flop.The states affected by X must differ by only one state variaThis means states S1 and S2 must be adjacent on a Karnau

S1 S2S1 is adjacent to S2

01 11 1000

0

1

Correctly groupedstate assignment S1


9/19/02


). See next section

), (S3, S4).to change the same flip flop

ror”?

S0

S4S1

XY=00XY=11

S3S2

XY=01 XY=10

PARENT

e variable controlled by X


p.13

State Assignment for a 4-Way Branch

The variables must be logically unrelated (not encoded

Two children with the same X must be adjacent.

Two children with the same Y must be adjacent.

FIG. 2-12 In a two-variable 4-way branch,Two children with the same X must be adjacent, like (S1, S2Then placing the pairs (S1, S2) and (S3, S4) together forces Y(B) for both pairs.

If X and Y both change on the clock edge, what is the worst “er

S1 is adjacent to S2; Both have Y=1S3 is adjacent to S4; Both have Y=0S1 is adjacent to S3; Both have X=1S2 is adjacent to S4; Both have X=0 S1

Correctly groupedstate assignment

01 11 1000

0

11

1S2

0

1S4

0

0S3

1

0

X

Y

stat

B

1DC1

ADA

DBY

X

1DC1 C=1 independent of the branch

1DC1

C \ AB


9/19/02

One Input Controlling Branches From Different

ates

nt times.

S1 S2

01 11 10

ed state assignment

S7

S9S8

X=1X=0

6

S9 S8

∆=1


p.14

One Input Controlling Branches From Different Starting St

FIG. 2-13 One asynchronous input X controlling branches at differeThe changes in X may be sent to different flip-flops.

S0

S2S1

X=1X=0

00

0

1

Correctly group

S

B

1DC1

ADA

DBX

1DC1 C = 1 before the branch from S0 -> S1 or S2

1DC1

0

= 0 before the branch from S7 -> S8 or S9

∆=1


9/19/02

Self Loops

bit.

op.iable. map.

S0

S1X=1X=0

∆=1


p.15

Self Loops

Self loops can make a state its own child.The children must still differ by only on bit.The parent and the other child must differ by only one

FIG. 2-14 This state assignment is safe if X only changes one flip-flThe states affected by X must differ by only one state varThis is states S0 and S1 must be adjacent on a Karnaugh

S0 S1S0 is adjacent to S1

01 11 1000

0

1

Correctly grouped

state assignment


9/19/02

Summary So Far

e D flip-flop

hild states


p.16

Summary So Far

Each asynchronous input change must be captured by only onwhen entering a synchronous circuit.

If a parent state branches on an asynchronous input the two creached by the branch must differ by exactly one bit.

BUT THIS MAY NOT BE ENOUGH!


9/19/02

Examples

it

the computer. other great things.

ct, but is not shown.

not how would you fix it?.

THK

MICROCOMPUTER

MICROCOMPUTERCLOCK

CONNECTION TOPARALLEL PORT.THIS IS OK


p.17

Examples

PROB 2.1 A Single Asychronous Input to A Synchronous Circu

This is for the Olympics. The timing results are read byThe computer separates start, stop and lap times, andThe counter counts in binary.All the flip-flops run from the microcomputer clock.Appropriate flip-flop reset circuitry exists, and is corre

Would you consider this circuit reliable all the time? If

C1

1DREGISTER OF 4D FLIP-FLOPS WIA COMMON CLOCEN

C1

1DEN

C1

1DEN

C1

1DEN +5 Sports Minded

Pusher

Circuitry for a binary counter

Co

mb

inat

ion

al L

og

ic C

ircu

itry

Mad Button

C1

1D

1D

1D

1D


9/19/02

Examples

ter.

ps may count and others may

MICROCOMPUTER

MICROCOMPUTERCLOCK

Sports Minded

Pusher Mad Button


p.18

SOLN 2.1 Interfacing to Synchronous Circuitry

Yes, the button needs debouncing, but you can do bet

The EN signal is asynchronous.If the button is pushed on the clock edge, some flip-flonot.

An EN signal must be captured by only one flip-flop.

FIG. 2-15 A better Olympic Timer.

C1

1DEN

C1

1DEN

C1

1DEN

C1

1DEN

+5

Circuitry for a binary counter

Co

mb

inat

ion

al L

og

ic C

ircu

itry

C1

1D

1D

1D

1D

C1

1D


9/19/02

Examples

.

to be pushed.state.

X=0

X=1

0=0000

S1=1110

S2=1100

S5=1001

S3=1000

1101

RESET

Y=1Y=0

+5RESET


p.19

PROB 2.2 Asynchronous Input Problem

A finite state machine has the partial state table shown

Every morning the machine is reset. It then waits for XOn Friday the 13th it always seems to come up in bad It does not wait for X to be pushed like it should.

FIG. 2-16 What is wrong with this design?

C11D

C11D

C11D

C11D

Finite-State Machine

Co

mb

inat

ion

al L

og

ic C

ircu

itry

R

R

R

R

S

S4=

+5

X

Y

+5

CLKQ1

Q2

Q3

Q4


9/19/02

Examples

by one bit as required (∆=1).r by one bit as required

100, 0010, or 0110.

RES

CL

X=0

X=1

=0000

S1=1110

2=1100

S5=1001

S3=1000

101

ESET

Y=1Y=0

+5RESET

∆=1

∆=3

∆=1


p.20

SOLN 2.2 Asynchronous Input Problem

The X and Y inputs are not a problem.

X switches between S1=1110 and S2=1100 which differY switches between S4=1101 and S5=1001 which diffe

The RESET signal is asynchronous.Coming out of RESET on the clock edge, may send one to state 1110, 1100, 1000, 1010, 0

One cure is to synchronize RESET.

FIG. 2-17 A better reset for the finite-state machine

11100

000 1

1100

000

ET

K

C11D

C11D

C11D

C11D

Finite-State MachineC

ombi

natio

nal L

ogic

Circ

uitr

y

R

R

R

R

S0

S

S4=1

R

+5

X

Y

+5Q1

Q2

Q3

Q4

C1

1D

CLKCLEAR

CLEAR=1

Note:SO is itsown child


9/19/02

Synchronizing Reset

ops.

hed.

+5RESET

EDGE


p.21

Synchronizing Reset

Clocked Reset

Watch out for synchronous reset (Rsyn) built into flip-flRsyn must not be fed an asynchronous signal.

FIG. 2-18 The circuit must not come out of reset on a clock edge.

The RESET signal should be synchronized on release.

It is not necessary to synchronize the start of RESETThere is no false state one can enter when reset is pus


CLK C11D

1RsynC1

1D

1RsynC1

1D

1Rsyn

CombinationalLogic

CLEAR

ONE CAN STILL COME OUT OF RESET ON THE CLOCKONE CAN STILL START UP IN A BAD STATE


9/19/02

Synchronizing Reset

the clock from reaching cer-

er flip-flops from resetting.

+5RESET

C1

1D

+5RESET

C1

1D


p.22

Do not synchronize going into reset .

Resetting clock dividers and resynchronizers can keeptain flip-flops.Thus those flip-flops cannot be reset.

FIG. 2-19 Resetting the clock divider stops the clock and keeps the oth

FIG. 2-20 The preferred reset signal.Asynchronous apply.Synchronous remove.


CLK C11D

1RsynC1

1D

1RsynC1

1D

1Rsyn

CombinationalLogic

Clock Divider

CLEAR

C11D

RC1

1D

R

Fast CLEAR applicationClocked CLEAR removal

CLEAR CLEAR

RESETCLK

Reset push at clock edge is applied immediatelyReset let up, is delayed till safely after clock edge.


9/19/02

Synchronizing Reset

1000, 1010, 0100, 0010, or 0110.

.

X=0

X=1

00

S1=1110

00

S5=1001

S3=1000

T

Y=1

+5

S1=0100

∆=1

∆=1

∆=3

∆=1

Make allchildren

differ by one bit

Forget the parents


p.23

SOLN 2.2a Asynchronous Input Problem. Another Solution

Releasing RESET on the clock edge, may send one to 1110, 1100,

State S0 has children S0 and S1; note ∆ =3.

Before we synchronized RESET with a flip-flop.

Alternately make state S1 only 1 bit different from S0.Coming out of RESET can then go only to 0000 or 0100

FIG. 2-21 Fix machine state assignment

C11D

C11D

C11D

C11D

Finite-State MachineC

ombi

natio

nal L

ogic

Circ

uitr

y

R

R

R

R

S0=00

S2=11

S4=1101

RESE

Y=0

+5

X

Y

+5Q1

Q2

Q3

Q4

RESET

C1

1D

CLK

NotNeeded

Note:SO is itsown child


9/19/02

The Problem With Encoded Signals

ncoded Variables

ng,.

thers are not.

t a 4-bit reading.

ratures.

s on the fire sprinklers.


p.24

Asynchronous Inputs of Logically Related or E

The Problem With Encoded SignalsWhen signals on several wires have a collective meanibe careful about how they enter a synchronous circuit

What will happen if some of the bits are received and o

Examples of signals with a collective meaning are:binary numbers,ASCII characters,and bus addresses in microcomputers.

An Example Using Logically Related Signals

Consider a digital-temperature sensor which sends ou

Readings from 0000 to 1110 are interpreted as a tempeThey are used to control heating and air-conditioning.

A reading of 1111 is too high for normal use and it turn


9/19/02

The Problem With Encoded Signals

flops.rinkler

captured and some not.

prinklers.

HRONOUSCUIT

To furnace

nce in timingdifferencelatched.


p.25

FIG. 2-22 The four digital wires are each synchronized by four D-flip-The synchronous circuit controls the furnace and the fire sp

Suppose several thermometer bits change at once,for example 0111 (7˚) to 1000 (8˚).

When this happens on a clock edge, some bits may be

In the worst scenario 1111 is capturedand the sprinklers are turned on.

FIG. 2-23 If Z is captured a little early and W, X and Y a little late.The synchronous circuit would read 1111 and turn on the s

W

CLK

XYZ

C1

1D1D

1D1D

DIGITAL THERMOMETER4-BIT OUTPUT

FABRIQUE AU CANADA

SYNCCIR

CLKWXYZ

1110 1

000 A slight differe

makes a large in the number


9/19/02

Nonencoded Signals Cause No Problems

g them on for one clock cycle.

-n

hange,


p.26

Nonencoded Signals Cause No Problems

FIG. 2-24 If instead of being encoded, suppose:W turned on a heater in the wash room,X turned on a heater in the bedroom,Y turned on a heater in the kitchen,and Z turned on a heater in the greenhouseIf W, X and Y were slow in being captured, it only delays turnin

CLKWXYZ

1110 1

000 A slight difference in

timing in the flipflopsonly causes a one clockcycle delay in turning o

Washroom

BedroomKitchenGreenhouse corresponding heaters.

Logically related or encoded inputs must have at most a single bit cduring the time they are being captured by a synchronous circuit.


9/19/02

Asynchronous Inputs Which Change Only One

lly related) signals:

a Time

m.

≈ 1100≈ 1101

˚ ≈ 1111˚ ≈ 1110˚ ≈ 1010˚ ≈ 1011˚ ≈ 1001˚ ≈ 1000


p.27

How to Synchronize Encoded SignalsWe will give three methods of treating encoded (logica

1) One variable changing at a time.2) Handshaking3) Debouncing

Asynchronous Inputs Which Change Only One Variable at

Gray Codes

Gray codes are binary encodings of numbers.They change only one bit at a time.Their are many of them.Gray codes can be read off a Karnaugh map.

FIG. 2-25 Follow a trace through the Karnaugh map.Writing down the squares in the order you pass through theThe common reflected Gray code is shown.

00 01 11 1000

ABCD

01

11

10

0˚ ≈ 00001˚ ≈ 00012˚ ≈ 00113˚ ≈ 00104˚ ≈ 01105˚ ≈ 01116˚ ≈ 01017˚ ≈ 0100

8˚9˚

101112131415

∆=1


9/19/02


mperatures.

1˚. is already at 14˚.

system

8˚ ≈ 11019˚ ≈ 11000˚ ≈ 10001˚ ≈ 10012˚ ≈ 10113˚ ≈ 10104˚ ≈ 1110

RE ≈ 1111

SYNCHRONOUSCIRCUIT


p.28

FIG. 2-26 Another Gray code which starts at 0000 and ends at 1111.Follow the map trace and equate these binary codes with teThe resulting temperatures change only one bit at a time.If they change on a clock edge, the error is never more thanOne can never get to the FIRE state unless the temperature

FIG. 2-27 False-bath resistant controller for the furnace and sprinkler

00 01 11 1000

ABCD

01

11

10

0˚ ≈ 01001˚ ≈ 00002˚ ≈ 00013˚ ≈ 00114˚ ≈ 00105˚ ≈ 01106˚ ≈ 01117˚ ≈ 0101

11111

FI

cold

FIRE

4˚

10˚

W

CLK

XYZ

C1

1D1D

1D1D

DIGITAL THERMOMETER4-BIT GREY CODE OUTPUT

GR

EY

CO

DE


9/19/02


it at a time.tween the flipflops.

the flipflops.

requencies.XYZ with a slower circuit.

d between readings,

uit.

time.

0000011111

Z

MainCircuitDifferentClock


p.29

Johnson Counters

Johnson or Mobius counters change only one output bThe counter is very fast because there are no gates be

FIG. 2-28 A Johnson counter. The clock line is shown running behind

Use a fast Johnson counter to measure square-wave fUse the square-wave to clock the counter, and read VW

The pattern tells exactly how many cycles had occurre provided it is less than ten.

The Johnson counter is asynchronous to the main circBut the VWXYZ signals can be latched without races.There is no race if only one of the signal changes at a

0 0 0 01 0 0 01 1 0 01 1 1 01 1 1 11 1 1 10 1 1 10 0 1 10 0 0 10 0 0 0

SIGNAL1 Ghz

1D 1D 1D 1D1D

YXWV

C1 C1 C1 C1 C1

Not the same clock


9/19/02


ter.

W

XY

Z

SYNCHRONOUSCIRCUIT


p.30

FIG. 2-29 This Johnson counter is a fast, asynchronous clocked, counIt is suitable for latching directly into a synchronous circuit.However watch out for metastability.

CLK

C1

1D

1D

1D

1D

JOHNSON COUNTER

FABRIQUE AU CANADA1D

C11DC1

1DC1

1DC1

1DC1

1D

HIGH-

INPUTFREQUENCY


9/19/02


the flash A-to-D.ed. in the circuit.

eter.

1

1

1

1

.7 V

” if (V+ - V-) > 0

” if (V+ - V-) < 0


p.31

Thermometer Code

The fastest analog-to-digital converter known is calledIt is also the most expensive if much accuracy is desirIf one needs n bit accuracy, one needs 2n comparators

FIG. 2-30 Schematic of a 4-level flash A-to-D converter.The output is called a thermometer code.The bit pattern rises and falls like the mercury in a thermomNote that only one bit changes at a time.

R

R

R

R

+5.0 V REFERENCE

+4.0

+3.0

+2.0

+1.0

ANALOGVin

0000

1000

1100

1110

Vin=0.4 1.1 2.6 3.3 4

V+V- Vout =

'1

'0


9/19/02


synchronous machine input.e clock edge.

onous circuit.

s.

e.

hange outputs.ve transient outputs.

code output.

V4V3V2V1

SYNCHRONOUSCIRCUIT


p.32

A Flash Converter Interfaces Directly

A flash-A-to-D converter can be directly connected to aThe worst error is reading the old voltage just before th

FIG. 2-31 A flash A-to-D is suitable for latching directly into a synchrHowever watch out for metastability.

Code Conversions

The thermometer code is too long for most application

Usually a thermometer-to-Gray-code conversion is donThis maintains the single change at a time.

One cannot convert binary to Gray code to get single-cIf the binary changes 0111 -> 1000 (3 to 4), it might ha

0111->0011->0001->1001->1000Each transient output would generate a transient Gray

CLK

C1

1D1D

1D1D

THE FLASHANALOG INPUT


9/19/02


gh D4 below) are stable.

wn duration.

he handshake =1.s high.e stable near the clock edge.

CLK

V4V3V2V1

UIT


p.33

Handshaking Methods

One and only one signal is the handshake.

It is made true only after all associated lines (D1 throu

If handshake = false:the associated lines may not be stable.

If handshake = true:the associated signals will be stable for some kno

The known duration may be:one or more clock cycles,until the handshake goes false,some other convention.

FIG. 2-32 All the associated signals, D1 through D4, are stable when tThe handshake is captured on the 1st clock edge after it goeThe latched ENABLE then lets through D1..D4 which will b

THE GADGETHANDSHAKE

1DC1

QENABLE

D1D2D3D4

SYNCHRONOUS CIRC


9/19/02


CLK

V4V3V2V1

IT

fore HANDSHAKE rises

nous

e at clock edge

4 were not


p.34

FIG. 2-33 FIG. 2-32 repeated

FIG. 2-34 Typical waveforms for the circuit of FIG. 2-32

THE GADGETHANDSHAKE

1DC1

QENABLE

D1D2D3D4

SYNCHRONOUS CIRCU

D1D2D3

D4

HANDSHAKE

CLK

V4

V3V2V1

ENABLE

The Ds may change here, but they must be stable be

ENABLE is synchronous

V1, V2, V3 and V4 are synchro

Handshake could com

even though D1, D2, D3 and D


9/19/02


efore the associated signals.

E rising and the associated

ilize after HANDSHAKE rises.

.

YNCHRONOUSCIRCUIT


p.35

The Less Restricted Handshake

It is not necessary for the HANDSHAKE signal to rise b

One only needs a know delay between the HANDSHAKsignals stabilizing.

D1 through D4 below, have almost a clock cycle to stab

FIG. 2-35 The HANDSHAKE signal is latched on the first clock edge.D1 through D4 are latched on the second clock edge.They need only stabilize a setup time before the second edge

CLK

C1

1,2D1,2D

1,2D1,2D

THE GADGET

V4V3V2V1

SEN2HANDSHAKE 1D

C1Q ENABLE

D1D2D3D4

The tug-of-war synchronizer works this way


9/19/02


YNCHRONOUSCIRCUIT

re the 2nd clock edges


p.36

FIG. 2-36 FIG. 2-35 repeated.

FIG. 2-37 The HANDSHAKE signal is latched on the first clock edge.The D signals are latched on the next edge.They need not be stable until they are ready to be latched.

CLK

C1

1,2D1,2D

1,2D1,2D

THE GADGET

V4V3V2V1

SEN2HANDSHAKE

1D

C1Q ENABLE

D1D2D3D4

D1D2D3

D4

HANDSHAKE

CLK

V4

V3V2V1

ENABLE

The Ds may change until a setup time befo

ENABLE is synchronous


9/19/02


ve readings.

ged,

ACCEPT DATAWORK ON IT.


p.37

Debouncing

Latches the asynchronous data several times.Accepts it when all bits are the same on two consecuti

This method is good if you know the inputs, once chanwill stay stable for several clock cycles.

FIG. 2-38 A flow chart of a system to sychronize data by Debouncing.

LATCH DATA

WAIT 1 CLOCK CYCLE

LATCH DATA AGAIN

ARE BOTHCOPIES OF DATA

THE SAME?

NO YES

record

wait

record

compare


9/19/02


DATA OK

ARE

it compare


p.38

Debouncing in Hardware

FIG. 2-39 A circuit that reads data,shifts the old data into a new set of flipflops,and reads the data again.Then it compares the two reads.

C1

1D1D

1D

C1

1D1D

1D

AS

YN

CH

RO

NO

US

INP

UT

DIGITAL COMP

XNOR is a two-b

record wait record compare

D1D2D3

V1V2V3


9/19/02


the photocell.ctioned correctly.

the register shown.rrect coconut count.embarrassment.

ct, but is not shown.

5WITHOCK

MICROCOMPUTERCLOCK

MICROCOMPUTER

CONNECTION TOPARALLEL PORTTHIS IS OK


p.39

PROB 2.1 The Coconut Counter

The following circuits counts coconuts as they fall by The original circuit only lit the display. That always fun

Then a consultant added the computer interface usingEvery once in a while the computer reads a wildly incoThis sometimes gets printed on invoices and leads to

Fix the interface design.Appropriate flip-flop reset circuitry exists, and is corre

Note coconuts do not fall at supersonic velocities.

C11D

C1

1D

1D

1D

1D

1D

C11D

C11D

C11D

C11D

COCONUTS

PHOTOCELL

REGISTER OF D FLIP-FLOPS A COMMON CL

FALLING BY PHOTOCELL

RIPPLE COUNTER

P


9/19/02


ls.r is changing.


p.40

SOLN 2.1 The Coconut Counter

Comments:

• The ripple counter clocks on the rising edge.• It may ripple for one or two clock cycles.• The counter output is encoded asynchronous signa• The register must not capture data while the counte•

Debouncing Solutions

Read the count in two consecutive cycles.If they are the same, the counter was stable.

Software debouncing

If you have control of the software,do the debouncing in software!

Hardware debouncing is excessively complex.


9/19/02


k-edgesre equal.

MICRO

CLOCK

MIC

RO

CO

MP

UT

ER

COMPUTER

parator

EG3Accept if high


p.41

Hardware debouncing

FIG. 2-40 Circuit to pass only stable data to the computerThe circuit compares data captured on two consecutive clocThe output register is enabled when the two data-samples a

RIPPLE COUNTER

C1

1D

1D

1D

1D

1D

C1

1D

1D

1D

1D

1D

C+

[16]

RCNTR

[8]

[4]

[2]

[1]

=

=

=

COMPARE

ENC1

1D

1D

1D

1D

1D

XNOR is a two-bit com

REG1 REG2 RP

Asynchronousinput

record recordwait


9/19/02


stable before H rises.

MICRO

CLOCK

MIC

RO

CO

MP

UT

ER

COMPUTER

EG3

take 2 cycles)


p.42

Handshaking Solutions

FIG. 2-41 Constructing a handshaking signal to enable REG3The ripple counter only changes after a rising edge of P.H is low before the rising edge and disables REG3.H is delayed by enough flip-flops to be sure the ripple-counter is

RIP

PL

E

C1

1D

1D

1D

1D1D

C+

[16]

RCNTR

[8]

[4]

[2]

[1]

EN RC1

1DC1

1DP H

coconut goes byP

CLK

H

ripple counter active

REG3 enabled

CO

UN

TE

R

2 cycle delay (because ripple may

2 cycle delay

Ripples for one or twoclock cycles


9/19/02


ock cycle.

MICRO

CLOCK

MIC

RO

CO

MP

UT

ER

COMPUTER

EG3

MICRO

CLOCK1

MIC

RO

CO

MP

UT

ER

COMPUTER

REG3


p.43

Handshaking Solutions (cont.)

FIG. 2-42 A handshaking signal for a fast ripple counterThe new count must ripple-through the counter in under one clThe D flip-flop synchronizes the P signal.The counter is stable before the next clock edge.

FIG. 2-43 Add delay if ripple-through takes over a cycle.

FAST

C1

1D

1D

1D

1D

1D

C+

[16]

RCNTR

[8]

[4]

[2]

[1]

EN RC11D

H+5

PsynP

RIPPLECOUNTER

C

1D

1D

C+RCNTR

[2]

[1]

ENC11D

HPsynP

[4]

C11D

C11D

two cycle delay

D

CLKPsyn

H


9/19/02


with speedy coconuts

MICRO

CLOCK

MIC

RO

CO

MP

UT

ER

COMPUTER

EG3

REG3 enabled

).


p.44

FIG. 2-44 Opposite edge (level) solutionThe counter counts when rises.P stays high long enough for the ripple count to complete, even H is low when the ripple-through takes place.H enables REG3 long after the ripple.

Psyn

C1

1D

1D

1D

1D

1D

C+

[16]

RCNTR

[8]

[4]

[2]

[1]

EN RC11D

HPsynP

RIPPLECOUNTER

coconut goes by

Psyn

PCLK

H

ripple counter active

REG3 enabled

Check other edge too (It’s OK here


9/19/02

Glitches Will Cause Errors

ere.

uts.

nchronous signals.ry hard to avoid multiple varia-

the logic in the synchronous


p.45

Hazards in Asynchronous Inputs

Glitches Will Cause ErrorsIf an asynchronous input has a glitch on it,and if that glitch comes in the restricted region,then it may be captured as a valid input.

Sending the signal through a D flip-flop will not work hThe flip-flop could also capture the glitch.The cure is to remove glitches from asynchronous inp

One should be very careful about doing logic with asyWhen two or more signals feed a logic network it is veble glitches.

Try to synchronize the individual variables and then dopart of the circuit.

C11D


9/19/02


.

Write

Read comparatorevery sec.

Next clock cyclereset binarycounter

0


p.46

Example From Educational Literature

PROB 2.1 Motor speed control.

The binary counter counts sensor pulses for 1 secondThe count is compared with the setpoint register.A FAST or a SLOW, or neither is sent to the controller.There is a slack of ±3 to avoid hunting.

Suggest some problems and some cures.

FIG. 2-45 A potential hazard

CounterBinary Set point

Register

Digital Compare

ω>s-3 ω<s+3

ω s

SynchronousController

10R

FAST

SLOW

1

clk


9/19/02


lines.

SLOW

FAST


p.47

SOLN 2.1 Hazardous Motor Speed Control

A binary counter is full of glitches.A glitch may be caught by the FAST, the SLOW, or both

Assume a Gray code counter.The ±3 keeps saves the design.If FAST and SLOW were 1 count apart,there could be a double transition from SLOW to FASTon the last motor pulse.

Is the reset clean?Yes, because it synchronous.

Do glitches matter on a motor control?No, a good low-pass filter is a great glitch minimizer.


9/19/02

Methods of Dealing With Multiple Changes

hronous analysis

uble change.

lity that it will happen.

ded.sign may be good enough.


p.48

Concurrent Input Changes

Methods of Dealing With Multiple ChangesMultiple variable changes were “not allowed” in asyncThe method could not deal with them.

State table analysis may still give a solution:

“Go ahead and sue me” method

Calculate all the states reachable from the potential doThis may be all states!Calculate the cost of such a transition and the probabi

If it will poison the city water supply, more work is neeIf it will make your talking doll say a bad word, your de

Interlock the input

Asynchronous arbiters can be designed.An example follows.


9/19/02

The Tug-of-War Arbiter

t button pusher.

er.

off the end of the display.

BR2

Player 2

CLOCK


p.49


FIG. 2-46 The tug -of-war game.

Playing the Game

Push reset.

After a random time the centre LED comes on.Then each player will try to push his button first.The position of the lit LED will move toward the fastesIf player 2 is fastest, the light shifts LED 0 -> LED 1.End of round one.

After a second the LEDs will all go out.After a random time LED 1 will come on.Again each player will try to push his button first.Again the light will shift toward the fastest button push

The game is won when the position of the lit LED move

Contents:3 push-buttons,5 light-emitting diodes (LEDs)1 field-programmable gate array

BL

RESET

-2 -1 0 1Player 1 LEDs


9/19/02


chnology can make it.n delay of two inverters.

yer.

ir button first.ounce properties of the push

cked logic because of glitches

RESET

2 CLOCK

ic


p.50

Specifications of the Push-Button Latch

FIG. 2-47 The synchronous and asynchronous parts.

The push button circuit shall be as fair as modern tei) It must tell who pushed first within the propagatio

ii) It shall have no theoretical bias toward one player.

iii) If your circuit goes into a tie state, it shall either:- have equal probability of exiting toward either pla- leave the light stationary for that round.

iv) It should not depend on which player releases theIn a tie, this lets the winner be determined by the bbuttons.

The Synchronizer:i) Shall not transfer the wrong information to the clo

or pushes near the clock edge.ii) A tie shall not be transferred as a win.iii) A win shall not be transferred as a tie.iv) The wrong winner shall not be transferred.

BL

-2 -1 0 1LEDs

BR

AsynchronousPush-Button

CircuitC1

1D

Synchronizer Clocked Log


9/19/02


AB

P,R/L=1,1

BR=1

Clear=1

=1

r=1

P,R/L=0,0

BL,BR=x,x

BL,BR=0,0

BR

Clear

B=01A=00

assignments for the latch.


p.51

FIG. 2-48 The State Diagram for the Latch.

FIG. 2-49 State Table for the State Diagram

BL,BR=x,x

The Push Button LatchState A........No button pushed since Clear.State B........Button 2 (right) was pushed first.State C........Button 1 (left) was pushed first.Input BL.......Left Button input.Input BR.......Right Button input.Input Clear...CLEAROutput P........PUSH; some button pushed.Output R/L....R(H)/L(L), High if BR was pushed

before BL; low if BL preceded BR

CBL

CleaP,R/L=1,0

BL

Clear

C=10

A race free statePres Next State OutputState Inputs= BL, BR, Clear

000 010 110 100 - -1 P, R/L

A A B - C A 0 -B B B - B A 1 1C C C - C A 1 0D - - - - - -

Circled states are stable. - = don’t care


9/19/02


a tie.

race.stead go 00 -> 10 or 00 -> 01,

in.

BR=1

Clear

B=01A=00

ith all defaults A.

D=11BR,BL=0,0; 1,1

ut change” rule


p.52

Handling the double input change

Take all the don’t care states and fill them in with.State A initially looks reasonable. It causes no bias on

FIG. 2-50 State table with all default states made “A.”

If both buttons are pushed at once:

• A tie does not have a bias toward either side.• Pushing two buttons together is a different kind of

It is true that the state change A=00 ->D=11, may inThis is just one side or the other winning.It is normal circuit operation for the faster side to w

BL=1

Clear

C=10

A State graph wPres Next State OutputState Inputs= BL, BR, Clear

000 010 110 100 - -1 P, R/L

A A B A C A 0 -B B B A B A 1 1C C C A C A 1 0D A A A A A -

For this problem, we have solved the “no double inp


9/19/02


ile BR,BL = 1,1.itch will lose.

s.

cycle. desirable.

ext State Output BL, BR, Clear

110 100 - -1 P, R/L

D C A 0 -A B A 1 1A C A 1 0A A A -

Cycle on tie


p.53

Side effects of this state table

a) When there is a tie, one stays in state A=00, only whIf a switch breaks contact the person pushing that swThis “lose on first bounce” is an avoidable unfairnes

FIG. 2-51 Push-button latch state tables that almost made it.

Questionable modification to the state table

b) Replace the “A” in the middle of a) by “D.”This cures the lose on first bounce, but makes a tie aAn oscillatory input to the synchronous circuit is not

Pres Next State OutputState Inputs= BL, BR, Clear

000 010 110 100 - -1 P, R/L

A A B A C A 0 -B B B A B A 1 1C C C A C A 1 0D A A A A A -

Pres NState Inputs=

000 010

A A BB B BC C CD A A

Lose on first bounce

a) b)


9/19/02


hazards.

xt State Output BL, BR, Clear

110 100 - -1 P, R/L

D C A 0 -B B A 1 1C C A 1 0D A A -

“lose on first bounce” on a tie

xt State Output BL, BR, Clear

110 100 - -1 P, R/L

D C A 0 -B B A 1 1C C A 1 0D D A -

ith a stable tie state.


p.54

More questionable state tables

FIG. 2-52 If you are fussy, the “don’t cares” are hard to fill in.

FIG. 2-53 One more dud, and the working table.

Don’t forget to check for hazards, races and essential


000 010 110 100 - -1 P, R/L

A A B D C A 0 -B B B B B A 1 1C C C C C A 1 0D A A A A A -

Pres NeState Inputs=

000 010

A A BB B BC C CD A A

The best of the oscillators. This will only cycle a A more subtle a few times. Hope they never come on the clock edge.


000 010 110 100 - -1 P, R/L

A A B D C A 0 -B B B D B A 1 1C C C D C A 1 0D D D D D D -

Pres NeState Inputs=

000 010

A A BB B BC C CD D D

Just dumb! Tie on first bounce. A good table w


9/19/02

The Push-Button Latch Circuit

t change near the clock edge

gnals should be sent throughchronous machine!

ke is captured.

chronous-Buttonircuit

C11D

SynchronizerG

H

CLKCLEAR


p.55

The Push-Button Latch CircuitThe final circuit has two latched outputs- G which indicates BL was pushed first.- H which indicates BR was pushed first. - When both are true there was a tie.

The Design of the Synchronizer Circuit The synchronizer circuit does two things:

• It sanitizes the asynchronous inputs so they cannoof the main synchronous machine.

• It makes sure G and H are both captured together.They are logically related signals.

Do not use the “general rule” that all asynchronous sia single D flip-flop before they enter the rest of the syn

A handshaking circuit

Generate a handshake whenever G and/or H change.

Synchronize the handshake.

Capture G and H the next clock cycle after the handsha

BL

BRAsynPush

C


9/19/02

The Design of the Synchronizer Circuit

ther.

nous

ous ENABLE


p.56

FIG. 2-54 The tug-of-war synchronizer using a handshake.

A change in G will lock out HA change in H will lock out G.Only during a Tie will they both change.

During a tie they will change close together.Waiting a clock after PUSH to capture G and Hensures they are both stable.

The sychronizer knows that changes in both G and H will be close togeWaiting a clock cycle after PUSH ensures stability in G and H.

SyPushPUSH1D

C1

PUSH

SyPUSH

CLOCK

asynchro

synchron

1D

C1EN

1D

C1EN

GSYNCH

HSYNCH

G

H G

GSYNCH

making asynchronous signals acceptable in a synchronous ...shams/elec3500/asynchronous.pdf ·...

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