Managing Pre-Technological Knowledge: A Multi-Dimensional Approach

Charles Weber

INFORMS Meeting, Pittsburgh, PANovember 6, 2006

ETMETM

Bohn’s Eight Stages of Knowledge• Quality of knowledge improves as process matures.

From R. Bohn, "Measuring and Managing Technological Knowledge,“ Sloan Management Review, Fall 1994, p. 63.

Stage Name Comment Typical Form of Knowledge

1 Complete Ignorance Nowhere

2 Awareness Pure art Tacit

3 Measure Pretechnological Written

4 Control of the mean Scientific method feasible

Written and embodied in hardware

5 Process capability Local recipe Hardware and operating manual

6 Process characterization

Tradeoffs to reduce costs

Empirical (numerical) equations

7 Know why Science Scientific formulas and algorithms

8 Complete Knowledge Nirvana

Learning in High Tech Manufacturing (Bohn, 1994, p. 64)

• “High tech manufacturing requires rapid learning about multiple variables in new products and processes.

• High tech processes are those in which many of the important variables are at stage 4 or below. – This makes the process difficult to control and to work with, – so a lot of effort goes into raising the knowledge level as quickly as

possible. • Because of customer and competitive pressures,

– no sooner is knowledge raised for one product than higher performance products are demanded,

– which brings in new low stage variables. • Thus managing in high tech industries requires both

– rapid learning and – the ability to manufacture with ‘immature’ (low stage of knowledge)

processes.”

Research Question:

• How does one manage low-stage (“pre-technological”) knowledge?

VLSI Semiconductor Manufacturing

• Bohn (1994) specifically cites VLSI semiconductor design and fabrication.– Hundreds of non-linear, potentially interdependent

variables– More variables are added as new products and

processes are introduced. – New variables start at low stages of knowledge.– This requires many changes in product and process

design.– Existing variables “regress” by a knowledge stage or

two.

Integrated (3-D) Framework for Concurrent Process Development (Weber, Moslehi, Dutta,1995)

• Discrete learning sectors {Q,PI,S}• Learning experience in each sector is unique.

Equipment Pass

Station Pass

Work Cell Pass

Process Layer

Process Module

VLSI Fab Cycle

Packaged Part 1 Month

1 Week

1 Day

1 Shift

1 Hour

Process IntegrationAxis

Intr

ins

ic D

ata

Cy

cle

Tim

e

Scaling Axis

0.7 um1.0 um

0.5 um0.35 um

0.25 um0.175 um G5

G4G3

G2G1

Systematic Mixed Random

Pro

ce

ss

Re

se

arc

h

Pilo

tD

ev

elo

pm

en

t

Co

mm

erc

ial

Sta

rtup

Vo

lum

eP

rod

uc

tion

1.5σ 3.0σ 4.5σ

10 1.0 0.1

Control

FD (cm-2)

DominantDefect Type

DevelopmentPhase

(Pisano, 1994)

QualityAxis

QualityMilestones

VPRe

CuSa

ESa

WSa

PrRe

Concurrent IC Process Development(Weber, Moslehi, Dutta, 1995; Weber and Utterback, 1996)

• Learning by conquering volume• The output of each sector feeds into adjacent sectors.

DevelopmentPhase

QualityAxis

PR PD CS VP

Scaling Axis

G1G2

G3G4

G5

ProcessGeneration

Process IntegrationAxis

Equipment Pass

Station Pass

Work Cell Pass

Process Layer

Unit Process

VLSI Fab

Packaged Part

Level of Integration

Isochrones

Specific Research Questions

• How mature is knowledge in each learning sector?

• How does the quality of knowledge evolve as a function of process maturity?

Preliminary Empirical Investigation

• Data come from (my dissertation)– 69 cases of learning and problem solving – in semiconductor manufacturing and process

development.– that transpired at 35 semiconductor facilities in Asia,

Europe and North America.– Each case is clearly associated with a particular

learning sector.

• Formal analysis has not yet taken place.• This is a work in progress.

Stages of Process Development(after Pisano, 1994, pp. 90-91)

• Process Research (PR) – “involves defining the basic structure of the process. … – The goal of process research is to define the basic process

architecture rather than the details.” • Pilot Development (PD)

– Scale up the process to some intermediate scale – Select reaction parameters (e.g. timing, temperature, pressure), – which optimize the efficiency of the process– Much more empirical in nature than process research – Relies on the analysis of the output of pilot production runs, – which are subjected to conditions that reflect actual production

environment more accurately. • Commercial startup (CS) involves ramping up the VLSI

circuit manufacturing process to commercial scale. • Volume Production (VP) at commercial scale

Levels of Integration(Weber, 1996)

• Full VLSI process (FP) yields VLSI circuits.

• Unit process (UP) – Consists of multiple process steps– yields electrically testable structures– 3 to 10 unit processes in a full process.

• Single process steps (PS)– 50 to 500 process steps in a full process

‘Baselining’ (Weber, 1996, 2003)

• Run current generation in same manufacturing line as previous generation

• Current generation shares ~75% of all process steps with previous generation.

• Advantages– Most key variables have high level of knowledge early

on in process development.– Problem solving: solution space shrinks

• If new VLSI process has low yield, • but the old one has high yield, • Then the problem is associated with new process steps

(~25%).

• Share whole unit processes with previous generation, if you can.

Knowledge Sectors and Stages of Knowledge

Current GenerationFP 1-3 3-5 4-6 4-6UP 2-5 4-6 4-7 4-7PS 4-7 4-7 5-7 5-7 Phase PR PD CS VP

Previous GenerationFP 1-3 3-5 4-6 4-6UP 2-5 4-6 4-7 4-7PS 4-7 4-7 5-7 5-7 Phase PR PD CS VP

time

Sca

ling

Quality

Inte

gra

tio

n

Observations• Level of knowledge decreases with level of integration.• Level of knowledge increases with process quality more rapidly at high levels of integration than at low levels.• Baselining: taking advantage of higher levels of knowledge of previous generation.• All more so in PR and PD than in CS and VP

Propositions

• ‘Knowledge bricks’ are intact.

• Knowledge architecture is not.

• How can we show this?

Organizational Differentiation and Integration (Lawrence & Lorsch, 1967-1969)

• Differentiation– is defined as “the state of segmentation of the organizational

system into subsystems (e.g. sales, research and production), – each of which tends to develop particular attributes in relation to

the requirements posed by its relevant external environment.”

• Integration is defined as “the process of achieving unity of effort among the various subsystems in the accomplishment of the organization’s task.”

• Completing a task requires a significant amount of knowledge that is differentiated with respect to relevant external environment of the various subsystems,

• and the differentiated knowledge of the various subsystems must be integrated to achieve unity of effort for the organization.

Organizational Differentiation and Integration (Lawrence & Lorsch, 1967-1969) • High performing organizations are required to be

both highly differentiated and well integrated. • These two goals are inherently at cross-

purposes, • unless individuals, teams or departments act as

intermediaries – or integrating devices – between the various subsystems.

• The presence of integrating devices would thus suggest low levels of integration knowledge.

• Their absence would suggest – high levels of integration knowledge or – that little integration knowledge is needed.

Data from my Dissertation (Weber, 2003)

Availability of Integrating Devices in Process Engineering Subsystems

Number of WorkEnviron-ments Situation at Work Environment29 Wafer factory runs full, state-of-the-art

process. Integrating device is available. 3 Wafer factory does not run full process.

No integrating device. 2 Wafer factory does not run state-of-

the-art process. No integrating device.

Implications

• Running full, state-of-the-art process requires integration knowledge,

• which tends to be at pre-technological levels of maturity (Stage 2 – 3)

• Is this inherently so?

• Subject warrants further investigation.

• I’ll give you an update in two years.