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Technology

In This Issue:• AerialImaging,theUltimateDefectClassifier

• NewCleaningTechnologyforAdvancedPhotomasks

• APCfor32nmDoublePatterning

• GriddedDesignRulesforContinuedCMOSScaling

V o l u m e 6 , I s s u e 2 , 2 0 0 8

Challenges and Solutions Through-SiliconVia Technology —

Publisher: Betty Newboe

Email: [email protected]

Chief Editor: Connie Duncan


Editor: Richard Lewington


Assistant Editor: Priya Gopalakrishnan

Advisory Board: Rudi Hendel, Ph.D.,

David Kyser, Ph.D., Omkaram Nalamasu, Ph.D.,

Reza Arghavani, Ph.D.

Nanochip Technology Journal is published by Applied Materials, Inc. in cooperation with United Business Media LLC © Copyright Applied Materials, Inc. 2008, for external use.

Cover Art: Elements Group

All trademarks so designated or otherwise indicated as product names or services are trademarks of Applied Materials, Inc. in the U.S. and other countries. All other product and service marks contained herein are trademarks of their respective owners.

Front Cover: The industry is moving to 3-D packaging using through-silicon vias. Deep Reactive Ion Etch (DRIE) is the preferred technology for this etch application.

www.appliedmaterials.com

One of the most exciting developments taking place in the IC industry is the work being done on through-silicon via (TSV) technology, an emerging solution for inter-connecting 3-D chip stacks. This new approach promises better device performance, lower power consumption, reduced costs and the integration of heterogeneous devices. In this issue, we highlight the challenges and progress being made in TSV formation with an exclusive article featuring the viewpoints of some of Applied’s leading tech-nologists in this area.

Applied is working on several different TSV approaches at its Maydan Technology Center (MTC), where we are focusing on unit process robustness, cost-effectiveness and integration. This effort leverages Applied’s broad range of process technologies and extends to several joint TSV projects with key industry partners and suppliers. Being able to use the MTC to leverage the broad range of Applied's process technologies, platforms and expertise gives us broader insight into overall manufacturability and the capability to deliver optimized and differentiated solutions.

Our research at the MTC on TSV etch processes is featured in an article that reviews both via-first and via-last applications. Since each of these have very different process requirements, the etch reactor must be flexible enough to handle both approaches. We introduce a new hardware and process scheme that provides excellent sidewall roughness without any trade-off in silicon etch rate.

Much of the other research discussed in this issue has also been conducted at the MTC, including the development of a new tantalum barrier process that addresses low k dielectric damage issues in advanced dual damascene interconnect structures and a demonstration of the use of integrated metrology to improve CD control in double patterning wafers.

Representing groundbreaking work in inspection technology, an article from our engineering team in Israel demonstrates that aerial imaging detection technology is the ultimate classifer between printing and non-printing defects, since it allows a very high detection rate without nuisance effects. This property can enable a simple migration from the 65nm node to beyond 32nm by tuning the detection limit.

In addition, we are pleased to present an article from Dr. Michael Smayling – an alum of Applied’s MTC and now of Tela Innovations – on one-dimensional gridded design rules (GDR). This approach has been shown to have a number of advantages over two dimensional cells, including smaller area, better gate CD control and the elimination of hotspots. The MTC scientists have also demonstrated 22nm logic cells with Tela by leveraging the emerging Self-Aligned Double Patterning process scheme at this year’s SPIE. Dr. Smayling predicts that 1-D GDR cells will enable continued simple scaling of CMOS logic to the 16nm node and beyond.

I hope that you enjoy this issue of the Nanochip Technology Journal and find the articles interesting and informative. Please feel free to contact me or the authors if you have any questions. We appreciate your comments and feedback.

A Message from Ken MacWilliamsVice President and General Manager of Applied Materials' Maydan Technology Center

To receive extra copies of the Nanochip Technology Journal or to add colleagues to the mailing list, please email the following information to:

[email protected]

• Name • Title • Company • Business address

Ken MacWilliams

2 Closed-LoopCDControlforSADPScheme

Integrated metrology improves wafer-to-wafer CD control and minimizes double patterning overlay errors.

8 PhotomaskCleaningfor45nmandBeyond

Photoresist stripping without using haze-promoting sulfuric acid-based chemistries extends mask lifetime.

23 VirtualMetrologyImprovesThermalUniformityforCriticalAnneals

Innovative approach can significantly reduce wafer processing errors, enhance yield and minimize production costs.

28 AerialImaging–theOptimalClassifierofPhotomaskDefectPrintabilityBreakthrough inspection technique filters out nuisance non-printing defects, allowing “true” defect detection.

33 GriddedDesignRules–1-DDesignEnablesScalingofCMOSLogic

Benefits of 1-D include smaller area requirement, better gate CD control, and elimination of hotspots.

38 InnovativeEndpointTechnologyOptimizesCMPProcessControl

In situ film thickness monitoring optimizes manufacturing yield and device performance.

42 NovelApproachExtendsPVDTa BarrierTechnologyto32nmandBelow New process preserves delicate low k trench

integrity, demonstrates excellent electrical and reliability performance.

46 ReducingLowkDamagewithCO2

PlasmaEtch CO

2 plasma has the potential to replace O

2 plasma

for the ashing process.

c o n t e n t s

Special Focus: TSV 14 Through-SiliconViaTechnologies—ChallengesandSolutions

19 DeepSiliconEtchforTSVIncreasesPerformanceandProductivity

Nanochip Technology Journal Issue Two 2008 1

Volume6,Issue2,2008

2 Issue Two 2008 Nanochip Technology Journal

Closed-Loop CD Control for SADP Scheme

I n teg ra ted Met ro l ogy

Wafer-to-wafer (WTW) critical dimension (CD) control through the implementation of integrated metrology (IM) has been applied to 32nm self-aligned double patterned (SADP) wafers. A standard deviation of 0.6nm in WTW hardmask CD, despite intentionally-created disturbances in incoming lithography and reactor conditions, demonstrated that tool-level IM is a robust capability for WTW CD control in the SADP scheme.

Keywords: Double Patte rning, SADP, Integrated Metrology, Advanced Process Control (APC), Overlay Error

There are two main double patterning approaches: double exposure (DE), which uses two masks, each containing half the features of the f inal pattern; and SADP, which generates identical pairs of features from a single mask. Our SADP scheme uses two layers of APF hardmask and nitride spacers to create dense, sub-32nm line CD circuit patterns using a 65nm photomask and non-immersion optical lithography.[1] If immersion lithography is used, the SADP scheme can be extended to the 22nm node. This line-by-space process f low (Figure 1) includes lithogra-phy resist trim, top APF etch, spacer for-mation (deposition and etch), strip of top APF (also referred to as core APF), and f inal pattern transfer from nitride spacers to bottom APF as a hardmask.

Two types of CD errors are commonly seen in double patterning. One is the line CD error, which refers to the CD variation of the lines from the design target after final pattern transfer. The other is the overlay error, which refers to the odd and even space between lines on the final pattern due to an offset between two patterning steps. In our SADP scheme, all the lines are derived from the same spacer deposition and etch process with good film thickness and CD uniformity control. As a result, the line CD error is greatly mini-mized. However, an overlay error can still occur in SADP. This is because of the dif-fering origins of the two types of spaces on the final pattern. The core space originates

from core APF, which is stripped later in the process f low. The gap space originates from the gap formed during spacer deposi-tion and etch. If the core APF CD deviates from the design target, then the core space and gap space will differ in CD and cause overlay error (Figure 2). Therefore, a very important objective of process control for the line-by-space SADP scheme is to deliver core APF CD within the upper (UCL) and lower (LCL) control limits and thus minimize the overlay error in the final pattern.

Core APF CD Control MethodThe exact overlay error specif ication is a matter of debate. The double expo-

Figure 1. SADP line-by-space process flow.

Final Pattern Transfer

Trim and Etch Core APF

STI Etch and Ash

Form Spacers

Strip Core APF

Patterning

Core APF

PR

Bottom APF


■ CD control for SADP

sure double patterning (DEDP) approach has demonstrated an overlay error of 5nm.[2] The SADP approach can signif i-cantly reduce the overlay error to 3-4nm because all features come from a single exposure. However, such overlay per-formance still may not meet the stringent requirement of DP, which some believe should be as low as 1nm. This level of control requires a good understanding of the process response function and the uti-lization of WTW APC.

For th is study, an integrated metrol-ogy (IM) system provided WTW APC with both feedforward (FF) and feed-back (FB) closed loop control. The IM system is at tached to the process tool so wafer s can be measured immedi-ately before and after processing. The most commonly used technology for CD measurement i s opt ica l scat ter-ometry, or opt ica l cr it ica l d imension (OCD). This type of control scheme is well established for control l ing gate length in logic devices in high-volume manufacturing.[3] In this study, a ful ly integrated run-to-run (R2R) control system was used to provide nanome-ter-level control of gate CD,[4] show-ing that this technology can be readily adopted for SADP CD control. Our APC cont rol ler i s integ rated on the process system, which inter faces with the IM, fab host and endpoint systems to provide f lexibil ity for various APC control schemes.

To improve CD control with an IM system, two criter ia must be satisf ied. First, the post-etch CD must be related to a recipe-controllable process parame-ter. For core APF CD control, this pro-cess parameter is the BARC trim time. The BARC tr im is t ypica l ly appl ied a f ter BARC open and before n it r ide hardmask etch to br ing the core APF CD to design target. The longer the BARC tr im step, the smal ler the core APF CD. The relationship between the tr im t ime and the amount of the CD

trim needed is cal led the trim curve. It is determined by measuring the wafer before and af ter etch for a var iety of t r im t imes. The t r im amount i s the difference between these two measure-ments and is a function of the trim time. Such trim process control has been well established for gate CD control in logic devices. Because of the learning from gate etch, the etch chamber and etch process are now ready to provide stable CD control for SADP.

Second , the core APF CD cont rol should not affect the f inal l ine CD and

its uniformity. This criterion is satis-f ied for our SADP scheme since the line CD and its uniformity is mainly deter-mined by the spacer deposition, while the core APF etch determines the space between adjacent l ines. This has a lso been proven by process results, where a 12 second trim time dif ference led to a core APF CD difference of ~8nm with no difference in the f inal line CD, uni-formity and roughness.

A f lowchart of the proposed core APF CD control method is shown in Figure 3. FF control takes place by making a set

Figure 2. Ilustration of spacer mask patterning overlay error (overlay error = core space - gap space).

CoreSpace

GapSpace

Target CD

Calculate Trim Time

Recipe

Process ModuleLitho CDIMCore APF CD

IM

TrimCurve

WTW

FF

WTW

FB

Wafer Movement

Data Flow

Figure 3. WTW APC process flow.



of CD measurements across the wafer using IM before the wafer is sent to the process module. The mean CD on that wafer is then calculated. The amount of tr im needed is then computed based on the mean pre-etch CD on that wafer, target CD, the trim curve, the current feedback of f set , and any add it iona l offset needed. The recipe settings for

that wafer are then changed based on this newly calculated trim time. After the wafer is etched, it is sent to the IM module for post-etch CD measurement. The measurement is performed at a set of sites across the wafer and the mean CD is computed. The feedback offset is calculated from the difference between the measured and expected CD values,

and then further adjusted by using an exponentially weighted moving average (EWMA) f i lter. The feedback offset is then applied to the FF calculation for the next wafer.

SADP APC DemonstrationTo test the funct iona l it y of the etch system and demonstrate the benef it of applying WTW APC to core APF etch, an APC demonstration was carried out on Applied’s 32nm SADP wafers by using the AdvantEdge G5 chamber.

OCD Modeling The f irst step in implementing IM for core APF CD cont rol was to create scatterometry models and libraries that provide precise CD measurement on pre- and post-etch wafers. An optimized OCD model represents the expected var iat ion seen in normal product ion while minimizing the contr ibution of insensitive parameters to critical output such as CD and sidewal l ang le. The OCD metrology tool on the etch sys-tem used in this demo was the NOVA 3090. The OCD models and l ibraries were created off line on a NOVA MARS station. Figure 4 shows the l itho and post-core APF etch f ilm structures used in the OCD models, with the measured parameters.

The libraries created from both models were va l idated by compar ing the CD va lues repor ted by OCD with those repor ted by CD-SEM a s shown in Figures 5(a) and 5(b). There are strong correlations between results from these two dif ferent CD measurement tech-nologies over a wide range of CD varia-tion, which validates the OCD models and libraries. Once instal led on the IM module the libraries were available for WTW APC.

Trim Curve Characterization Once the OCD l ibr a r ie s were c re-ated and va l idated, the next step was to character ize the tr im curve, which

Width (nm)

Heig

ht (n

m)

630

60 120 180

PR CD

PR Height

Nitride Thickness

Core APFThickness

240 300 360 420 480 540

560

490

420

350

280

210

140

70

0

400

40 80 120 160 200 240 280 320 360 400

Top CDSidewallAngle

Core APF Height

Bottom APFThickness

350

300

250

200

150

100

50

0

Width (nm)

Heig

ht (n

m)

Figure 4. OCD model of the SADP film stacks (top) before patterning and (bottom) after core APF etch.



represent s the rel at ionsh ip between trim amount and trim time. Six wafers were etched, with the trim time vary-ing from 3 to 12 seconds. Each wafer was measured before and after core APF etch in the IM module. The dif ference between these two measurements was calculated and plotted against the trim time applied (Figure 6). The relation-ship between the trim amount and trim time was very well described by a lin-ear function. Based on this l inear tr im

curve, the FF ca lcu lat ion dur ing the APC test was such that

CDfeedback is given by:

where l= 0.4 , CDo f f s e t = 8.44n m, CDtarget =38.0nm, trim rate =0.78nm/s. CDoffset accounts for the sum of CD bias

induced from all other etch steps except BARC trim.

IM Data Collection Plan The impact of IM on wafer through-put is always a concern in WTW APC. The goal of the IM data collection plan was to minimize the IM measurement time while stil l measuring enough sites on the wafer to have true mean CD. In order to achieve this goal, a total of 92 dies were measured on the whole wafer. Then 17 dies were selected as shown in Figure 7, which yielded very simi lar mean CD and standard deviation as that of all 92 dies. These 17 dies were later measured on every wafer before and after etch in the IM module during the APC demonstration to provide input for FF and FB control.

Design of the APC Test Unl ike the situat ion in a product ion fab where large wafer populations are available for monitoring and testing of an APC scheme, the number of SADP wafer s ava i l able for th i s s tudy were l imited. Therefore, the APC test was designed to demonstrate WTW APC behavior under var ious expected pro-duction variations with only 22 SADP demonstration wafers.

In order to simulate lot-to-lot lithogra-phy CD variation and demonstrate the benef it of FF control, the 22 SADP dem-onstration wafers were patterned with different target CDs. The f inal litho CD variation in this group of wafers had a range of 6.2nm with a standard deviation of 1.49nm.

These 22 demonstrat ion wafers were split into three groups during the APC demo. Five wafers were etched with no APC appl ied , i .e. they were a l l etched using exact ly the same cham-ber and baseline recipes. The post-etch CD va lues of th is g roup would pro-vide a comparison for the WTW APC scheme. The second g roup had ten

Figure 5 (a). CD-SEM measurements vs. OCD measurements on litho CD.

Figure 5 (b). CD-SEM measurements vs. OCD measurements on core APF CD.

60

58

56

54

52

50

4848 50 52 54 56 58 60

CD-S

EM (n

m)

OCD (nm)

y = 1.1066x - 6.9242

R2 = 0.9705

50

49

48

47

46

45

44

43

42

41

4032 34 36 38 40 42

CD-S

EM (n

m)

OCD (nm)

y = 0.9521x + 9.9881R2 = 0.9562



wafers, etched with FF and FB closed loop control from WTW. The baseline process recipe was used with only the t r im t ime adjusted by the APC con-trol ler. Results from this group were used to demonstrate the benef it of FF control with minor process excursions. There were seven wafers in the third group. The O2 f low rate in the t r im step for this group was increased from 12sccm in the baseline recipe to 15sccm to simulate an unexpected disturbance in the process chamber. The O2 f low

increase could ef fectively increase the trim rate and result in smaller CDs on the wafer i f lef t uncorrected. Results f rom th i s g roup wou ld be u sed to demonstrate the benef it of WTW FB control.

SADP APC Demonstration Results The post-etch core APF CD va lues mea su red on a l l 22 demon s t r a t ion wafers are shown in Figure 8. Group one has the highest CD var iat ion, as expected. This indicates the ef fect of

litho CD variation on the post-etch CD if no process control is applied.

Although group two has similar l itho CD variation as that of group one, the post-etch core APF CD is wel l kept within the +/-1nm control band. This is because of the FF control applied to this group of wafers that effectively cor-rected the CD variation in the incom-ing wafers. The benef it of FB control is minimal for this group of wafers, as shown by the dif ference between the CD values in green (simulated results assuming no FB applied) and real CD values in pink. This was expected since the benef it of FB control is its capability to detect process excursions and make corrections. When the process is at a stable state, there is not much FB cor-rection needed.

The FB benef it is clearly demonstrat-ed by the CD va lues in g roup three. Only the f irst wafer in the group has a post-etch CD outside the control band. I f the FB control was not appl ied to th is g roup of wafer s, their post-etch core APF CD would have been ~1nm smaller than the design target as shown by the CD values in green in Figure 8. The abi l ity of tool level FB control to immediately detect and correct a pro-cess excursion and reduce the number of wafers at r isk is clearly demonstrated by these results.

Over a l l , t he W T W FF+F B c lo sed loop APC control was able to del iver a post-etch core APF CD wel l within the (design target +/-1nm) control band with a 3σ va lue of 1.7nm despite the wide incoming CD var iat ion (range: 6.2nm, 1σ : 1.49nm) and O2 f low dis-turbance in the etch process.

ConclusionThe WTW closed loop APC has been succes s fu l ly appl ied to 32nm SADP wafers to provide tight control of core APF CD and thus min imize overlay

Figure 7. The IM data collection plan for the SADP APC demo. Each die contains multiple 100x100μm 2-D gratings for OCD measurements (red circles).

0

-4

-8

-12

-16

-200 2 4 6 8 10 12 14

CD B

ias

(nm

)

Trim Time (s)

y = -7.7928x - 8.4406R2 = 0.9819

Wafer Map Die Map

Figure 6. The core APF etch trim curve shows a linear relationship between trim time and change in CD (CD bias).



error from DP schemes. Although the APC test conducted is relatively simple compared with similar APC tests in a product ion env ironment, the resu lt s clearly prove the functionality of OCD metrology as a solut ion for tool level APC and demonstrate the benef it of WTW APC control in an SADP pro-cess f low.

AcknowledgementsThe author s a r e e spec i a l l y g r a t e -fu l to Huix iong Dai of the Maydan Technolog y Center for per form ing l ithography on the SADP APC demo wafers to generate litho CD variation as designed. The authors would also like to thank Applied’s Yongmei Chen, Jessie Blanquet, Ming Xu, Opher Harel, and

Verlyn Fischer for their special contri-butions. ■

References [1] C.Bencher,“SADP:TheBestOptionfor32nm

NANDFlash”,NanochipTechnologyJournal,

IssueTwo,2007.

[2]“SADPmostcost-effectivefor32nmnode–

AppliedMaterials,”ElectronicsWeekly,March

11,2008.

[3]M.Sendelbach,etal,“Integratedscatterometry

inhigh-volumemanufacturingforpolysilicon

gateetchcontrol”,Proc.ofSPIEVol.6152,

61520F,2006.

[4]D.Muietal,“In-toolprocesscontrolfor

advancedpatterningbasedonintegrated

metrology”,Proc.ofSPIEVol.5378,2004.

Applied Centura® AdvantEdge™

G3 Silicon Etch

Process System Used in Study

• Exact CD control and CD uniformity to within 2mm of the wafer’s edge

• Run-to-run control with closed-loop feedback from optional integrated OCD metrology

• In situ resist trimming capability

Lei Lianisamemberofthetechnicalstaff

inAppliedMaterials’SiliconEtchDivision.

She iscurrentlyworkingonetchprocess

endpoint control, advancedprocess con-

trol for SADP, andplasma statemonitor-

ingandprocess chambermatching. She

has a Ph.D. in theoretical and applied

mechanics from theUniversityof Illinois

atUrbana-Champaign.

Jaklyn Jin isamemberofthetechnical

staff in Applied’s Silicon Etch Division.

She has a B.S. in materials science

from the Univers i ty of Sc ience and

TechnologyofChina.

Corne l Bozdog has he ld d i f ferent

ro les as appl icat ions sc ient ist and

applications group manager at Nova

Measuring Instruments. He is the 2007

recipient of the “Nova Expert” fellow-

sh ip and i s cur rent ly the product

manager of the NovaMARS sof tware

for scatterometry appl icat ions. He

receivedhisPh.D. insolidstatephysics

from Lehigh University and his B.S. in

physics from University of Bucharest,

Romania.

Article Contact: [email protected]

45

44

43

42

41

40

39

38

37

36

351 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Post

-etc

h CD

(nm

)

Wafer Number

Group 2 FF and FBGroup 3 FF, FB

with Process ExcursionGroup 1 Baseline

Lith

o CD

(nm

)

57

58

56

55

54

53

52

51

50

49

48

Post-etch CDPost-etch CD with no FB

Target CDLitho CD

Authors

Figure 8. The SADP APC demonstration results for the three wafer groups showed improve-ment in CD control from the application of WTW APC.


Photomask Cleaning for 45nm and Beyond

Photomask C l ean ing

As the semiconductor industry moves to 45nm and beyond, the cleaning of advanced photomasks becomes much more challenging, requiring new technology solutions. The major challenges are particulate cleaning on blank masks, damage-free cleaning for post-etch and post-repair applica-tions, preserving film integrity, and sulfur-free cleaning to reduce haze growth. New photomask cleaning technologies have been developed to meet these demanding cleaning requirements.

Keywords: Photomask, Mask Cleaning, NanoDroplet Technology (NDT), Haze

The photomask manufacturing process is shown in Figure 1. Although this f low is less complex than a wafer f low, the defect requirements are much more stringent. On a wafer, a defect affects only a single die, whereas mask defects get printed on every die. Thus, a mask cleaning system must provide defect-free performance without altering optical properties or damaging the sensitive structures. Applied Materials developed the Tetra Reticle Clean system to meet the above challenges. In this paper, the technologies that enable phototresist strip and damage- free cleaning in the new clean system are presented.

Clean System DesignThe new clean system integrates dry and wet process chambers. The dry chamber is based on a remote plasma source and is used for photoresist strip and surface pre-treatment applications. The wet process-ing chamber is equipped with advanced damage-f ree clean ing technolog ie s including proprietary Uniform Cavitation Megasonics (UCM) and NanoDroplet Technology (NDT).

Damage-Free CleaningA viable cleaning technology has to remove defects without damaging the

Mask Blank

Order Information

Reticle layout

and data fracture

Resist Coat Pattern Generation Resist Develop Etch

Metrology Strip and CleanCleanDefect InspectionRepair

Final Inspection To Wafer FabApply PellicleCleanDefect Inspection

Figure 1. Typical phase shift mask process flow. Each mask is cleaned several times during manufacturing.


sensitive mask features. Table 1 shows the technology node and the corresponding sub-resolution assist feature (SRAF) sizes according to the 2007 ITRS. The SRAF size is very small for advanced technology nodes and it is critical to remove contami-nants without damaging these features during mask cleaning.

Megasonics is commonly used for parti-cle removal. Historically, “f inger-based” megasonics, where acoust ic energy is applied to the stream of a cleaning f luid at the delivery nozzle, is known to cause

localized SRAF damage. UCM technol-ogy has been demonstrated to have a large damage-free cleaning window and is in use for 45nm production. With UCM, the energy is transmitted uniformly from the back side of the mask to the front side of the mask where the critical features are located. By transmitting the energy from the back, the mask itself acts as an attenu-ator, thus reducing the delivered energy level to the top side of the mask. Besides energy control, this approach cleans both sides of the mask simultaneously, reduc-ing the total process time for improved throughput.

While UCM can be used for 45nm, a new mixed f luid jet nozzle technology called NanoDroplet was developed to further reduce the potential for SRAF damage without compromising particle removal

eff iciency (PRE) for 32nm and beyond. NDT is a momentum-based cleaning technique that delivers microscopic liquid droplets to the mask surface. As described by Haller et al. in their fundamental study of droplet impact onto a substrate, the impinging droplets create a pressure front at the impact zone resulting in a radial or lateral jetting f low of liquid.[2] The lateral liquid f low induces a drag force, FD, on particles, enabling their removal from the mask when this drag force exceeds the van der Waals interaction force, FvdW, between the particle and the substrate (Figure 2). For 65nm particles, FD is estimated to be an order of magnitude higher than FvdW with appropriate NDT parameters.

Prudent design of the mixed f luid jet nozzle is critical to obtain desired droplet characteristics for damage-free cleaning. One of the major limitations of conven-tional nozzles is that their droplet velocity/size distribution has a relatively signif icant tail of large diameter droplets (Figure 3). The kinetic energy of a droplet, Ek is pro-portional to the cube of its diameter, d, per the following equation:

where ρ is the f luid density and v is veloc-ity. These large diameter droplets result in a corresponding high energy tail in the droplet kinetic energy distribution, and

■ Advanced Photomask Cleaning

Table 1. Assist feature size and defect size for 65nm and below technology nodes.[1]

2007

65

85

52

2008

57

76

45

2010

45

60

36

2013

32

42

26

2016

22

30

18

Production Year

Technology Node (nm)

Sub-resolution Feature Size (nm)

Defect Size (nm)

Manufacturable solutions exist, and are being optimized

Manufacturable solutions are known

Manufacturable solutions are NOT known

Figure 2. NDT mechanism showing the drag and van der Waals forces exerted on a defect during cleaning.

NanodropletTechnology

Conventional Nozzle

Velo

city

(au)

Droplet Diameter (au)

Substrate

FVdW

FD

Vf

Defect

Figure 3. Conventional nozzles create damage-inducing large diameter outliers (circled area). NDT generates droplets with uniform small size distribution to enable damage-free cleaning.


can induce damage to sensitive mask fea-tures and erode the inside of the nozzle. Consequently, a new nozzle design was developed to eliminate the large drop-let size/high energy tail. Phase Doppler analysis was used as a diagnostic tool to characterize the nozzle droplet size and velocity distributions and to help guide the design optimization.[3]

Particle Removal EfficiencyPRE is the standard metric used to evalu-ate cleaning capability, and is def ined as the percentage of particles cleaned rela-tive to the original particle count.[4] To conduct PRE testing, unpatterned blank masks are “contaminated” with several thousand particles using a wet deposi-tion method. The blanks are comprised

of industry-standard f i lm stacks (e.g., NTAR7 binary masks and TF11 phase shift masks). Particle counts are measured before deposition, after deposition, and after cleaning using a Lasertec 2351 par-ticle counting system. This PRE testing simulates removal of actual particles that contaminate the mask during the fabri-cation process. Polystyrene latex spheres (PSL) and si l icon nitr ide (Si3N4) par-ticles are used to simulate organic and inorganic particles, respectively. Figure 4 shows the PRE performance obtained on un-patterned NTAR7 photomask blanks for Si3N4 particles. Similar PRE of >99% is achieved with PSL on NTAR7 blanks (Figure 5). Additional data on TF11 blanks, the most common phase shift mask type for 45/32nm applications, showed similar results.

Figure 6 shows data on the performance of NDT compared to conventional meth-ods. The particle measurement system sizes and classif ies particles in pixels. The correlation between pixel-sized binning and par t icle diameter var ies between metrology tools, but smaller pixel sizes correspond to smaller particle diameters. NDT-based cleaning shows superior per-formance across all bins compared to con-ventional PTOR clean.

As mentioned previously, the high PRE must be achieved without feature damage. Repeatable damage-free cleaning has been demonstrated using NDT on damage test masks for sub-50nm Cr/MoSi lines (32nm technology node) as shown in Figure 7. The same process was run on a set of PRE masks deposited with Si3N4 particles. The PRE was repeatable > 98% (Figure 7), demonstrating a robust window for dam-age-free cleaning with high PRE.

Photoresist RemovalPhotore s i s t s t r ipping i s per for med af ter mask etching steps and a l so for rework dur ing patterning. The over-a l l st r ip+clean process must remove photoresist and post-etch residues, and


Figure 4. Representative PRE performance (>99.9%) for >80nm Si3N4 particles with NDT cleaning shown by defect maps for a mask (left) before deposition, (center) after Si3N4 particle deposition, and (right) after NDT cleaning.

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Figure 5. Representative PRE performance (>99%) for >80nm PSL particles on NTAR7 masks with NDT cleaning as shown by defect maps for a mask (left) before deposition, (center) after Si3N4 particle deposition, and (right) after NDT cleaning.


leave the mask free of particle defects. In addition to the bulk photoresist layer, all photoresist on the vertical and hori-zontal edges of the mask must a lso be completely removed. Typically the edge photoresist is thicker and takes consider-ably longer to str ip than the bulk. For masks with negative photoresist or with posit ive photoresist plus an edge bead removal step after coating, the edge resist is less of a concern. However, there is still a bump of thicker resist at the outer perimeter of the bulk resist region.

Conventional photoresist stripping uses a sulfuric acid/hydrogen peroxide mix-ture (SPM) for both bulk and edge resist. In some cases, sulfuric ozone chemistry (SOM) has been used in which sulfuric acid and ozone is mixed instead of hydrogen peroxide.[5] Although fast and effective at removing organic photoresist, sulfuric acid-based chemistries leave chemical residuals on the surface of the mask that can lead to the formation of haze. Strategies have been implemented to minimize the residue, such as hot water rinsing, UV light, or thermal treatments,[5] but these have proven only partially effective. The complete removal of sulfuric acid from the process f low is desir-able for not only mask cleaning purposes but also for environmental reasons.

The Tetra Clean system enables the strip+clean process to be accomplished with either a dry/wet or an all-wet pro-cess, both of which are sulfur-free. For the dry/wet approach, stripping is performed in the dry remote plasma chamber. This chamber is equipped with multiple gases for str ipping dif ferent types of resists with high selectivity to underlying f ilms. For wet stripping, photoresist is removed in the wet chamber using an ozonated water (DIWO3) process. A f inal clean in the wet chamber is performed after dry stripping, or incorporated into the end of the all-wet process sequence.

Overall, the dry/wet approach is favored for str ip+clean appl icat ions. In addi-

tion to providing ~ 30% faster photore-sist strip rates, using remote plasma for stripping signif icantly reduces DIWO3 exposure time and potential feature ero-sion issues. An added benef it of dry pro-cess capability is for surface pretreatment in the cleaning of blank masks. Blanks typica l ly have an organic residue due to outgassing from shipping and storage containers, and high quality cleaning is dif f icult unless this organic residue is removed initial ly. A short plasma pre-treatment has proven to be very effective for removing these organic residues, and also offers higher productivity relative to conventional approaches such as UV treatment.

Representat ive part icle data after dry str ipping+wet cleaning are shown in Figure 8. The f ina l par t icle count is approximately twenty, and most of these defects are concentrated in the smaller particle size bins. Additional f inal clean-ing does not substantially reduce the par-ticles further, indicating that the dry/wet process performs resist removal and f inal particle cleaning as intended.

Haze ControlManaging haze is one of the most critical issues in the lithography process. There are three main causes of haze as described below.

• Sulfateionresiduesonthemasksur-


Conventional cleanNDT-based clean

10

10

203040

50

6070

80

90100

3 5 7 10 12 16 20 40 41

PRE

(%)

Pixel Bin

Figure 6. Bin by bin PRE performance on Si3N4 particles for NDT and conventional clean-ing processes.

Figure 7. Repeatability results using two sets of blank and sub-50nm line/space patterned masks (inset) subjected to the same NDT cleaning recipe. The average PRE was 99% with zero damage.

PRE

% (>

80nm

)

Mask Number

Num

ber o

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aged

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ture

s on


face combine with ammonium ions in the presence of high energy light during stepper exposure (particularly ArF 193nm) to form ammonium sul-fate crystals. These are the most com-monly reported as progressive haze defects.

• Thebreakdownoforganic-containingpellicle gasket and adhesive materials also occurs during repeated exposure of the mask in the stepper. This results in outgassing of organics and subsequent reaction with moisture and ammonia on the mask active area to form haze.[6]

• Themaskstorageenvironmentaffectsthe residual mask contaminant level, even without photon exposure, and could cause haze issues.

The best solut ion to prevent and/or reduce haze problems is to avoid using sulfur-based chemistries such as sulfuric peroxide mixture (SPM) in mask clean-ing. The Tetra Clean uses ozone-based chemistr y for improved haze per for-mance. Figure 9 shows the sulfate and ammonium ion levels as measured by ion chromatography for conventional and Tetra Clean processes. It can be noted that the Tetra Clean process shows sig-ni f icant ly lower residua l ions lef t on the sur face of the mask compared to

conventional SPM processes. Figure 9 also shows haze threshold energy on the secondary y-axis for both conventional and Tetra Clean processes. These data were generated using a haze accelera-tion test bench where the cleaned mask is exposed to high laser energy to pro-mote haze g rowth in a shor t per iod of time. It is shown that the threshold energy for haze growth is much higher for masks processed with Tetra Clean

process using ozone-based chemistr y compared to SPM based cleaning chem-istry. Higher threshold energy results in increased mask lifetime in the wafer fab and reduced number of recleans.

Film IntegrityPreserving the f ilm integrity is a criti-ca l measure of a good cleaning pro-cess. Film integrity can be evaluated by measuring phase loss and transmittance change for attenuated phase shift pho-tomasks (APSM) and ref lect iv ity for binary masks (BM). For APSM masks the at tenuator layer induces a phase shift to enhance patterning resolution. Precise control of phase (change in opti-cal path length between two regions on the mask expressed in degrees) is essential for accurate patterning of small features. The mean value of phase is determined by averaging measurements for many features on the mask. Figure 10 shows the phase loss and transmittance change per clean for conventional and Tetra processes. As shown, the Tetra Clean ozone-based pro-cess is signif icantly better in preserving f ilm integrity than SPM chemistry.

Future Cleaning ChallengesThe next generation of masks wil l be more sensitive to damage due to smaller features and have even tighter defectivity


Figure 8. Post strip+clean particle map for FEP photoresist stripped from TF11 photomask.

Figure 10. Comparison of the phase and transmittance change per clean on APSM masks for conventional vs. Tetra Clean processes.

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Cleaning Processes

On-mask Surface Ions (au)Threshold Energy (au)

Figure 9. Residual surface ions and haze threshold energy for conventional and Tetra Clean processes.

Phase Loss(Degrees/Clean)

Transmittance(%/clean)

requirements than current technologies. Therefore, control l ing contamination with effective cleaning technology will be critical. Extreme ultraviolet (EUV) l ithography is being considered as an alternative to current optical patterning methods and will be a signif icant depar-ture from the DUV lithography masks used today. The EUV masks will be com-posed of multilayer stacks of new materi-als which will bring new challenges in maintaining optical and topographical integr ity including dif ferent types of post-etch residues and material selectivity to cleaning chemistries. The Tetra Clean system is designed for extendibility and work is on-going to develop next genera-tion NDT and megasonics technologies.

ConclusionTetra Clean technology meets the strin-gent cleaning requirements for advanced

photomask cleaning for 45nm and below processing. The use of integrated dry and wet processing sequences enables fast pho-toresist stripping without the use of haze-promoting sulfuric-acid based chemistries thus extending mask lifetime. UCM has shown damage free cleaning while achiev-ing >99% PRE for 45nm technology node masks. A new mixed-jet f luid technology (NDT) has been developed and damage free cleaning was demonstrated for 32nm processing using masks with sub-50nm SRAFs and 32nm line and space features on nano-imprint masks. ■

References [1] Lithography – Optical mask requirements, avail-

able at http://www.itrs.net, ITRS 2007.

[2] Haller K.K. et al., “Computational study of high-speed liquid droplet impact”, J. Applied Physics, 92(5), 2821-2828, 2002.

[3] Bachalo W.D. et al., “Phase/Doppler spray ana-lyzer for simultaneous measurements of drop size and velocity distributions,” Opt. Eng. 23(5), pp. 583–590, 1984.

[4] Gouk, G. et al., “Advanced damage-free photo-mask cleaning for 45/32nm technology nodes” Photomask and Next Generation Lithography Mask technology XV, Proc. SPIE 7028, 702808-4, 2008.

[5] Kindt, Let al., “Sulfur-Free Cleaning Strategy for Advanced Mask Manufacturing”, Photomask Technology 2006, P.M. Martin and R.J. Naber, eds., Proc. SPIE 6349, 63491J, 2006.

[6] Kalk F. et al., “Photomask defectivity and clean-ing: A new Milieu,” Semiconductor International, (Sept-2007).

Applied Tetra™ Reticle Clean

Process System Used in Study

• Delivers damage-free cleaning with 99% particle removal efficiency for 32nm and beyond

• Dry/wet technology offers maximum flexibility for applications including strip, post-etch clean, and final clean for all mask types

• Highest productivity due to simultaneous front/back cleaning, short process times, and 2-step mask processing

Evans Baiya is a global product manager for photomask cleans in Applied’s Etch and Cleans Unit. He is responsible for product strategy development, product marketing, and project management of all photomask cleaning activities. He has an MBA from Northwest Nazarene University.

Jim Papanu is a senior technology manager for photomask cleans in Applied’s Etch and Cleans unit. He has B.S. and M.S. degrees from Case Western Reserve University, and a Ph.D. from University of California, Berkeley, all in chemical engineering.

Ro m a n G o u k i s a m e m b e r o f t h e techn ica l s ta f f w i th App l ied ’s Etch and Cleans unit , working on process deve lopment for photomask c lean -i n g a p p l i c a t i o n s . H e re c e i v e d h i s B.S. and M.S. degrees in mechanical eng ineer ing f rom the Un ivers i ty of Minnesota.

Jason Jeon is a process engineer in Applied’s Etch and Cleans unit, focusing on process development metrology/inspection for mask clean applications. He received his Ph.D. in solid state physics from Moscow State University.

Tong Liu is a process engineer in Applied’s Etch and Cleans unit. She is responsible for process and technology development, customer demos and on-site support. Tong has a Ph.D from Rensselaer Polytechnic Institute, and M.S. and B.E. degrees from Tsinghua University, China, all in materials science and engineering.

Rao Yalamanchil i is the director of Applied’s Photomask Cleans group. He received his masters degree from the Indian Institute of Technology, Bombay, and a Ph.D. from the University of Utah, both in metallurgical engineering.

Brad Eaton is the global product market-ing manager in Applied’s Etch and Cleans unit. His responsibilities include managing global product marketing activities across etch and cleans for mask products. He has an MBA from Santa Clara University.

Ajay Kumar is the general manager of Applied’s Mask Etch and Cleans group. He received his Ph.D. in applied physics from the Indian Institute of Technology.

Article Contact: [email protected]

Authors




New Techno logy

Why is the industry adopting TSV, and what are the markets and applications driving this technique?Sesh Ramaswami: Let me start off by providing a context for TSV development. TSV is an evolution of 3-D packaging, com-bining the best aspects of system-on-chip (SOC), where different functional blocks are fabricated on the same substrate, and system-in-package (SIP) schemes. In TSV wafers or the chips are stacked on top of each other, and are connected using vertical pathways of interconnects (instead of wires) that run completely through the chips. The chips can be of the same type or of different types, referred to as homogenous or heterogeneous integration, respec-tively. For end-product companies, this approach opens up the supply chain and lowers their cost by enabling them to procure different components from various suppliers − and scale them at different rates, hence different costs curves – and integrate them using TSV.

In homogenous integration, there might be four or eight DRAM chips, for example, stacked up with tens of copper interconnect vias

running through them. This results in one chip with the memory equivalent of eight individual chips in a smaller form factor. Using these DRAM chips in a server would consume less board space and also reduce the latency and improve the bandwidth between the microprocessors and the DRAM.

For communications devices like Blackberries and iPhones, wire bonding is used today to connect chips of various types. These chips are mounted on multi-layer substrates. By using copper to intercon-nect devices in 3-D with several thousand vias interconnecting them, one can get more functionality from the same real estate.

An established application for TSVs is in CMOS image sensors, where manufacturers have already implemented TSVs at 200mm and will be migrating to 300mm starting next year. Although the technical requirements here are less challenging, cost is a major issue. In a nutshell. we expect significant growth in the design-in of TSV in communication and DRAM chips in 2009 and 2010 with significant growth to begin around 2011.

Through-SiliconViaTechnologieS— ChallengesandSolutions

SPECIAL FOCUS : TSV


TSV i s emerg ing as a c r i t i ca l techn ique

f o r s c a l i n g , p a c ka g i n g a n d c o n t i n u i n g

the d r i ve to h i ghe r dens i ty and h i ghe r

pe r fo rmance ICs . We assemb led a pane l

o f A p p l i e d ’s l e a d i n g t e c h n o l o g i s t s i n

t h i s f i e l d t o d i s c u s s t h e c h a l l e n g e s

and so lu t i ons needed to imp l ement and

acce lerate new TSV integrat ion schemes.

Panelists include Sesh Ramaswami, Brad Eaton, John Dukovic, Nitin Khurana, Sherry Xia, Balaji Chandrasekaran, and Kedar Sapre.


■ TSV Etch Technology

What are some of the key challenges for TSV applica-tions?Sesh Ramaswami: Challenges associated with EDA tools and mod-els, device reliability, cost-effective unit processes and process integra-tion on thinned wafers need to be solved to enable the adoption of TSV technology into high volume devices. We are mitigating process risks for customers by integrating proven materials, films and equip-ment into the TSV scheme. Key unit processes are etch, dielectric oxide liners, PVD barrier/seed, low temperature oxide/nitride films, plating and CMP.

There are two main choices for TSV processing. Chipmakers that choose to introduce TSV at the FEOL use the via-first scheme that requires the most changes to interconnect circuit layout. A simpler way to introduce TSV is at the back end of line – via-last. In the via-last approach, the vias are formed after BEOL or bonding, on a full thickness wafer from the front-side or from the backside on a thinned wafer. Also, the via size and aspect ratio are important to understand since they drive the integration schemes.

CMOS image sensors have via sizes >40 um with>2:1 aspect ratio. For other devices, the vias range from 3-20μm, with wafer thickness (which determines aspect ratio) ranging from 30-125μm.

Device wafers are typically bonded to carriers (glass or dummy silicon) prior to thinning down to the 30-125μm range. Bonding, grinding, wafer processing on bonded/thinned wafers and subsequent de-bond-ing are hence very important steps in the wafer f low. Once bonded,

processing temperatures cannot exceed 200°C. Since significant ‘value’ is added by the business entity that processes these wafers, we see a ‘value tussle’ between foundries and packaging houses, which in turn drives integration requirements. One can well imagine that a packag-ing house does not want to be tagged with breaking valuable thinned wafers coming to them from a wafer fab.

John Dukovic: There are various dimensions to TSV technology that will have to come together before it can go into mainstream vol-ume production. While CMOS image sensors have led the way in unit volume, they do not constitute high volume in terms of new 300mm wafer starts. The volumes are expected to be large for stack-ing memory chips and for joining logic and memory chips together to achieve faster bandwidth and lower latency. You could combine two chips using conventional wire bonds, but the inductive losses will make the data exchange too slow. These types of TSV applications present new design challenges, especially if a logic chip is married to a memory chip. Designers will have to work off of the same plan and line up the connection points between the two chips. There is also the thermal question: will this chip now be too hot and is there a good way to release the heat? Finally, we also need new automatic test capability compatible with 3-D integration.

What is the cost factor for TSV? Sesh Ramaswami: For TSV to be adopted in high volume, cost is an over-riding factor. For example, there are early indications that a 30% cost increase relative to wire-bond can be tolerated since TSV enables a much higher return in value at the system level. However, this needs to be watched carefully, since the economics on the value side may change rapidly. A couple of years ago, the TSV process added

Through-SiliconViaTechnologieS— ChallengesandSolutions

■ TSV Challenges and Solutions

SESH RAMASWAMI is senior director of Strategy and Marketing in Applied’s Silicon Systems Group.

JOHN DUKOVIC is a distinguished member of technical staff in the Silicon Systems Group.



about $300 or $400 per wafer. There are roadmaps to get it to the sub-$150 range. The biggest contributors to cost are bonding/de-bonding and copper fill. Applied’s joint work with suppliers in these areas will help reduce cost.

What processing tools will be required for TSV? John Dukovic: Certain new process systems will be needed depending on how the TSV technology is implemented. One area that will change is the formation of via holes, which was origi-nally done with laser ablation. As the number of vias grows and the damage-free requirements increase, this method will soon be unworkable. Instead, the vias will be formed using deep reactive ion etch technology.

After the hole is etched, if the via was immediately lined and filled with metal, it would be shorted to the body of the silicon. So the hole must first be lined with an insulating layer of oxide. Assuming copper is the metal for the via, a second liner that is a barrier to copper diffusion is also needed. Alternatives to copper have been explored. Tungsten is a possibility, especially for the via-first f lows, and polysilicon has also been tried. Copper is likely to prevail in mainstream applications for reasons of conductivity and cost.

Suitable barrier materials for copper TSVs are the same as those deposited for advanced logic devices: titanium or tantalum. Deposition uniformity is critical since very-high-aspect-ratio struc-tures are historically tricky for PVD. However, we’ve had some excellent results with extensions of our PVD technology and we are encouraged by the possibilities there.

Filling the via with copper will almost certainly be done by electro-plating. We are partnering with Semitool on plating, and conducting integrated process-sequence development together to co-optimize the etch, dielectric liner, barrier/seed and plating steps..

An additional step in the sequence, in some applications, is CMP. Currently, three process schemes using CMP in TSV devices have been identified. They are pre-transistor via , post-transistor via first and post-transistor via last schemes. The former scheme requires an oxide CMP processing step while the latter post-transistor schemes can use copper CMP for both via-first and via-last approaches

It’s notable that all processes performed after the wafer has been bonded to a carrier and thinned must be below 200°C. These include PVD and dielectric CVD oxide and nitride films, stress-relief Si CMP and copper CMP.

What progress has Applied made with technologies for TSV? Brad Eaton: On the wafer, the smallest CDs for via-first schemes tend to be 5-10μm. Via-last CDs are 25-100μm, typically with 5:1 to 10:1 aspect ratios. We have a lot of experience with these types of materials and aspect ratios and we have a long history of deep silicon etch, from very high aspect ratios. Our HART system is used for etching trench capacitors with aspect ratios as high as 80:1. Also, we have a 200mm DPS system running TSV in production for CMOS image sensors.

The biggest challenge is to etch very, very fast and maintain a low cost of ownership. Etch profile is another technical challenge. With the traditional Bosch process approach that consists of rapidly alternating etch and deposition steps, there is a significant trade-off between the quality of the profile and the etch rate. You can etch very quickly but have poor quality profiles or you can etch very slowly and have excellent profiles.

We have found a way to the profile requirements with etch rate to get the smoothest sidewall to ensure that subsequent deposition steps are of high quality and have good electrical characteristics. To achieve this, we have modified a proprietary process in our new Silvia etch system. This will have a substantial impact on cost of ownership and provides the fastest silicon etch rate on the market.

There is another method that others are pursuing, utilizing a steady-state process. It’s not a multi-step etch/dep process, but rather a sim-pler single-step deep etch. However, it has very poor tapers and undercut, so it’s generally not the favored approach where high aspect ratios and high selectivity to resist are required. The approach has proven sufficient for low via density and low aspect ratio applications such as CMOS image sensors. However, the high plasma density of Silvia’s ICP reactor makes it ideal for both approaches.

BRAD EATON is global product manager of Applied’s Etch and Cleans Business Group.




Kedar Sapre: Our solution includes SA and PE CVD processes that are ideal for TSV dielectric liner applications. SACVD processes are highly conformal while PECVD processes are capable of deposit-ing films at very low temperatures. Conformality is critical for the subsequent titanium barrier and copper seed step coverage. SACVD processes use O3/TEOS chemistry at high pressure in a non-plasma environment which is beneficial for TSV trench profiles where a uni-form oxide film is desired along the sidewall. These processes have demonstrated 70-80% conformality in high aspect ratio TSVs. While plasma-based processes are ideal for via-last integration schemes where thermal budget considerations may be critical, current SACVD ther-mal oxides can be deposited at temperatures as low as 400°C with good breakdown voltage and leakage current properties. Both the SACVD and PECVD processes in conjunction with the Producer high-productivity platform, enable a low-cost-of-ownership solution for our customers. The Producer platform also supports up to three types of twin chambers for optimal f lexibility. So, in addition to liners mentioned above, low temperature (



the other companies that are trying to penetrate this market maybe with a tool here or a tool there (at


■ TSV Etch TechnologyNew Techno logy

Deep Silicon Etch for TSV Increases Performance and Productivity

Through-silicon via (TSV) is an emerging technology used in 3D packaging for integrating stacked ICs. Establishing a vertical electrical interconnect that passes completely through the die, the TSV approach can deliver increased device performance through shorter interconnect lengths and more compact form factors. This article examines the etch technology required for implementing TSV in via-first and via-last integration schemes.

Keywords: Etch, Through-Silicon Via, Deep Reactive Ion Etch

Consumer demand for smaller, lighter electronic devices with higher perfor-mance and more features is putting con-tinuous pressure on chipmakers to increase the functionality of ICs while reducing their cost and size in both footprint and thickness. This requirement has resulted in innovative, cost-effective 3-D packag-ing schemes.

The technology being adopted to form 3-D packages is TSV to link individual chips by employing vertical connections etched through a silicon wafer and f illed with metal to directly attach multiple dies. A basic f low involves the via etched through the silicon using a deep reactive ion etching (DRIE) process. This hole is then typically lined with a dielectric depos-ited by CVD. Then, much as with copper dual damascene processes, a diffusion bar-

rier and copper seed layer is deposited by physical vapor deposition (PVD), and the hole is filled by electroplated copper.

The formation of the metal-f illed holes is only part of the TSV process. The TSVs are opened at the wafer backside by aggressively thinning the silicon wafer to allow dies to be attached and electrically interconnected to a Cu/dielectric landing substrate. Thinning is done by grinding, chemical mechanical planarization (CMP) or by a wet chemical process.

Typically, the wafer is reduced in thick-ness by backgrinding after device fabrica-tion, TSV features need only be etched to the f inal die thickness. Currently, a f inal thickness of 50μm is typical, but this is

expected to be reduced to 30μm in the near future, with a f inal goal of 15μm.[1] DRIE is the preferred technology choice for TSV etch. TSV is implemented at dif-ferent phases of the manufacturing f low. There are two main categories: before front end of line (FEOL) which is the via-f irst scheme and back end of line (BEOL) called the via-last scheme. Since process requirements vary for each approach the TSV etch reactor must be f lexible enough for a range of applications. This study dis-cusses key requirements for TSV etch as well as applications that employ deep sili-con etch outside the regime of TSVs.

Deep silicon etch can be performed today by two signif icantly different modes of operation. In one mode, passivation to

Via-First

Via-Last

TSV etch TSV fill

TSV etchDevicefabrication

Devicefabrication

Grinding Stacking

TSV fill

Figure 1. TSV integration falls into two categories: via-first and via-last.



the sidewalls of the trenches is provided by heavily polymerizing chemistries such as C4F8. For TSV etch applications, an etch reactor can use alternating gases that f irst etch silicon then deposit a protective coating on the newly etched feature. The process is repeated making a series of iso-tropic etch bubbles in the silicon to form through-silicon vias. This technique of using alternating deposition and etch steps for etching is known as the Bosch or time multiplexed gas modulation (TMGM) process.

The second mode is called the “steady state process.” In this mode, etch is dominated by halogen chemistries such as f luorine, bromine or chlorine. Passivation to the trench sidewalls is provided by introduc-tion of oxidizing chemistries such as O2, N2, etc. The majority of deep Si etch processes included in our study were per-formed using etch gases such as SF6, NF3, Cl2, and HBr.

The steady state process is a clear favorite for applications where absolutely no side-wall attack is allowed such as deep trench isolation, RF power devices, opto-MEMS, etc. It is possible that via-first applications may adopt this method at a future date as via CDs continue to shrink. Although the steady state process has excellent sidewall integrity, it lacks the higher etch rates and

higher selectivity seen today with Bosch or derivative processes.

Laser drilling is another approach used for forming TSV features. The disadvantages of laser drilling are large minimum hole size and, because each via must be drilled separately, limited throughput. As TSV CDs continue to shrink, and via count per die continues to increase, laser drill-ing is expected to be supplanted by DRIE technology.

TSV Integration SchemesThe entry point for TSV etch varies for dif-ferent device requirements. Some manu-

facturers will introduce TSV at the FEOL. This via-f irst scheme requires the most changes to interconnect circuit layout, but may ultimately offer the greatest benefits. The simplest way to introduce TSV with minimum circuit layout impact is to intro-duce TSV formation at the BEOL (via-last). These schemes are shown in Figure 1 and explored in more detail below.

Via-First SchemeIn this approach, vias are etched during FEOL processing. The via-f irst approach typically has smaller CDs allowing for higher via density, with a typical via CD in the range of 0.5-5.0μm. Along with the smaller CD, depth is generally shal-lower, on the order of 20-50μm. This approach has advantages in that when vias are formed before the device, only good wafers are used to form the f inal device, minimizing yield impact of TSV forma-tion. This approach is favored where high via density is required such as in logic.

Via-Last SchemeIn the via-last approach, the vias are formed after BEOL or bonding, on a full thick-ness wafer from the front-side or from the backside on a thinned wafer. The biggest difference is the larger features and more complicated f ilm stacks. Via-last will involve etching silicon and oxide stack in one chamber in order to provide the lowest cost. In the case of via-last, the process-ing can be done by the IDM or packaging house. Currently, via-last is in production today for CMOS image sensors.

Experimental WorkApparatusAll experiments were conducted in an inductively-coupled plasma (ICP) etch reactor using the TMGM approach (Figure 2). The source has a dual coil design that enables radial control of plasma den-sity across the wafer by varying the current ratio between the inner and outer coils.[2]

The wafer to be etched sits on a ceramic electrostatic chuck (CESC) that can oper-

Tunable Gas Nozzle- Gas flow rate- Radial flow distribution

Dual Tunable RF Source- Source RF power- Radial Plasma Uniformity

Low Frequency RF Bias- Ion energy

Ceramic ESC- Wafer temp. control- RF bias power

Throttling GateValve- Pressure control

Turbo Pump

Figure 3. Test pattern with four via CD sizes (4μm, 10μm, 25μm, 50μm) with three differ-ent pitches and corresponding trenches.

Figure 2. ICP reactor layout showing adjustable parameters.



ate between 20-60°C with



parameters that change are reactor pres-sure, gas f low, gas type and RF power levels for source and bias.

In a traditional TMGM process, any sig-nif icant reduction in sidewall scallop is almost always accompanied by a trade-off such as a reduction in the Si etch rate. By using a new hardware scheme and a new process regime, plasma eff iciency was increased for this TMGM process. In doing so, we achieved a signif icant improvement in the sidewall roughness for a given etch rate. We were able to break this industry-accepted trade-off of etch rate vs. scallops. This hardware is able to reduce sidewall roughness from 280nm to below 80nm without any loss in etch rate, as shown in Figure 7. It is expected that the process improve-ment should be extendable to a sidewall roughness below 50nm without any adverse impact on Si etch rate.

This concept will be most valuable for v ia-f i r st appl icat ions where sidewal l integ r it y i s es sent ia l for subsequent integration steps such as liner and metal deposition.

ConclusionsSome of the basic processes for via-f irst and via-last applications have been dis-cussed. An increase in silicon etch rate was seen with an increase in the source power. This process trend appl ies to both via-f irst and via-last applications. Also, a novel concept was introduced where excellent sidewall roughness can be achieved without any trade-off in sili-con etch rate. ■

References[1] ITRS 2007 Edition Interconnect. Table INTC6,

page 46.

[2] John Holland et al., 48th AVS Symposium, San

Francisco, CA, 2001.

Jon Farr is a senior process engineer responsi-ble for process development in through-silicon via technology and is part of the Etch business unit of Applied Materials. He received his B.S. in physics from Arizona State University.

Khalid Sirajuddin is a key account tech-nologist at Applied, currently focused on TSV process development. He received his B.S. in chemical engineering from the University of Texas at Austin.

Sharma Pamarthy is a senior process manager at Applied and program manager for TSV Etch. He received his masters in chemical engineering from Oklahoma State University and his M.B.A. from Santa Clara University.

Ajay Kumar is general manager of Applied’s Mask Etch and Cleans group. He holds a Ph.D. in applied physics from the Indian Institute of Technology. Article Contact: [email protected]

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Figure 7. (Left) Scalloping from a standard, unoptimized TMGM process; (right) modifica-tions to the process regime achieved significant reduction in scalloping.

Figure 6. Effect of etch time on silicon etch depth.

Authors


■ running headRTP

Virtual Metrology Improves Thermal Uniformity forCritical Anneals

For transistors with gate lengths of 32nm and below, it is important to maximize uniformity in rapid thermal processing (RTP) spike anneals while minimizing variations across the wafer. Established of f-line methods of monitoring process and tool performance are costly and not time-efficient. An advanced analysis package featuring a virtual metrology module analyzes and transforms process data that can be used wafer-to-wafer to improve thermal uniformity. This innovative new method can significantly reduce wafer processing errors, enhance yield, and minimize production cost.

Keywords: RTP, Virtual Metrology, WISR, Metrology, Wafer Uniformity, Advanced Process Control

The control software of modern RTP sys-tems can acquire process data with high resolution and at high data rates. In this article, we explore how this information, in particular wafer rotation angle and wafer rotation speed, can be used to pre-dict on-wafer process results using WISR (wafer interdiction and scrap reduction) advanced analysis.

WISR is an advanced process control plat-form for the collection, storage, visualiza-tion, and analysis of process parameters from production tools. One of the key analysis features of WISR is the ability to create virtual sensors. Virtual sensors are calculated parameters derived from physical sensors that can provide real-time

and statistical representations of process health.

We focus here on the WISR platform’s capability to transform time series cham-ber parameters from the pyrometers and the magnetic levitation controller into thermal wafer images. This information would be available any time during the recipe execution and provide wafer-to-wafer handoff correction. We describe the implementation of WISR analysis and show how temperature maps and han-doff corrections correlate with off-line metrology in RTP critical anneals.

RTP ChallengesThe variability of the thermal properties of wafers during RTP has always challenged the control performance of the system. As gate lengths shrink to 32nm and 22nm, there is an increased need to address smaller scale variability within the wafer. There are several root causes for this variability. The issue of “pattern effect” has been described, where the presence of dopants and thin film layers in the patterned product area of the wafer significantly affects the thermal and optical properties of that wafer.[1] Also, the properties of the bulk of the substrate can introduce variations in photon absorp-tion across the wafer, which contributes to temperature variations.[2] Thus, tempera-ture measurements made while annealing implanted wafers can result in errors that can be incorrectly interpreted as tempera-ture non-uniformity.

As a consequence, a signif icant portion of process work on an RTP tool involves processing expensive, specialized monitor wafers using production recipes to antici-pate the uniformity of product wafers. These monitor wafers are analyzed to measure sheet resistance (Rs) using the 4-point probe method, and f ilm thick-ness using an ellipsometer. By optimiz-ing process parameters, variations on the monitor wafers are minimized, which results in improved uniformity on product wafers. Subsequently, periodic processing of monitor wafers is necessary to ensure product yield.

Although the use of monitor wafers is the establ ished method for checking process health and tool per formance, it is expensive and not time-eff icient. Process tools must wait for metrology results to be verif ied before processing product wafers, which hinders wafer throughput and impacts tool ut i l iza-t ion. Monitor wafers are only ef fec-tive indicators of process health if the frequency of their measurement is suf-f icient ly high. With more aggressive thermal processing requirements, faster and more cost-eff icient approaches are needed to monitor process health, such as faster ramp rates, minimal t ime at peak temperature, and higher demands for uniformity and repeatability.

In other f ields of semiconductor process-ing, particularly in chemical mechanical


■ Improving Thermal Uniformity

planarization (CMP), methods of utiliz-ing relevant process parameters to predict wafer-to-wafer data for use in advanced process control (APC) have been devel-oped and appl ied successfu l ly. New demands in thermal processing and the high cost of monitor wafers give RTP tremendous potential to benefit from this type of information.

The magnet ic lev it at ion cont rol ler (MagLev) on RTP tools is able to pro-vide high resolution (100Hz) data of the wafer rotation angle and rotation speed as a function of time. WISR collects, analyzes, and displays this information. The virtual metrology (VM) module in WISR reads and analyzes the temperature readings and MagLev data to compute contour maps of temperature variation at any point during the recipe and provides a suggested robot handoff correction to improve the ther-mal uniformity of the wafer. By focusing on these critical parameters for 300mm wafers, we were able to generate the wafer-to-wafer data needed for APC.

Experimental SetupThe RTP chamber used consists of three main parts: light source, wafer support mechanism and temperature measurement system. The light source is a tightly-packed honeycomb array of tungsten f ilament lamps with an integrated ref lector for each

lamp. The wafer rests on a susceptor capable of withstanding high temperature. This is mounted to a metal rotor that is magnetical-ly coupled to an external motor for rotation and levitation control. The wafer support design and all materials are chosen carefully to shield the lamp radiation from the wafer backside, where pyrometers measure the wafer temperature. Seven fiber optic probes situated at f ixed radii within the bottom ref lector plate transmit the wafer radiation readings to the pyrometers below.

The rotation speed is controlled very tightly, and the rotational angle is mea-sured with an accuracy of approximately 1°. The high rate of temperature read-

ings from the pyrometer probe allows the transformation of the stream of tempera-ture data to points (x,y) on the wafer to be calculated with high accuracy. Figure 1 shows the temperature data for a typical spike anneal. The inset focuses on the peak temperature and shows the temperature for each probe.

Experimental Results and AnalysisThe primary capability of VM is the ability to produce wafer temperature contour maps for any given time during recipe execution. Using the fast fourier transform (FFT) and filtering algorithms contained within the VM module of WISR, we were able to separate temperature averages from the rotational oscillation.[3] To validate our algorithm, this investigation was limited to spike anneal reci-pes due to their high sensitivity to tempera-ture variation. Among the factors influencing the effectiveness of a spike anneal, the peak temperature is the most important. Therefore, only the contour map corresponding to the peak temperature in VM was compared to off-line metrology.

Figure 2 shows peak temperature contours from an implant wafer derived from two sources. The VM data is shown on the left and off-line Rs measurements from the same wafer are shown on the right. Significant correlation between the two distributions is observed.

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During high temperature processing of short duration applications such as spike anneals, wafer centering is crucial to pro-cess performance. In an experiment per-formed in a 300mm RTP chamber, f ive wafers were processed using a spike anneal recipe. The first wafer was processed at the center of the chamber. For the remaining four wafers, the robot parameters were changed to place the wafers signif icantly off-center in four different directions: posi-tive and negative tracking (left and right)

and extension (forward and backward) from chamber center.

The metrology results were compared to the VM contour maps at the peak temperature of the recipe (Figure 3). The temperature distributions on all f ive wafers indicate a strong correlation between VM and off-line metrology.

The results above gave us confidence to per-form further analysis on factors contributing

to wafer uniformity. The contour maps generated by VM when the wafers were intentionally placed off-center have a distinctive thermal signature (Figure 3, left). The region of the wafer edge farthest away from the chamber center was cooler than the rest of the wafer. Similarly, the region of the wafer edge closest to the chamber center was hotter than the rest of the wafer. These results demonstrate that temperature

variation at the edge of the wafer at the peak temperature is directly related to the place-ment of the wafer. This suggests that VM temperature measurements can be used to provide wafer-to-wafer handoff correction.

Calculation of the handoff correction is split into three main computational blocks, begin-ning with generating the contour maps. Using the contour map, the location of the center of the wafer is computed based on the tempera-ture variation throughout the wafer. Lastly,

Figure 5. Absolute value of the difference between VM and Optitune tracking coordinate values. The average difference is 0.036mm, including the wafer 9 outlier point.

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Figure 4. Tracking values reported by VM and off-line metrology (Optitune).



the difference between the calculated center of the wafer and the center of the susceptor is converted to polar coordinates and used to correct the placement of the next wafer.

The VM-based wafer placement capabil-ity was verified using monitor wafers on a production RTP system. Similar to VM, the Optitune tuning algorithm provides input for handoff corrections by performing a pro-cess-based tuning algorithm on the 121-point metrology data. Monitor wafers were cycled and Rs measurements taken. Sixteen monitor wafers were processed over 32 days in a high-volume production environment.

A comparison of VM and Optitune val-ues for angular placement, referred to as

tracking, is shown in Figure 4. It was observed that the VM data is in good agreement with Optitune tracking with a correlation coefficient of 0.96. Wafer number 9 in this plot is shown to be at least 0.4mm away from the chamber cen-ter in the tracking direc-tion. Virtual metrology detected this gross mis-placement, and the robot was manually adjusted to place subsequent wafers closer to thermal zero,

i.e. centrally placed on the susceptor.

Figure 5 shows the absolute value of the difference between VM and Optitune for the tracking-coordinate. The differences between the reported tracking-correction values of VM and Optitune are minimal with an average difference of 0.036mm including the outlier data-point corresponding to wafer number 9.

Figure 6 shows extension coordinate values for VM and Optitune for the same 16 monitor wafers. While VM data follows the same trend as its metrology counterpart for the exten-sion coordinate, it does not match as well as tracking does. Similarly, the absolute value of the difference between VM and Optitune is

shown in Figure 7. The maximum difference in the extension-coordinate is not as severe as the tracking coordinate, but there is more significant f luctuation in the extension value with an average difference of 0.05mm.

The decoupled analysis of extension and tracking for VM and metrology shows a very strong correlation. In order to further con-firm the accuracy of VM, the radial distance of VM and metrology must be compared. Figure 8 shows the radial distance from the center of the chamber for VM and Optitune. Similar to the results shown for extension and tracking individually, VM data exhibits strong correlation with metrology.

DiscussionPlacement corrections from metrology mea-surements and VM correlate well. However, there are differences that seemingly limit the applicability of VM. It must be noted that in off-line metrology, aerial resolution is on the order of a few square millimeters com-pared to 5-6cm2 for VM. The discrepancy in the measurement scale between these two methods does not automatically discount the accuracy of VM. Off-line metrology takes a coarser measurement: the thermal conduc-tion properties of bulk silicon minimize thermal gradients, making them no more sensitive than VM data for a 300mm wafer.

Also, by measuring temperature directly, VM is less affected by inconsistencies in the

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Figure 7. Absolute value of the difference between VM and Optitune for the extension coordinate.


Victor Vitale is a process engineer with

Applied’s Front End Products (FEP) core

engineering unit. He received his B.S. in

electrical engineering from Santa Clara

University.

Wolfgang Aderhold is a senior member

of the technical staff in Applied’s FEP divi-

sion and a process technologist with the

RTP core engineering unit. He received

his Dipl.-Ing. and Dr.-Ing. degree in elec-

trical engineering from the University of

Erlangen-Nuernberg, Germany.

Aaron Hunter leads the core technology

unit of Applied’s RTP division. He received

his B.A. in ph

manufacturers - applied materials...in this study, a fully integrated run-to-run (r2r) control...

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