marc riedel ph.d. defense, electrical engineering, caltech november 17, 2003 combinational circuits...
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Marc RiedelPh.D. Defense, Electrical Engineering, Caltech
November 17, 2003
Combinational Circuitswith Feedback
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Combinational Circuits
Logic GateBuilding Block:
1x2x
dx
di
ix
,,1allfor
{0,1}
{0,1}{0,1}: dg
),,( 1 dxxg
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Combinational Circuits
Logic GateBuilding Block:
1x2x
dx
),,( 1 dxxg
feed-forward device
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Combinational Circuits
“AND” gate
0001
Common Gate:
1x
2x
g0011
0101
1x 2x g
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Combinational Circuits
“OR” gate
0011
0101
0111
Common Gate:
1x
2x
g
1x 2x g
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Combinational Circuits
“XOR” gate
0011
0101
0110
Common Gate:
1x
2x
g
1x 2x g
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),,( 11 mxxf a
),,( 12 mxxf a
),,( 1 mn xxf a
inputs outputs
The current outputs depend only on the current inputs.
Combinational Circuits
1x
2x
mx
mi
ix
,,1allfor
{0,1}
nj
mjf
,,1allfor
{0,1}{0,1}:
combinationallogic
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),,( 1 mn xxf a
),,( 11 mxxf a
),,( 12 mxxf a),,( 1 mxxf a
Combinational Circuits
inputs outputs
The current outputs depend only on the current inputs.
1x
2x
mx
combinationallogic
gate
mi
ix
,,1allfor
{0,1}
nj
mjf
,,1allfor
{0,1}{0,1}:
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Generally feed-forward (i.e., acyclic) structures.
Combinational Circuits
x
y
x
y
z
z
c
s
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Generally feed-forward (i.e., acyclic) structures.
Combinational Circuits
0
1
0
1
1
1
0
1
1
0
1
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Feedback
How can we determine the output without knowing the current state?
...
...
...
...
feedback
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Feedback
How can we determine the output without knowing the current state?
...
...
...
...
?
?
?
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fa a
Example: outputs can be determined in spite of feedback.
x x
Feedback
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fa a
0 0
Example: outputs can be determined in spite of feedback.
Feedback
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fa a
0 0
00
Example: outputs can be determined in spite of feedback.
Feedback
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fa a
Example: outputs can be determined in spite of feedback.
Feedback
x x
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fa a
1 1
Example: outputs can be determined in spite of feedback.
Feedback
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fa a
1 1
11
There is feedback is a topological sense, but not in an electrical sense.
Example: outputs can be determined in spite of feedback.
Feedback
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fa a
Admittedly, this circuit is useless...
Example: outputs can be determined in spite of feedback.
Feedback
x x
x
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Rivest’s Circuit
Example due to Rivest:
1x 2x 3x 1x 2x 3x
1fa a 2fa a 3fa a 4fa a 5fa a 6fa a
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0 0
Example due to Rivest:
Rivest’s Circuit
2x 3x 2x 3x
1fa a 2fa a 3fa a 4fa a 5fa a 6fa a
1x 1x
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Rivest’s Circuit
0 0
0
Example due to Rivest:
2x 3x 2x 3x
1fa a 2fa a 3fa a 4fa a 5fa a 6fa a
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Rivest’s Circuit
Example due to Rivest:
1x 2x 3x 1x 2x 3x
1fa a 2fa a 3fa a 4fa a 5fa a 6fa a
0 0
0
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1 1
Example due to Rivest:
Rivest’s Circuit
2x 3x 2x 3x
1fa a 2fa a 3fa a 4fa a 5fa a 6fa a
1x 1x
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1
1 1
Example due to Rivest:
Rivest’s Circuit
2x 3x 2x 3x
1fa a 2fa a 3fa a 5fa a 6fa a4fa a
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4fa a
Example due to Rivest:
1x 1x1 1
Rivest’s Circuit
2x 3x 2x 3x
1fa a 2fa a 3fa a 5fa a 6fa a1
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Rivest’s Circuit
Example due to Rivest:
)( 321 xxx )( 312 xxx )( 213 xxx
321 xxx 312 xxx 213 xxx
1x 2x 3x 1x 2x 3x
3 inputs, 6 fan-in two gates. 6 distinct functions, each dependent on all 3 variables.
Addition: ORMultiplication: AND
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Rivest’s Circuit
Individually, each function requires 2 fan-in two gates:
)( 321 xxx
)( 3211 xxxf a 3122 xxxf a )( 2133 xxxf a
3214 xxxf a )( 3125 xxxf a 2136 xxxf a
1x2x
3x
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An equivalent feed-forward circuit requires 7 fan-in two gates.
1fa a1x
2x
3x
6fa a
2fa a
5fa a
4fa a
3fa a
1x
2x
3x
2x
3x
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A feedback circuit with fewer gates than any equivalent feed-forward circuit.
Rivest’s Circuit
1x 2x 3x 1x 2x 3x
1fa a 2fa a 3fa a 4fa a 5fa a 6fa a
3 inputs, 6 fan-in two gates.
6 distinct functions.
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Rivest’s Circuit
n inputs 2n fan-in two gates,
2n distinct functions.
1x nx 1x nx
1fa a
nfa a1nfa a
nf2a a
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1fa a...
...
...
...
a
2fa a
Rivest’s Circuit
1n gates
12 n gates
An equivalent feed-forward circuit requires fan-in two gates.
23 n
nf2a
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Rivest’s Circuit
n inputs 2n fan-in two gates,
2n distinct functions.
A feedback circuit with the number of gates of any equivalent feed-forward circuit.
32
1x nx 1x nx
1fa a
nfa a1nfa a
nf2a a
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Prior Work
• Kautz first discussed the concept of feedback in logic circuits (1970).
• Huffman discussed feedback in threshold networks (1971).
• Rivest presented the first, and only viable, example of a combinational circuit with feedback (1977).
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Prior Work
F(X) G(X)e.g., add e.g., shift
Stok discussed feedback at the level of functional units (1992).
Malik (1994) and Shiple et al. (1996) proposed techniques for analysis.
X
G(F(X))
Y
F(G(Y))
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Questions
1. Is feedback more than a theoretical curiosity, even a general principle?
322. Can we improve upon the bound of ?
3. Can we optimize real circuits with feedback?
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Key Contributions
2. Efficient symbolic algorithm for analysis (both functional and timing).
1. A family of feedback circuits that are asymptotically the size of equivalent feed-forward circuits. 2
1
3. A general methodology for synthesis.
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Ph.D. Defense
• Present examples with same property as Rivest’s circuits.
• Illustrate techniques for analysis.
• Focus on synthesis: methodology, examples, optimization results.
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Example
43218 )( xxxxf
43215 xxxxf
43214 )( xxxxf
34213 xxxxf
43212 xxxxf
)( 43211 xxxxf
34217 )( xxxxf
43216 xxxxf
a
not symmetrical
4 inputs
8 gates
8 distinct functions
x4
x3
x2
x1
x4
x3
x2
x1
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Examples, multiple cycles
x1
x1
x1
x1
x2
x2
x3
x3
321311 2xxxxxxf a
3212 xxxf a
a )( 3123 xxxf
2134 xxxf a
a )( 3215 xxxf
a3216 xxxf a
aa )( 3127 xxxf
aa
1138 xxxf
aa )( 3219 xxxf
, 3 inputs9 gates , 9 distinct functions
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Example
x1 x2 x3 x4 x5 x1 x2 x3 x4 x5
1f 2f 3f 4f 5f 6f 7f 8f 9f 10fa
11f 12f 13f 14f 15f 16fa 17f 18f 19f 20fa
, 5 inputs 20 gates , 20 distinct functions.
(“stacked” Rivest circuits)
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½ Example
Generalization: family of feedback circuits ½ the size of equivalent feed-forward circuits.
3111 ff a
a
3222 ff a
a
213231333 fffff a
a
Xiiii offunctionsare,,, nxxxX ,,, 21
(sketch)
X
X
X
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Analysis
• Functional analysis: determine if the circuit is combinational and if
so, what values appear.
• Timing analysis: determine when the values appear.
Contributions:
1. Symbolic algorithm based on Binary Decision Diagrams.
2. Optimizations based on topology (“first-cut” method).
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Analysis
1x 2x 3x 1x 2x 3x0 0 0 00 0
01
Assume gates each have unit delay.
02 01 0102 02
arrival times
Explicit analysis:
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0 0 0 00 0
01 02 01 0102 02
0 1 0 10 0
01 11 01 0302 04
1x 2x 3x 1x 2x 3x
Analysis
Explicit analysis:
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1x0 1 0 10 0
01 11 01 0302 04
2x 3x 1x 2x 3x
n inputs n2 combinations
Exhaustive evaluation intractable.
Analysis
Explicit analysis:
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1x 2x 3x 1x 2x 3x
Symbolic analysis:
1x
31 xx
321 xxx321 xxx
1fa a
01 :
12 :
03 :
14 :
Analysis
654,32 ,,, fffffasimilarly for
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Symbolic analysis:
fa a
01
02
11
12
Analysis
),,( 11 nxxc ),,( 12 nxxc
),,( 11 nxxc ),,( 12 nxxc
),,( 1 nxxd undefined
evaluates to 1
evaluates to 0
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Symbolic analysis:
fa a
01-7
08-28
11-10
111-21
Analysis
),,( 11 nxxc ),,( 12 nxxc
),,( 11 nxxc ),,( 12 nxxc
),,( 1 nxxd undefined
evaluates to 1
evaluates to 0
range of values
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Synthesis
• General methodology: optimize by introducing feedback in the substitution/minimization phase.
• Optimizations are significant and applicable to a wide range of circuits.
Design a circuit to meet a specification.
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Example: 7 Segment Display
Inputs a
b
c
d
e
f
g
Output
1001
0001
1110
0110
1010
0010
1100
0100
1000
00000123 xxxx
9
8
7
6
5
4
3
2
1
0
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Example: 7 Segment Display
g
f
e
d
c
b
a
)(
)(
))((
))((
))((
)(
))((
20321
10102321
2012103210
102213321
210203321
21310
302321320
xxxxx
xxxxxxxx
xxxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxx
xxxxxxxxx
a
b
c
d
e
f
g
Output
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Substitution/Minimization
Basic minimization/restructuring operation: express a function in terms of other functions.
Substitute b into a:
(cost 9)a ))(( 302321320 xxxxxxxxx
(cost 8)
Substitute c into a:(cost 5)
Substitute c, d into a:(cost 4)
a )( 323212 bxxxxxbx
a cxxcx 321
a dccx 1
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Substitution/Minimization
Berkeley SISTool
a ))(( 302321320 xxxxxxxxx
},,,{ fdcb
target function
substitutional set
a dccx 1
low-cost expression
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Acyclic Substitution
g
f
e
b
a
c
d
Select an acyclic topological ordering:
g
f
e
d
c
b
a
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g
f
d
c
b
a
edcaxx 21
dccx 1
xxxxxxxxx 102213321 ))((
dxxxxxx 102320 )(
cdxx 10 )(
Select an acyclic topological ordering:
Cost (literal count): 37
Acyclic Substitution
e 3cxb d
ba f
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Acyclic Substitution
Select an acyclic topological ordering:
Nodes at the top benefit little from substitution.
g
f
d
c
b
a
edcaxx 21
dccx 1
xxxxxxxxx 102213321 ))((
dxxxxxx 102320 )(
cdxx 10 )(
e 3cxb d
ba f
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Cyclic Substitution
Try substituting every other function into each function:
Not combinational!Cost (literal count): 30
0
1
ex
dccx
fba
geex
bcdx
gxaxex
egxxax
2
3
321
202 f
g
f
d
c
b
a
e
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Cost 30Lower bound
Cost 37
Upper boundAcyclic substitution
Unordered substitution
Cyclic solution? Cost 34
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Cyclic Substitution
g
f
e
d
c
b
a
Cost (literal count): 34
Combinational solution:
x e0
bxa 3
gxxxax 1023 )(
axxex 321 )( exxxxxx 312320 )(
cxxcx 301
xxxfx 1023 )( f
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Cyclic Substitution
Cost (literal count): 34
Combinational solution:
topological cycles
g
f
e
d
c
b
a
x e0
bxa 3
gxxxax 1023 )(
axxex 321 )( exxxxxx 312320 )(
cxxcx 301
xxxfx 1023 )( f
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Inputs x3, x2, x1, x0
Cost (literal count): 34
ba
ga
e
e
e
c
1
no electrical cycles
Cyclic Substitution
g
f
e
d
c
b
a
x e0
bxa 3
gxxxax 1023 )(
axxex 321 )( exxxxxx 312320 )(
cxxcx 301
xxxfx 1023 )( f
= [0,0,1,0]:
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g
f
e
d
c
b
a
Cost (literal count): 34
ba
ga
e
e
e
c
1
1
1
0
1
1
1
0
Cyclic Substitution
no electrical cycles
x e0
bxa 3
gxxxax 1023 )(
axxex 321 )( exxxxxx 312320 )(
cxxcx 301
xxxfx 1023 )( f
Inputs x3, x2, x1, x0 = [0,0,1,0]:
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g
f
e
d
c
b
a
Cost (literal count): 34
ba
ga
e
e
e
c
1
1
1
0
1
1
1
0
a
b
c
d
e
f
g
Cyclic Substitution
x e0
bxa 3
gxxxax 1023 )(
axxex 321 )( exxxxxx 312320 )(
cxxcx 301
xxxfx 1023 )( f
Inputs x3, x2, x1, x0 = [0,0,1,0]:
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g
f
e
d
c
b
a
Cost (literal count): 34
ba
ga
e
e
e
c
1
1
1
0
1
1
1
0
a
b
c
d
e
f
g
Cyclic Substitution
x e0
bxa 3
gxxxax 1023 )(
axxex 321 )( exxxxxx 312320 )(
cxxcx 301
xxxfx 1023 )( f
Inputs x3, x2, x1, x0 = [0,0,1,0]:
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g
f
e
d
c
b
a
Cost (literal count): 34
ba
ga
e
e
e
c
1
1
1
0
1
1
1
0
a
b
c
d
e
f
g
Cyclic Substitution
x e0
bxa 3
gxxxax 1023 )(
axxex 321 )( exxxxxx 312320 )(
cxxcx 301
xxxfx 1023 )( f
Inputs x3, x2, x1, x0 = [0,0,1,0]:
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g
f
e
d
c
b
a
Cost (literal count): 34
Cyclic Substitution
x e0
bxa 3
gxxxax 1023 )(
axxex 321 )( exxxxxx 312320 )(
cxxcx 301
xxxfx 1023 )( f
Inputs x3, x2, x1, x0 = [0,1,0,1]:
![Page 68: Marc Riedel Ph.D. Defense, Electrical Engineering, Caltech November 17, 2003 Combinational Circuits with Feedback](https://reader036.vdocuments.net/reader036/viewer/2022062518/56649d4c5503460f94a2a14d/html5/thumbnails/68.jpg)
g
f
e
d
c
b
a
Cost (literal count): 34
Cyclic Substitution
ba
a
a
1
0
c
f
x e0
bxa 3
gxxxax 1023 )(
axxex 321 )( exxxxxx 312320 )(
cxxcx 301
xxxfx 1023 )( f
Inputs x3, x2, x1, x0 = [0,1,0,1]:
no electrical cycles
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g
f
e
d
c
b
a
Cost (literal count): 34
1
0
1
0
1
1
1
Cyclic Substitution
ba
a
a
1
0
c
f
x e0
bxa 3
gxxxax 1023 )(
axxex 321 )( exxxxxx 312320 )(
cxxcx 301
xxxfx 1023 )( f
no electrical cycles
Inputs x3, x2, x1, x0 = [0,1,0,1]:
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g
f
e
d
c
b
a
Cost (literal count): 34
a
b
c
d
e
f
g
Cyclic Substitution
1
0
1
0
1
1
1ba
a
a
1
0
c
f
x e0
bxa 3
gxxxax 1023 )(
axxex 321 )( exxxxxx 312320 )(
cxxcx 301
xxxfx 1023 )( f
Inputs x3, x2, x1, x0 = [0,1,0,1]:
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g
f
e
d
c
b
a
Cost (literal count): 34
Cyclic Substitution
1
0
1
0
1
1
1ba
a
a
1
0
c
f
a
b
d
e
f
g
x e0
bxa 3
gxxxax 1023 )(
axxex 321 )( exxxxxx 312320 )(
cxxcx 301
xxxfx 1023 )( f
Inputs x3, x2, x1, x0 = [0,1,0,1]:
c
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Synthesis
Strategy:
• Allow cycles in the substitution phase of logic synthesis. • Find lowest-cost combinational solution.
21213
321321
312321
)(
)(
)(
xxxxxc
xxxxxxb
xxxxxxa
Collapsed:
Cost: 17
321
1321
323
xxaxc
cxxxxb
xxbxa
Solution:
Cost: 13
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“Break-Down” approach
• Exclude edges• Search performed outside space
of combinational solutions
cost 12
cost 13 cost 12
cost 13combinational
cost 14
Branch and Bound
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“Build-Up” approach
• Include edges• Search performed inside space
of combinational solutions
cost 17
cost 16cost 15not combinational
cost 14
Branch and Bound
cost 13best solution
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Implementation: CYCLIFY Program
• Incorporated synthesis methodology in a general logic synthesis environment (Berkeley SIS package).
• Trials on wide range of circuits– randomly generated– benchmarks– industrial designs.
• Consistently successful at finding superior cyclic solutions.
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Benchmark Circuits
Cost (literals in factored form) of Berkeley SIS Simplify vs. Cyclify
Circuit # Inputs # Outputs Berkeley Simplify Caltech Cyclify Improvementdc1 4 7 39 34 12.80%ex6 8 11 85 76 10.60%p82 5 14 104 90 13.50%t4 12 8 109 89 18.30%bbsse 11 11 118 106 10.20%sse 11 11 118 106 10.20%5xp1 7 10 123 109 11.40%s386 11 11 131 113 13.70%dk17 10 11 160 136 15.00%apla 10 12 185 131 29.20%tms 8 16 185 158 14.60%cse 11 11 212 177 16.50%clip 9 5 213 189 11.30%m2 8 16 231 207 10.40%s510 25 13 260 227 12.70%t1 21 23 273 206 24.50%ex1 13 24 309 276 10.70%exp 8 18 320 262 18.10%
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Benchmarks
Example: EXP circuit
Cyclic Solution (Caltech CYCLIFY): cost 262
Acyclic Solution (Berkeley SIS): cost 320
cost measured by the literal count in the substitute/minimize phase
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Discussion
• A new definition for the term “combinational circuit”: a directed, possibly cyclic, collection of logic gates.
• Most circuits can be optimized with feedback.
• Optimizations are significant.
Paradigm shift:
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Current Work
• Implement more sophisticated search heuristics (e.g., simulated annealing).
• Extend ideas to a decomposition and technology mapping phases of synthesis.
• Address optimization of circuits for delay with feedback.
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Future Directions
inputs outputsdata structure
Structured Network Representations
databases, biological systems,...
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Binary Decision Diagrams
• Introduced by Lee (1959).• Popularized by Bryant (1986).
Graph-based Representation of Boolean Functions
• compact (functions of 50 variables)• efficient (linear time manipluation)
Widely used; has had a significant impact on the CAD industry.
0
1
fa
10
1x
2x
3x
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Binary Decision Diagrams
0
1
fa
10
1x
2x
3x1 1 1 1
0000111
0011001
0101010
0000011
1x 2x 3x f
0 1BDDs generally defined as Directed Acyclic Graphs
Graph-based Representation of Boolean Functions
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Binary Decision Diagrams
Short described a cyclic structure for a BDD variant (1960).We suggest cycles are a general phenomenon.
1fa a 2fa a 3fa a 4fa a 5fa a 6fa a
1x 2x 3x 1x 2x 3x
00 1 01 1
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Binary Decision Diagrams
Short described a cyclic structure for a BDD variant (1960).We suggest cycles are a general phenomenon.
1fa a 2fa a 3fa a 4fa a 5fa a 6fa a
1x 2x 3x 1x 2x 3x
00 1 01 1
0 * * 0
1fa a1x 2x 3x
0
1 0 1 1
1
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Binary Decision Diagrams
Short described a cyclic structure for a BDD variant (1960).We suggest cycles are a general phenomenon.
1fa a 2fa a 3fa a 4fa a 5fa a 6fa a
1x 2x 3x 1x 2x 3x
00 1 01 1
)( 3211 xxxf a 3122 xxxf a )( 2133 xxxf a
3214 xxxf a )( 3125 xxxf a 2136 xxxf a
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Binary Decision Diagrams
Short described a cyclic structure for a BDD variant (1960).We suggest cycles are a general phenomenon.
1fa a 2fa a 3fa a 4fa a 5fa a 6fa a
1x 2x 3x 1x 2x 3x
00 1 01 1
Future research awaits...