Marcello TraiolaPh.D.

B marcellotraiola@gmail.com® http://www.lirmm.fr/~traiola

°marcellotraiolaBorn in Naples (Italy)

Last update on 06/25/2020

In 2019, I earned a Ph.D. degree in Computer Engineering from the Montpellier University, inFrance. In 2016, I earned a Master’s degree in Computer Engineering - summa cum laude -from the Italian University “Federico II” of Naples, Italy.From Octobre 2019 to January 2020 I was in the USA at the semiconductor company MediaTekUSA Inc., as intern R&D engineer. Since February 2020, I am at the Lyon Institute of Technology(École Centrale de Lyon), in France, as post-doctoral researcher.I actively research on Emerging Computing Paradigms with focus on design, test and reliability.

Professional Experience in Academysince Feb.

2020Post-doctoral researcherLyon Institute of Technology (INL), École Centrale de Lyon, FranceTeam Heterogeneous System Design

Subject : The main goal of this post-doc is to analyze how emerging computing paradigmsand technologies can be exploited to design new hardware accelerators for CNNin deep-learning applications under several constraints: Area, Energy Efficiency,Accuracy, Reliability, Security, etc. The research methodology will analyzeemerging computing paradigms (e.g., AxC, In-Memory Computing) and developmodels. Such models will compose a DataBase of possible “operators”. Eachoperator will be associated to many technologies (i.e., Nanophotonics, Nanowires,non-volatile Memory, etc.) thus leading to different characteristics. A SearchEngine will exploit the operator DB by selecting the best solution w.r.t. the userconstraints. Each solution has to be evaluated at application level in terms ofArea, Energy, Accuracy, Reliability, etc. without simulating/running the CNN.Analytical and Probabilistic approaches will be thus investigated. The result willbe the best Hardware (HW) architecture/technology able to implement the givenCNN topology satisfying the user constraints. The identified HW architecture willbe synthesized on a programmable HW platform (FPGA) to have an emulator ofthe CNN accelerator. At Long term, the ultimate goal is to produce a real HWprototype exploiting emerging technologies.

EducationOct. 2016 –Sep. 2019

Ph.D Degree - Computer EngineeringLaboratory of Computer Science, Microelectronics and Robotics of Montpellier(LIRMM) - University of Montpellier, France

{ Thesis: “Test Techniques for Approximate Digital Circuits”Defense : September 25, 2019 at LIRMM - University of Montpellier

Jury :

Prof Alberto BOSIO École Centrale de Lyon, INL, Lyon Advisor

Dr. Patrick GIRARD CNRS, LIRMM, Montpellier Co-advisor

Prof. Arnaud VIRAZEL Universiy of Montpellier, LIRMM, Montpellier Co-advisor

Prof. Olivier SENTIEYS INRIA, IRISA, Rennes Examiner

Prof. Matteo SONZA REORDA Politecnico di Torino, Italy Examiner

Prof. Lirida NAVINER Telecom ParisTech, Paris Committee president

Summary : Approximate Computing (AxC) is increasingly emerging as a new design paradigmto produce more efficient computing systems by reducing the quality of calcula-tions. In particular, AxC has been successfully applied to integrated circuits inrecent years. As a result, new challenges - as well as new opportunities - haveemerged for the testing of this new class of integrated circuits, namely Approxi-mate Integrated Circuits (AxICs). In this thesis, we provide an in-depth analysisof the issues related to AxIC testing procedures and present innovative techniquesto address them. We use an illustrative example with the twofold purpose ofguiding the reader through the challenges of AxIC testing and illustrating theproposed solutions to overcome them correctly, while taking proper advantageof the opportunities arising from the approximation. We experimentally analyzeall the proposed techniques. The experimental results show the effectiveness ofthe proposed techniques and that their synergy leads to important results. Mythesis work has led to the publication (with proceedings) of two (3) scientificarticles in refereed journals – including a special issue of the journalProceedings of the IEEE –, six (6) scientific articles in proceedings ofinternational conferences, as well as two (2) invited articles in internationalcongresses.

Feb. 2016 –Jul. 2016

Research Intern - Computer EngineeringLIRMM, Montpellier, France

Subject: During this internship, I developed a software tool able to automatically synthesizeany kind of Boolean function to an In-Memory Computing architecture based ona crossbar of memristors. The proposed tool allows an exploration of the designalternatives in order to identify the best implementation conditions in terms ofperformance and area. This work led to the publication (with proceedings) of one(1) article in a international journal and four (4) articles in proceedingsof international conferences. The source code of the tool is available at thefollowing link https://github.com/mtraiola/XbarGen. More information at thefollowing link: www.lirmm.fr/~traiola/xbargen/

Jan. 2014 –Jul. 2016

Master’s Degree in Computer Engineering - summa cum laudeUniversity of Naples “Federico II” (UniNa), ItalyEmbedded Systems curriculum.{ Thesis: “Design space exploration of a Memristor based crossbar architecture”{ Supervisors: A. Bosio (LIRMM/UM), M. Barbareschi and A. Mazzeo (UniNa)

Nov. 2012 –Dec. 2013

Vocational training (Scholarship Holder)“IESWECAN” Project: “Informatics for Embedded SoftWare Engineering forConstruction and Agricultural machiNes” – Naples, Italy

Sept. 2008 –Jun. 2012

Bachelor’s Degree in Computer Engineering - magna cum laudeUniversity of Naples “Federico II” (UniNa), Italy

Sept. 2003 –Jun. 2008

High school: Classical studies (Italian Grade: 100/100)“Liceo Classico Umberto I”, Naples, Italy

Academic Collaborationssince 2019 Collaboration with the team "Electronic CAD & Reliability Group",

Politecnico di Torino (Italy)As part of this collaboration, aspects related to the use of memory encryptionas a fault tolerance mechanism are being studied. In particular, the results ofour experiments have shown that memory encryption is sufficient to significantlyincrease the probability of error detection. This opens the opportunity to avoidthe use of classical and expensive fault tolerance mechanisms. To date, thiscollaboration has led to the publication of one (1) article in the proceedingsof an international conference.

since 2018 Internal collaboration, LIRMMSince the end of 2018, within the LIRMM, I have been involved in work concerningthe study of approximate computing techniques applied to safety-critical systems.In particular, we have first studied the impact of approximation techniqueson fault-tolerant systems; hence, we have developed an approximation-basedapproach suitable for critical systems, which can reduce the cost compared toconventional fault-tolerant solutions. To date, this collaboration has led tothe publication of one (1) article in the proceedings of an internationalconference.

since 2017 Collaboration with the team "TestGroup", Politecnico di Torino(Italy)My collaboration with the TestGroup at the Politecnico di Torino (Italy) focuseson the study of the propagation of the effects of approximate computing tech-niques in complex systems. In particular, we have designed a model based onBayesian networks to predict the accuracy of results, at the application level,when an approximation has been introduced. To date, this collaboration hasresulted in the publication of two (2) articles, one in a international journaland one in the proceedings of an international conference.

Research-related activitiesArticle reviews Over the past few years, I’ve been asked to review articles for international

journals and conferences.In particular, I’ve reviewed articles for the following journals:{ Transactions on Emerging Topics in Computing published by IEEE{ Micro published by IEEE{ Journal of Electronic Testing Theory and Applications (JETTA) published by

Springer{ Electronics published by Multidisciplinary Digital Publishing Institute (MDPI).{ Journal of Low Power Electronics (JOLPE) published by American Scientific{ Journal of Circuits, Systems and Computers (JCSC) published by World

Scientific.

I’ve reviewed articles for the following conferences:{ VLSI Test Symposium (VTS), proceedings published by IEEE{ International NEWCAS conference, proceedings published by IEEE{ Applications in Electronics Pervading Industry, Environment and Society (Ap-

plePies), proceedings published by Springer

ConferenceOrganizingCommittees

Since 2017, I have been invited to participate in various conference organizingcommittees.{ Web chair - IEEE Design & Technology of Integrated Systems in Nanoscale

Era (DTIS), 2018 - http://www.lirmm.fr/dtis18/{ Web chair - IEEE International Symposium on Design and Diagnostics of

Electronic Circuits and Systems (DDECS), 2019 - http://www.lirmm.fr/ddecs2019/

{ Web chair - IEEE Design & Technology of Integrated Systems in NanoscaleEra (DTIS), 2020 - http://www.lirmm.fr/dtis2020/

{ Local arrangement chair - IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), 2020 - http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts20/

{ Web chair - IEEE Design & Technology of Integrated Systems in NanoscaleEra (DTIS), 2021

ProgramCommittees

Since 2020, I have serve as programm committee of the following confer-ences/workshops:{ AxC: Workshop on Approximate Computing

Invited talks I was invited to deliver the following talks:{ "Toward Approximation-Based Modular Redundancy for the Relia-

bility of Integrated Systems"M. TraiolaAxC’20 : 5th Workshop on Approximate Computing @ DAC 2020

Scientificdissemination

I have presented the results of my work on several occasions. In particular, Ihave presented my work in the form of oral and poster exhibitions at severalconferences and workshops and I have also given interactive demonstrations.

Teaching2019-2020 Student co-supervision

École Centrale de Lyon, France

{ Master’s student internship co-supervision (Embedded Systems curriculum).Subject: design of hardware accelerators for Neural Networks with FPGAtechnology

{ Ph.D. student co-supervision.Subject: reducing Deep Learning implementation cost to design high energy-efficient accelerators.

2018-2019 Teaching assistantUniversity of Montpellier, France

{ Computer Architectures - Programming module (ARM cortex M4 architectureand assembly programming) - lectures and laboratories

{ C Programming - laboratories

2017-2018 Teaching assistantUniversity of Montpellier, France

{ Computer Architectures - Programming module (ARM cortex M4 architectureand assembly programming) - laboratories

{ C Programming - laboratories{ Object oriented Programming (C++) - laboratories

Mainactivities:

Preparation of lectures to lead students through the understanding of the subjects.Preparation of laboratory slides for the students to guide them in the developmentof the exercises. http://www.lirmm.fr/~traiola/#teachingDuring the years of my thesis, I was also co-supervisor of two Master’s levelstudents during their internship at the LIRMM. In particular, I was co-supervisorof a student in Computer Engineering at the University of Naples "FedericoII" (Italy), during his final internship at LIRMM. The results of his work ledto the publication of an article in the proceedings of a congress with areading committee, in 2018. I was invited to participate in the jury of his "LaureaMagistrale" as co-advisor, at the University of Naples in January 2018.

Professional Experience in IndustryOct. 2019 –Jan. 2020

R&D Engineer - InternshipMediaTek USA Inc. (Woburn) – Boston Area, United States of AmericaMission: designing and implementing a simulation framework to enable the analysis oflossy data compression in firmware running on several Mediatek DSPs.

Jun. 2013 –Nov. 2013

InternFIAT ITEM SPA - Training on the Job (IESWECAN) – Naples, ItalyMission: critical issues identification and analysis in FIAT ITEM embedded softwaredesign and test phases. Software solution design and development.

Technical skillsSW prog lang C/C++, Python, Java, Shell Scripting, Javascript, PHPAssembly lang ARM Cortex-M, Motorola 68k, MIPSHW desc lang VHDL, VerilogMarkup lang LATEX, HTML, XML

RTOS FreeRTOS, RTAIOSs Linux, Windows, Mac OSX, Android, iOS

DBMSs MySQL, Oracle, MongoDB

ToolsSynthesis and

SimulationXilinx Vivado/ISE, Mentor Graphics Modelsim, Synopsys Design Com-piler/Tetramax

Scientific Matlab/Simulink, ABC and SIS (synthesis/optimization circuits by Berkley)IDE Eclipse, Android Studio

Others Git, Subversion (SVN), Doxygen, MS Office, Internet Browsers

LanguagesEnglish : Fluent French : Fluent Italian : Native

Free Time

Sports I’ve been practicing Aikido, a Japanese martial art, since September 2008. I achievedthe 1st Dan black belt in June 2014. I also like practicing yoga, soccer, volley.

Travelling I love traveling around the world both for working and pleasure.

Publication listMarcello Traiola, Ph.D.

B marcellotraiola@gmail.com® http://www.lirmm.fr/~traiola

°marcellotraiola

Last update on 06/24/2020

The table below provides an overview by year of my different types of publications: scientific journals(indexed JCR), invited journals with peer review (indexed JCR), conferences with proceedings(classified by rank according to the classification established by the French Research Group GdR-SOC2), invited conferences and workshops without proceedings.

Type of Document 2016 2017 2018 2019 2020 Total

Scientific Journal (JCR) 2 2 4Invited Scientific Journal 1 1Conference Proceedings Rank A+ 1 1

Rank A 1 1 2Rank B 1 3 3 7Not classified 1 1 1 3

Invited conference article 1 1 2Workshops 1 7 6 1 2 17Total 2 11 14 3 7 37

International Journals (JCR)[RE1] “Estimating dynamic power consumption for memristor-based CiM

architecture”M. Traiola, M. Barbareschi, A. BosioMicroelectronics Reliability, Volume 80, pp 241-248Elsevier, 0026-2714, January 2018DOI : 10.1016/j.microrel.2017.12.009

[RE2] "Test and Reliability in Approximate Computing”L. Anghel, M. Benabdenbi, A. Bosio, M. Traiola, E.I. Vatajelu (alphabetic)Journal of Electronic Testing Theory and Applications, Volume 34, Issue 4, pp375–387Springer US, ISNN 0923-8174, August 2018DOI : 10.1007/s10836-018-5734-9

[RE3] "A Test Pattern Generation Technique for Approximate Circuits Basedon an ILP-Formulated Pattern Selection Procedure"M. Traiola, A. Virazel, P. Girard, M. Barbareschi, A. BosioIEEE Transactions on Nanotechnology, Volume 18, pp 849-857IEEE Computer Society Press, ISSN 1536-125X, June 2019DOI : 10.1109/TNANO.2019.2923040

[RE4] "Probabilistic estimation of the application-level impact of precisionscaling in approximate computing applications"M. Traiola, A. Savino, S. Di CarloMicroelectronics Reliability, Volume 102, pp 241-248Elsevier, 0026-2714, November 2019DOI : 10.1016/j.microrel.2019.06.002

Invited International Journals with Peer Review[RI1] "A Survey of Testing Techniques for Approximate Integrated Circuits"

M. Traiola, A. Virazel, P. Girard, M. Barbareschi, A. BosioProceedings of the IEEE, special issue “Approximate Computing”IEEE Computer Society Press, ISSN 1558-2256, 2020DOI : 10.1109/JPROC.2020.2999613.

International Conference Proceedings[CO1] "XbarGen: A memristor based boolean logic synthesis tool"

M. Traiola, M. Barbareschi, A. Mazzeo, A. BosioVLSI-SoC 2016 : IFIP/IEEE International Conference on Very Large ScaleIntegration,Tallinn, Estonia, 26-28 September, 2016Actes publiés par IEEE Computer Society Press, ISSN: 2324-8440DOI : 10.1109/VLSI-SoC.2016.7753567

[CO2] "Memristive devices: Technology, design automation and computingfrontiers,"M. Barbareschi, A. Bosio, H. A. Du Nguyen, S. Hamdioui, M. Traiola and E. I.Vatajelu (alphabetic)DTIS 2017 : 12th International Conference on Design & Technology of IntegratedSystems In Nanoscale Era,Palma de Mallorca, Spain, 4-6 April 2017Actes publiés par IEEE Computer Society Press, ISBN: 978-1-5090-6377-2DOI : 10.1109/DTIS.2017.7930178

[CO3] "Formal Design Space Exploration for memristor-based crossbar ar-chitecture"M. Traiola, M. Barbareschi, A. BosioDDECS’2017 : International Symposium on Design and Diagnostics of ElectronicCircuits Systems, Dresden, Germany, 19-21 April 2017Actes publiés par IEEE Computer Society Press, ISSN 2473-2117DOI : 10.1109/DDECS.2017.7934557

[CO4] "Towards Approximation during Test of Integrated Circuits"I. Wali, M. Traiola, A. Virazel, P. Girard, M. Barbareschi, A. Bosio,DDECS’2017 : International Symposium on Design and Diagnostics of ElectronicCircuits Systems, Dresden, Germany, 19-21 April 2017Actes publiés par IEEE Computer Society Press, ISSN 2473-2117DOI : 10.1109/DDECS.2017.7934574

[CO5] "Towards digital circuit approximation by exploiting fault simulation"M. Traiola, A. Virazel, P. Girard, M. Barbareschi, A. Bosio,EWDTS’2017 : East-West Design & Test SymposiumDresden, Germany, 29 September - 2 October 2017Actes publiés par IEEE Computer Society Press, ISBN 978-1-5386-3299-4DOI : 10.1109/EWDTS.2017.8110108

[CO6] "Testing approximate digital circuits: Challenges and opportunities"M. Traiola, A. Virazel, P. Girard, M. Barbareschi, A. BosioLATS’2018 : Latin American Test Symposium,Sao Paulo, Brazil, 12-14 March 2018Actes publiés par IEEE Computer Society Press, ISBN 978-1-5386-1472-3DOI : 10.1109/LATW.2018.8349681

[CO7] "Synthesis of Finite State Machines on Memristor Crossbars"U. Ferrandino, M. Traiola, M. Barbareschi, A. Mazzeo, P. Fiser, A. BosioDDECS 2018 : International Symposium on Design and Diagnostics of ElectronicCircuits Systems, Budapest, Hungary, 25-27 April 2018Actes publiés par IEEE Computer Society Press, ISBN 2473-2117DOI : 10.1109/DDECS.2018.000-3

[CO8] "On the Comparison of Different ATPG Approaches for ApproximateIntegrated Circuits"M. Traiola, A. Virazel, P. Girard, M. Barbareschi, A. BosioDDECS 2018 : International Symposium on Design and Diagnostics of ElectronicCircuits Systems, Budapest, Hungary, 25-27 April 2018Actes publiés par IEEE Computer Society Press, ISBN 2473-2117DOI : 10.1109/DDECS.2018.00022

[CO9] "Predicting the Impact of Functional Approximation: fromComponent- to Application-Level"M. Traiola, A. Savino, M. Barbareschi, S. D. Carlo, A. BosioIOLTS 2018 : IEEE 24th International Symposium on On-Line Testing AndRobust System Design, Platja d’Aro, Spain, 2-4 July 2018Actes publiés par IEEE Computer Society Press, ISSN 1942-9401DOI : 10.1109/IOLTS.2018.8474072

[CO10] "Investigation of Mean-Error Metrics for Testing Approximate Inte-grated Circuits"M. Traiola, A. Virazel, P. Girard, M. Barbarcschi, A. BosioDFTS 2018 : IEEE International Symposium on Defect and Fault Tolerance inVLSI and Nanotechnology Systems,Chicago, IL, USA, 8-10 October 2018Actes publiés par IEEE Computer Society Press, ISSN 2377-7966DOI : 10.1109/DFT.2018.8602939

[CO11] "Maximizing Yield for Approximate Integrated Circuits"M. Traiola, A. Virazel, P. Girard, M. Barbarcschi, A. BosioDATE 2020 : Design, Automation & Test in Europe Conference & Exhibition,Grenoble, France, 9-13 March 2020Actes publiés par IEEE Computer Society Press, ISSN 1558-1101DOI : 10.23919/DATE48585.2020.9116341

[CO12] "Evaluating the Code Encryption Effects on Memory Fault Resilience"R.Cantoro, N. I. Deligiannis, M. Sonza Reorda, M.Traiola, E. Valea (alphabetic)LATS 2020 : IEEE Latin-American Test SymposiumJatiúca (Maceió), Brazil, 30 March – 2 April 2020Actes publiés par IEEE Computer Society Press, ISSN 2373-0862DOI : 10.1109/LATS49555.2020.9093670

[CO13] "QAMR: an Approximation-Based Fully Reliable TMR Alternative forArea Overhead Reduction"B. Deveautour, M. Traiola, A. Virazel, P. GirardETS 2020 : IEEE European Test SymposiumTallinn, Estonia, 25-29 May 2020Actes publiés par IEEE Computer Society PressDOI : T.B.A.

Invited International Conference[CI1] "Special session: How approximate computing impacts verification,

test and reliability"L. Sekanina, Z. Vasicek, A. Bosio, M. Traiola, P. Rech, D. Oliveria, F. Fernandes,S. Di CarloVTS’2018 : VLSI Test Symposium,San Francisco, California, USA - 22-25 April 2018Actes publiés par IEEE Computer Society Press, ISSN: 2375-1053DOI : 10.1109/VTS.2018.8368628

[CI2] "Embedded Tutorial: Design, Verification, Test and In-Field Implica-tions of Approximate Computing Systems"A. Bosio, S. Di Carlo, P. Girard, E. Sanchez, A. Savino, L. Sekanina, M. Traiola,Z. Vasicek, A. Virazel (alphabetic)ETS 2020 : IEEE European Test SymposiumTallinn, Estonia, 25-29 May 2020Actes publiés par IEEE Computer Society PressDOI : T.B.A.

Workshops[DR1] "XbarGen: A memristor based boolean logic synthesis tool"

M. Traiola, M. Barbareschi, A. Mazzeo, A. BosioJournées de la section électronique du Club EEA: "Mémoires émergentes etMemristors pour le stockage & traitement de l’information"Marseille, France, 3-4 November 2016

[DR2] “Formal Design Space Exploration for Memristor-based Crossbar Ar-chitecture”M. Traiola, A. Bosio, M. BarbareschimDAC’17 : Memristor Technology, Design, Automation and Computing @HiPEAC 2017,Stockolm, Sweden, 23 January 2017

[DR3] "Can we Approximate the Test of Integrated Circuits?"I. Wali, M. Traiola, A. Virazel, P. Girard, M. Barbareschi, A. BosioWAPCO ’17 : 3rd Workshop On Approximate Computing @ HiPEAC 2017,Stockolm, Sweden, 25 January 2017

[DR4] "Test of Approximate Circuits"M. Traiola, A. Virazel, P. Girard, A. BosioSETS’2017: South European Test Seminar,France, 20-24 March 2017

[DR5] “XbarGen: a Tool for Design Space Exploration of Memristor BasedCrossbar Architectures”M. Traiola, M. Barbareschi, A. BosioDATE 2017 University BoothLausanne, Switzerland, 28-30 March 2017

[DR6] "A Case Study on the Approximate Test of Integrated Circuits"M. Traiola, A. Virazel, A. Bosio, P. GirardGDR SOC-SoC2’17: Colloque GDR SoC-SoC2,Bordeaux, France, 14-16 June 2017

[DR7] "Formal Design Space Exploration for Memristor-based Crossbar Ar-chitecture"M. Traiola, M. Barbareschi, A. BosioPESW 2017 : The 5th Prague Embedded Systems WorkshopPrague, Czech Republic, 29-30 June 2017

[DR8] "Formal Design Space Exploration for Memristor-based Crossbar Ar-chitecture"M. TraiolaNVM’2017 : Leading-Edge E-NVM Workshop, “Device and Architecture” SessionGardanne, France, 25-27 September 2017

[DR9] "Testing Integrated Circuits for Approximate Computing Applica-tions?"M. Traiola, A. Virazel, P. Girard, M. Barbareschi, A. BosioWAPCO’18: 4th Workshop On Approximate Computing @ HiPEAC 2018,Manchester, United Kingdom, 22 January 2018

[DR10] "Synthesis of Finite State Machine on Memristor Crossbars”U. Ferrandino, M. Traiola, M. Barbareschi, A. Mazzeo, A. BosiomDAC’18 : Memristor Technology, Design, Automation and Computing @HiPEAC 2018,Manchester, United Kingdom, 24 January 2018

[DR11] “IIDEAA: Design Space Exploration for Functional-Level Approxima-tion”M. Traiola, M. Barbareschi, A. BosioDATE 2018 University BoothDresde, Germany, 20-22 March 2017

[DR12] "On the Testing of Approximate Integrated Circuits for Embeddedapplications considering Average-Error Metrics"M. Traiola, A. Virazel, P. Girard, M. Barbareschi, A. BosioAxC’2018 : AxC Workshop @ ETS 2018,Bremen, Germany, 31 May - 1 June 2018

[DR13] "A low-cost approach for determining the impact of Functional Ap-proximation"M. Traiola, A. Savino, S. Di CarloAxC’2018 : AxC Workshop @ ETS 2018,Bremen, Germany, 31 May - 1 June 2018

[DR14] "Automatic Test Pattern Generation for Approximate Integrated Cir-cuits"M. Traiola, A. Virazel, P. Girard, A. BosioGDR SOC-SoC2’18: Colloque GDR SoC-SoC18,Paris, France, 13-15 June 2018

[DR15] "Test Techniques for Approximate Integrated Circuits"M. Traiola, A. Virazel, P. Girard, A. BosioGDR SOC-SoC2’19: Colloque GDR SoC-SoC19,Montpellier, France, 19-21 June 2019

[DR16] "A Novel Test Flow for Approximate Digital Circuits"M. TraiolaPhD Forum @ DATE 2020,Grenoble, France, 9-13 March 2020

[DR17] Invited talk: "Toward Approximation-Based Modular Redundancy forthe Reliability of Integrated Systems"M. TraiolaAxC’2020 : AxC Workshop @ DAC 2020,July 2020