maroc test setup...maroc sum test board modify maroc asic board to add sum 5 sum of 64 with 1.5kohm...

MaPMT MAROC Sum and Simple Sum board test and planning

Zhiwen Zhao

Drew Smith

Benjamin Raydo

Jack Mckisson

2020/08/07

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SoLID Cherenkov beam test in HallCMaPMT maroc sum readout setup

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15 MaMPTs

5 adapter boards 5 asic boards 5 sum boards 5 FPGA boards

1 SSP in VXS crate5 fadc boards in VXS crate

• we use 3-PMT maroc boards only, so 15 MaPMTs are read out and 1 corner MaPMTwon’t

• 5 sets of board for beam test, 2 sets for desktop test and spare, total 7 sets

5 I-PEX cable

I-PEX to BNC converter

75 BNC cable

2 4-in-1 optical cable

5 HV powersupply (-1kV) 5 LV powersupply (+5V)

5 special SHV cable 5 special cable

SoLID Cherenkov beam test in HallCMaPMT simple sum readout setup

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16 MaMPTs

1 big simple sum board

5 fadc boards in VXS crate

• 1 big board for beam test, 1 big board as spare, Total 2 big boards?

• a few small boards for desktop test

80 BNC cable

16 HV powersupply (-1kV)

16 LV powersupply (+5V,0,-5V)

16 SHV cable

16 special cable

MAROC Sum Test Setup

HV

LV

Optical Fiber

• Ben connected sum of 8, then sum of 64, to fadc

• Put the modified maroc board behind the top left rack of the CLAS12 RICH test stand

• fadc and maroc daq share the same trigger (~1kHz) from FPGA board synced laser and controlled by computer

• fadc and maroc daq are taking data with laser at the same time and can be matched event by event if no deadtime

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Maroc sum test boardModify maroc asic board to add sum

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Sum of 64 with 1.5kohm for each sum of 8 and 0.5x onboard amp(sum8 has connection issue, actually sum of 56 is working)

• MaPMT pixel signal ~2ns wide, SoLID Cerenkov photons are within 10ns (3m)

• Low impendence would have saturation at ~25mV for sum of 8 with fast signal < 10ns

• add high impedance and amplifier on board to avoid saturation

fadc signal shape

Sum of 56 (run 257)

• ~12ns rise time and ~32ns full width

100k event

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• Enable any sum in FPGA by software “TRich_Frontend.cpp”• Laser power 20%, wheel 1

• ~50% chance has 1 p.e. in 1 pixel per event• Average 28 p.e. in sum of 56 signal

• HV 0.8kV (~0.25e6 gain), maroc DAC 64 (1x gain), ~0.5x onboard amp

1 event

Sum of 1, pixel=60 (run 258)

• Wires pick up some noise from the switching power supply on maroc asic board

• It would be much cleaner if using sum board

fadc signal

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Sum of 1, pixel=60 (run 258)

fadc signalSum of 56 (run 291)

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maroc sum VS offline sum

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maroc sum VS offline sum

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Sum of 56 (run 291)

Average 28 p.e. in sum of 56 signalAt least 40 p.e. in 40 pixels

1 pixel is fired when maroc adc > pedestalSo at least 1 p.e. is in that pixel

Input and output charge linearity

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0

0.5

1

1.5

2

2.5

3

3.5

0 2000 4000 6000 8000 10000 12000SU

M P

uls

e In

tegr

al (

nV

*s)

Injected Charge (fC)

Corrected (fC), Corrected (nV*s) and Corrected (nV*s)

1Mohm Corrected (nV*s)

50ohm Corrected (nV*s)

Sum of 56 (run 291)

Sum of 8, linearity

3500/(56/8)=500fC

Suppose sum of 64 has max 80 p.e. and 500fC is for at least 40 p.e.1000fC for 80 p.e. is still in the linear region

958fC injected

Maroc sum board produced 2020/02

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• 3 chip board• Modify maroc asic board to add sum• Make new sum board output 4 quad and 1 total sum by IPEX

connector• Make IPEX connector to BNC conversion board• no change to adaptor or FPGA board

result

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run 645

run 694

offline sum of 4 quad match total sum signal

use HV=800V, gain 0.375x to avoid nonlinearityNeed to determine the absolute charge whennonlinearity happens

run 692

gain 0.375x gain 0.5x

Simple Sum Test Setup

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1. Exactly same test setup like maroc sum2. laser light has a probability of 0.5 to have 1 p.e. in one pixel per event. so on average, there are 32 p.e with a very wide distribution per event. 3. all 6 channels in fadc have 0.5V range

Simple Sum Test Setup

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LV +5,0,-5V 12mA quiescent current1 to 5 pC per pulse, small even at high rate

Total 6 output include 4 quad, last dynode, sum644 quad and dynode each has 10x Amp (AD8012)Sum64 has 1x Amp (AD8012)Sum64 and dynode have positive signal, 4 quad have negative signal

fadc signal shape

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(run 432)

Running condition HV 0.8kV, gain ~2.5e5 according to spec sheet

1 event 100k event

fadc signal

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(run 432)

fadc integral sum over the entire range of ringing

Compare peak^2/sigma^2 of fadc integral

• 4911^2/913^2=29 for maroc sum56 (run 300)

• 1951^2/377^2=27 for simple sum64 (run 432)Quad sum and sum64 match well

Quad1 and sum64 match well

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Pixel 1, quad 1 (run 434)Leave only 1 pixel open to take data (HV=1kV)


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Quad sum and sum64 match well

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Quad sum and sum64 match well

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Big Simple Sum board• 16 slots sharing LV input. There are 3 independent LV input connectors

• Initially each slot is a clone of small test board design, but we see large ringing again and Jack needs to tweak the same resistor and capacitors which fixed the ringing on the small test board. So somehow the two boards need slightly different design.

result

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A lot of light A little light with visible pedestal(run 567) (run 582)

offline sum of 4 quad match total sum signal

Readout channel count

• for maroc with sum (15 PMTs with 3-PMT boards)1. 15 fadc ch=1 fadc board, if only total sum of 642. 15+15*8=135 fadc ch=9 fadc board, if adding 8 of sum 8 in output

3. 15+15*4=75 fadc ch=5 fadc board, if adding 4 of sum 16 in output

• for simple sum (16 PMTs)1. 16 fadc ch=1 fadc board, if only total sum of 642. 16+16*4=80 fadc ch=5 fadc board, if adding 4 of sum 16 in output

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backup

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SoLID Cherenkov beam test in HallCMaPMT maroc sum readout component list

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"MAROC with sum output“ with budget $41,700

When to get quote Who get quote comment

adapter board Late Dec INFN Ferrara After design finish at INFN Ferrara

maroc asic board late Dec INFN Ferrara After design finish at INFN Ferrara

maroc sum board late Dec INFN Ferrara After design finish at INFN Ferrara

maroc chips $10326 Zhiwen Zhao

I-PEX to BNC converter Early Jan Jeff Willson and Zhiwen After design finish at jlabelectronic group

FPGA board $8513, 19 days lead time Chris Cuevas and Zhiwen


“Cabling and misc. for MAROC readout” with budget $5,000

Dec Ben Raydo and Zhiwen

"Feed-through adapter for MAROC readout” with budget $1,000

Jan Gary Swift and Zhiwen After design finish at Duke

HV and LV powersupply with budget $20,000

Dec Alexandre Camsonne and Zhiwen

SoLID Cherenkov beam test in HallCMaPMT simple sum readout component list

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Simple sum board with budget$2000

Jack McKisson and Michael Paolone

After design finish at jlabdetector group early Dec

“Cabling and misc.” with budget $1,000

Jack McKisson and Michael Paolone

After design finish at jlabdetector group early Dec

"Feed-through adapter” with budget $1,000

Edward Kaczanowicz and Michael Paolone

After design finish at Temple

fadc signal shape

Sum of 1, pixel 60 (run 207) Sum of 8 (run 200)

• ~12ns rise time and ~32ns full width• Somehow there is a 12ns shift for baseline, we

can reduce the effect by doing integral over a multiple of 3 time windows

1 event

100k event

• Enable sum of 1, 2,3, … 8 in FPGA by software “TRich_Frontend.cpp”• Laser power 20%, wheel 1

• ~50% chance has 1 p.e. in 1 pixel per event• Average 6 p.e. in sum of 8 signal

• HV 1kV (~1.5e6 gain), maroc DAC 8 (0.125x gain), ~10x amp by NIM

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fadc signal Sum of 8 (run 200)

pedestal

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sum of 8 7 6 5 4 3 2 1

Integral mean

2823 2493 2135 1819 1531 642 714 678

Integral 1161 1121 1094 1038 1022 548 388 340

Compare fadc and maroc signal Sum of 8 (run 200)

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Compare event by event

• The 2D plot shows linear relation hold until ~3000 fadc integral where its peak is

• The right plots show the most events have 4 p.e. in sum of 8, which is consistent with ~50% chance has 1 p.e. in 1 pixel per event observed in sum of 1 plot where pedestal and signal have same area

fadc signal shape

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(run 367)

Running condition HV 0.8kV, gain ~2.5e5 according to spec sheet

1 event 100k event

fadc signal

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(run 367)

fadc integral sum over the entire range of ringing

Compare peak^2/sigma^2 of fadc integral

• 4911^2/913^2=29 for maroc sum56 (run 300)

• 1577^2/315^2=25 for simple sum64 (run 367)


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Pixel 32, quad 2 (run 370)Leave only 1 pixel open to take data


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Quad3 > sum64 somehow

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Quad and sum64 are complicated

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Quad and sum64 are complicated

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maroc test setup...maroc sum test board modify maroc asic board to add sum 5 sum of 64 with 1.5kohm...

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