SARDAR VALLABHBHAI PATEL INSTITUTE OF TECHNOLOGY

ElectricalDepartment

TOPIC: MASTER SLAVE JK FLIP FLOP & T FLIP FLOP…

PREPARED BY: NAME EN.NO

Smit shah 96

Flip-Flops• The latch circuits presented thus far are not appropriate

for use in synchronous sequential logic circuits. • The possibility of two cascaded combinational circuits

feeding each other, generating oscillations and unstable transient behavior can be controlled by using a special timing control signal called a clock.

• The clock can then be used to restrict the times at which the states of the memory elements may change thus preventing the unstable behavior just described.

Clock Signal

Sequential logic circuits have memory Output is a function of input and present stateSequential circuits are synchronized by a periodic “clock” signal

Master-Slave JK Flip-Flop

• The output state of a master-slave SR flip-flop is undefined upon returning the control input to 0 when S = R = 1.– Necessary to avoid this condition.

• Master-slave JK flip-flop allows its two information input lines to be simultaneously 1.– Results in toggling the output of the flip flop.

Master-Slave JK Flip-Flop

• Assume in 1-state, C = 0, J = K = 1.– Due to feedback, the output of the J-gate is 0, output of K-gate is 1.– If clock is changed to C = 1 then master is reset.

• Assume in 0-state, C = 0, J = K = 1.– Due to feedback, the output of the J-gate is 1, output of K-gate is 0.– If clock is changed to C = 1 then master is set.

• 1 on J input line, 0 on K input line sets the flip-flop. – If in 1-state, unchanged b/c S,R set to 0.– If in 0-state, S set to 1, R set to 0.

• 0 on J input, 1 on K input line resets the flip-flop. Why?

Master-Slave JK Flip-Flop

Timing Diagram forMaster-Slave JK Flip-Flop

T (toggle) Flip-flop• It’s a complementing flip-flop• It can be made using JK flip-flop or D flip-

flop.• If made using JK flip-flop– Inputs J & K are tied together– T=0, J=K=0, No Change in Q– T=1, J=K=1, Q = Q’

• If made using D flip-flop– Q = D = T XOR Q = TQ’ + T’Q

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