matlab workshop at gauhati university

Proceedings of

National Level Workshop On

MATLAB and Selected Applications

18th to 27th June, 2012

Organized by

Department of Electronics and Communication Engineering

In Association with

RESONICS-Society for Promotion of Education and Research in Electronics and Related Areas

Gauhati University

Guwahati-781014, Assam, India

www.gauhati.ac.in

Proceedings of National Level Workshop on MATLAB and Selected Applications-2012

Published by

Department of Electronics and Communication Engineering, Gauhati University

Editorial Board Editor-in-chief:

Kandarpa Kumar Sarma, HOD i/c, Dept. of ECE, GU

Editors: Manash Pratim Sarma, Asst. Prof., Dept. of ECE, GU Mousmita Sarma, Assistant Project Engineer, Dept. of EEE, IITG

Associate Editors: Anjan Kumar Talukdar, Asst. Prof., Dept. of ECE, GU Krishna Dutta, Guest Faculty, Dept. of ECE, GU Manash Jyoti Bhuyan, Project Associate, Dept. of ECT, GU Parismita Gogoi, Guest Faculty, Dept. of ECE, GU

Advisors: Prof. Kanak Chandra Sarma, Dept. of Instrumentation and USIC

Dr. Tulsi Bezboruah, Associate Prof., Dept. of ECT, GU Mr. Hidam K. Singh, Asst. Prof., Dept. of ECT, GU Nirmala S. R., Asst. Prof., Dept. of ECE, GU Jyoti Prakash Medhi, Asst. Prof., Dept. of ECE, GU Dr. Utpal Sarma, Asst. Prof., Dept. of Instrumentation and USIC, GU

Cover Design Amlan Jyoti Das CopyrightDepartment of Electronics and Communication Engineering, Gauhati University No part of this publication can be reproduced or distributed in any form or by any means, or stored in database or retrieval system without prior written consent from Department of Electronics and Communication Engineering, Gauhati University .

ISBN: 978-93-81691-08-3

(The ISBN is managed by K. K. Publication, Bamunimaidam, Guwahati-781021)

Proceedings of National Level Workshop on Matlab and Selected Applications, Gauhati University, Guwahati- 781014, 18-27th June, 2012. Printed at by K. K. Graphics, Bamunimaidam, Guwahati-781021, Assam, India. CopyrightDepartment of Electronics and Communication Engineering, Gauhati University


FORWARDING FROM VICE CHANCELLOR

Prof. Okhil Kumar Medhi

Vice Chancellor

GAUHATI UNIVERSITY GUWAHATI-781014 website: gauhati.ac.in

Ph.No: +91-361-2570412(O) Fax: +91-361-2700311 (O)

I am happy to know that a proceeding is to be published as part of the 10-day National Level Workshop on MATLAB and Selected Applications. The contents of the proceedings have been included after

review and are likely to provide a ready reference to the participants later.

MATLAB is the most popular tool for validation, verification and visualization used by students, researchers and designers of Electronics

and Related areas world over. In this context, a workshop exclusively dedicated for providing hands-on skills to participants on MATLAB and

selected applications shall go a long way in helping the participants to develop know-how and skills in specific areas.

I wish all the best to the organizers for holding the event and hope that it will pass off smoothly.

Prof. O.K.Medhi

12-06-2012


FORWARDING FROM DEAN, FACULTY OF TECHNOLOGY

Prof. Pranayee Datta Dean, Faculty of Technology

GAUHATI UNIVERSITY GUWAHATI-781014 website:

gauhati.ac.in

The Department of Electronics and Communication Engineering, one of the significant components of the Faculty of

Technology, GU, is coming up with a mission to promote

education and research in the field of electronics in the NE region. The department established in the year 2009 has been

conducting B.Tech and M.Tech programmes with an aim to enrich our region with qualified manpower having technical background.

Basically, the subject Electronics has two flavours one is science aspect and the other is technology aspect. Hence, studies in electronics must proceed in the path from concept to reality.

So, it is the responsibility of this newly established department to initiate the process.

Im quite sure that the workshop entitled National Level Workshop on MATLAB and Selected Applications is following that path. This is the beautiful beginning and there is Miles to go. My best wishes are there and will be always with each and everybody associated with this mission.

Prof. P. Datta


PREFACE

The 1st National Level Workshop on MATLAB and Selected Applications

organized by the Department of Electronics and Communication Engineering,

Gauhati University and RESONICS- the Society for Promotion of Education and

Research in Electronics and Related Areas is intended to provide hands-on

exposure about MATLAB to the participants. Over the years, MATLAB has

emerged as the most preferred tool of validation, visualization and verification

used by students, researchers, designers and application developers world

over. This is because of the fact that MATLAB is driven philosophically by the

fact that a picture speaks a thousand words.

This workshop is arranged with the objective that it will provide

organized know-how o participants on a diverse range of topics in which

MATALB can be applied. Starting with the basic concepts and rudimentary

familiarization, the programme intends to provide in-depth know-how on

applications of MATLAB in selected areas of Mathematics, Signals and

Systems, Communication System, Control System, Digital Signal Processing,

Image Processing, Bio-medical Signal processing, Soft-computation and Multi-

media applications. With in-house resource persons and managed from nearby

institutes, the programme is designed to be conducted in two distinct modes-

theory and practical sessions. Equal importance given to both theory and

practical sessions reflect the fact that both these two levels of know-how is

essential for application of MATLAB.

A workshop proceedings is prepared by compiling invited write-ups

from resource persons and certain scholars of repute. The content of the

proceedings has been reviewed and organized in such a manner that it will

serve as a ready reference of MATLAB to the participants while they use the

know-how acquired for some specific applications of their concern.

The organizers are thankful to the Gauhati University authorities for

extending cooperation of all forms in making the event successful. Our

honable Vice Chancellor Prof. O. K. Medhi has been a source of constant support to us. Special thanks should go to Dr. J. Dutta, Academic Registrar,

Gauhati University for his support while organizing the event. Prof. (Mrs)

Pranayee Datta, Dean, Faculty of Technology and Director i/c, Institute of

Science and Technology, GU also has been a source of inspiration to us and

have contributed significantly in making the event possible. Special thanks

goes to all members of the department of ECE, GU, IST and members of

RESONICS. Their active cooperation and participation have helped

considerably in making the event possible.

The undersigned, on behalf of the organizing committee and RESONICS

specially thank M/s K. K. Graphics, Bamunimaidam, Guwahati for readily

agreeing to print the proceedings volume within a very short notice.

Kandarpa Kumar Sarma

Date:12th June,2012, Guwahati


CONTENTS SECTION 1: Invited Papers

1 Frequency to Voltage Converter Circuits for Sensor Interface.

Hidam Kumarjit Singh, Adit Kumar Singha,

Hari Prosad Nath, T.Bezboruah

2 Investigations on database transaction summary of interactive

web application based on Java technique.

M. Kalita and T. Bezboruah

Coding and Its Application in Communication. Parismita Gogoi

4 Studies on some aspects of frequency/phase locking

phenomenon in communication systems.

J. Handique and T. Bezboruah

SECTION 2: Workshop Contents

1 Basics of MATLAB and Familiarization Mousmita Sarma

2 Programming in MATLAB Krishna Dutta

MATLAB and SIMULINK Parismita Gogoi

4 MATLAB support for Mathematics Toolboxes and

Programming Techniques: A brief review

Manas Dutta

5 Signals-Systems and Digital Signal Processing using MATLAB Manash Pratim Sarma

6 Simulation of Communication Systems using MATLAB Manasjyoti Bhuyan

7 Control System Engineering using MATLAB Anjan Kumar Talukdar

8 Digital Image Processing using MATLAB Jyoti Prakash Medhi

9 Biomedical Signal and Image Processing using MATLAB S.R. Nirmala

10 Soft-Computation and Related Applications using MATLAB

with Special Stress on Artificial Neural Networks and

Fuzzy Systems.

Kandarpa Kumar Sarma


SECTION 1: Invited Papers

.

1

National Level Workshop on MATLAB and Selected Applications-2012

FREQUENCY TO VOLTAGE CONVERTER CIRCUITS FOR

SENSOR INTERFACE

Hidam Kumarjit Singh, Adit Kumar Singha, Hari Prosad Nath, T.Bezboruah Department of Electronics and Communication Technology, Gauhati University, Guwahati-14, Assam, India Email: [email protected]

Abstract - Design of innovative circuits to convert frequency variation into proportional voltage is presented in this paper. The design methodology of the proposed system is based on digital frequency counter and digital to analog conversion processes. Two prototype circuits of the proposed technique has been designed, and tested. The frequencies to voltage converter circuits are found to work satisfactorily with a large conversion range that can be further extended to a few Megahertz of input signal frequency. The propose design methodology shows the feasibility of having trade-off between sensitivity and conversion range depending on the requirement. These circuits will have numerous applications in sensor instrumentation and telemetry system.

Key words: Analog, conversion, digital, frequency, instrumentation, and sensor.

1.1. INTRODUCTION

Frequency to voltage converter (FVC) circuits finds their applications in electronic sensor interfacing circuits, where the frequency of a sensing oscillator circuit is required to be converted into proportional DC voltage. In the recent times, several techniques to design frequency to voltage conversions circuit have been reported, as in [1]-[5]. FVC circuit is basically designed by allowing a capacitor to be charged and discharged in response to a time varying pulse, as in [1] and [4]. But, this technique has disadvantages of having significant ripples in the output DC voltage at low frequency. In the reported technique of [2], a differentiator, an integrator, a linear divider, and a square rooter circuits are used to design a FVC. These above techniques are characterized by smaller conversion range of about 10-20 KHz, and longer time of conversion, usable only with sinusoidal signals. Another method of FVC design is based on pulse counting technique, as reported in [3]. And, this technique counts the pulse transitions of an input signal over a fixed counting time interval, and the count value is converted into analog signal by using an ADC. But, dynamic range of conversion of [3] varies with the RC time constant of an integrator circuit used in the circuits. As such, we propose the design and implementation of an innovative FVC circuit, based on frequency counting and digital to analog conversion processes but there is neither integrator nor differentiator circuits in the proposed method. Design methodology of this technique avoids the effects of RC time constant on the frequency conversion limit of the FVC that happens in [3].

1.2. DESIGN OF THE PROPOSED FVC CIRCUIT

We use an AND gate to act as control gate of an 8-bit digital counter. One of the input terminals of the control gate is given a control signal of fixed frequency, while the other input

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terminal is given an input signal, whose frequency variation is to be converted into DC voltage. The gated input signal appears at the output of the control gate when the control gate is enabled during high TTL state of the control gate signal, and its low TTL state will reset the control gate and a digital counter. The digital counter gets its clock signal from the output of the control gate. Then, a DAC is used to convert the digital count values into analog signal. The functional block diagram of the circuit is shown in Fig.1. The circuit is designed in such a way to reset the count values of the counter during low TTL state of the control signal. Counter resetting action is required to avoid accumulation of the count value, which will otherwise cause to produce erroneous results. Fig.2 shows the theoretical timing diagram of the signal flow in the control gate and digital counter.

Fig.1 Functional block diagram of the proposed FVC circuit model-1.

Fig.2 Timing diagram showing operation of the control gate and 8-bit digital counter used in the FVC circuit model-1.

The frequency of the control gate signal is selected under the condition that there will be a maximum count value of the counter at the highest frequency of input signal, whereas the lowest frequency of the input signal will produce a minimum count value. For an 8-bit counter, theoretical value of minimum count value is (00000000)

2, while that of maximum count value is (11111111) 2.

3


If TGON is the time duration of control gate signal in high logic state, and TIN is the total time period of input signal then, count values are given by (1) and (2).

)(MININ

GONMAX T

TC (1)

)(MAXIN

GONMIN T

TC (2)

Where, CMAX and CMIN are the maximum and minimum count values respectively. TIN (MAX) and TIN (MIN) are the maximum and minimum time durations of the input signal.

The value of CMAX has to be (255) 10 for an 8-bit counter and this value is used to determine the highest frequency of input signal for a given value of reference signal frequency. As the input signal changes its frequency from minimum to maximum limit, the count value will change in steps from (0)

10 - (255) 10 or (00000000) 2 - (11111111) 2.We use negative edge sensitive Flip-Flops to design an 8-bit asynchronous ripple counter. This counter counts pulse transitions of the control gate output signal during TGON. The counter value will be incremented by one every time there is a negative edge transition in the counter clock signal. From (1) and (2), we have noticed that the change in the value of count value is proportional to the magnitude of TIN when TGON is constant. Finally, we used an 8-bit digital to analog converter (DAC) circuit is used to convert the outputs of the counter to analog voltage. The corresponding analog voltage w.r.t the different input frequency can be measured.

We also used a modified control gate circuit to increase fCR (Frequency Conversion Range) of the above circuit, as in Fig.3. In this case, we use a divide by N counter to act as frequency divider for an input signal of larger frequency. And, the value of N is selected in such a way that the effective input signal of the control gate must satisfy (1) and (2) to get the same values of CMAX and CMIN. So, fCR of the FVC circuit having modified control gate can be expressed as in (3). 00 LHLNHNCR ffNfff (3)

Where, fLN and fHN are the upper and lower limits of conversion range with a divide by N counter, and f L0 and fH0 are the frequency limits when N is unity. For instance, this equation shows the feasibility of converting a FVC circuit having fCR value 500 KHz into another FVC having fCR value 1MHz by using the proposed design methodology. However, the upper frequency limit of the conversion will be limited by the propagation delay of the digital gates and conversion time of the DAC used in the circuit. Fig.4 shows the timing diagram of the circuit given in Fig.3.

Fig.3 FVC circuit model-2 having a divide by 2 counter in the control gate unit.

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Fig.4 Timing diagram showing operation of the control gate and 8-bit digital counter used in the FVC circuit model-2 having a divide by 2 counters.

1.3. EXPERIMENTAL OBSERVATIONS

Experimental observation and functional verification of the proposed circuit models are in two steps. The first step does functional verification of the different building blocks of the FVC circuits. In order to verify functionality of the control gate circuit, counter circuit, and DAC circuit, external test signals are feed into the input of each circuit and corresponding timing diagram of the signals are displayed and examined by using digital oscilloscope. Fig 5 shows the merged timing diagram of the signals of control gate and 8-bit counter of the FVC circuits. Finally, the transfer response of the DAC is determined separately by applying digital inputs manually. Transfer curve of the DAC (DAC0808) is shown in Fig.7.

Fig.5 Merged timing diagram of digital counter used in the FVC circuits

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Secondly, the overall responses of the complete FVC circuits (model-1 and model-2) are studied. In the experimental observations of these two circuits, we use two separate TTL signal generators, out of which one acts as source of input signal, while the other acts as gate signal generator. The gate signal frequency is kept constant at 1 KHz to make TGON equal to 5s, while the input signal is maintained at around 50 KHz. Under this condition, the FVC circuit model-1 is supposed to provide proportional DC signal variation up to input signal frequency of about 500 KHz in accordance with relation (1). Fig.7 shows the corresponding variation DC output voltage with input signal frequency. The response of the FVC begins to have saturation effect at around 500 KHz. Similarly, the same procedure is repeated for the circuit model -2 up to 1500 KHz and 2800 KHz. Saturations effects are also observed after 1 MHz and 2 MHz, as shown in Fig.8 and Fig.9. Further, we have plotted the three response curves of the FVC circuits having different values of maximum conversion frequencies in a single XY palne, as in Fig.10. This graph is drawn in oder to compare the sensitivities of the different FVC circuits used in the present work. We consider only a few experimental data to draw this graph as the linear regions of the response curves must be used while calculating individual values of sensitivity. Here, the sensitivitivy of FVC will be defined as the ratio of change in FVC output voltage to the change in input frequency of the applied signals.

Fig.6 Transfer characteristics of DAC used in the FVC circuit

Fig.7 Frequency versus DC voltage variation curve for FVC circuit model-1. (In this maximum conversion frequency of the circuit is 500KHz.)

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Fig.8 Frequency versus DC voltage variation curve for FVC circuit model-2 when a divide by2 counter is used. (In this maximum conversion frequency of the circuit is 1000 KHz.)

Fig.9 Frequency versus DC voltage variation curve for FVC circuit model-2 when a divide by 4 counter is used. (In this maximum conversion frequency of the circuit is 2000 KHz.)

Fig.10 Combined response curves for FVC circuits having different maximum conversion frequency values.

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1.4. RESULTS AND DISCUSSIONS

This experimental work on the design and implementation of FVC yields satisfactory results, as shown in Fig.7-Fig.9. Characteristic response curves of the proposed FVC circuit models are obtained in agreement with the theoretically expected ones. However, these response curves show slight non-linearity with increasing frequency, and saturation effects beyond a threshold frequency of the input signal. This threshold frequency is the maximum usable frequency of a circuit. The non-linearity of the response at lower frequency can be due to the non-linearity of the DAC used in the present FVC circuit. This is quite evident from the DAC transfer characteristics, shown in Fig.6. Linearizing electronic circuits will be required to correct this non-linearity. The saturation effects occurred because of the fact that digital count value can not be further increased beyond the maximum usable frequency. The saturation effect can be delayed by decreasing TGON of the control gate signal, or it can also be delayed by increasing the number of bits in the digital counter. Further, we have found that frequency conversion range can be extended at the expense of reduction in sensitivity of the proposed FVC circuit. This is clear from Fig.10. In this figure, the response curve of 500 KHz conversion range has the highest sensitivity as it is having the largest slope. The least sensitivity is obtained with response curve of 2000 KHz.

The FVC circuit designed in the present work can be used in instrumentation and measurement system that involves frequency conversions. For instance, a sensing circuit may give its output signal in the form of variation in signal frequency. We can convert the frequency variation into its proportional DC voltage by using such FVC circuit. Future direction and scope of this work will be dealing with the design of an innovative sensor circuit by using the FVC circuits implemented in this work.

1.5. CONCLUSIONS

The present work has designed and implemented innovative frequency to voltage converter circuits that can be used for interfacing frequency varying sensing circuits to other circuits that requires voltage level variation such as amplifiers and analog to digital converters. Novelty of the proposed design technique lies in the ability of the circuit to operate over a large frequency range without having to deal with RC time constants that is normally done in other reported works and literatures[1]-[4].

REFERENCES

[1] R. A. Gayakward (2005). Op-Amps and Linear Integrated Circuits, Prentice Hall, India, New Delhi, pp.336-339.

[2] W.Surakampontorn (1991). An analog Sinusoidal Frequency to Voltage converter, IEEE Transactions on Instrumentation and Measurement, Vol:40, No:6,pp.925-929.

[3] An Sang Hou (2004). Design of Fast Frequency to Voltage Converter using Successive Approximation Technique, Journal of Circuits Systems Signal Processing, Springer Link, Vol.23, No.6, pp.537-550,.

[4] C.Borah, M.Das, H.KSingh (2011). A Novel technique to measure ambient temperature. Paper presented at 56th Annual Technical Session of Assam Science Society (Physical Sciences section), held at Dibrugarh University, Assam, India.

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ADDITIONAL READING SECTION We are not able to find much research papers and other literature except those included in the reference. Readers of this paper, if interested, can read the same included in the reference. But, the following device datasheets can be read so as to know design of FVC circuits in the commercial chips.

[1] Voltage-to-Frequency and Frequency-to-Voltage Converter, from http://focus.ti.com/lit/ds/symlink/vfc32.pdf. [2] LM231A/LM231/LM331A/LM331, Details of operation as F-to-V converter, from http://www.national.com/ds/LM/LM231.pdf.

KEY TERMS & DEFINITIONS

Ripple counter: A digital counter having two or more toggled Flip-Flops that works in such a way that output of a previous clocked Flip-Flop drives the succeeding Flip-Flops to change its logic state. Conversion Range: The range of frequencies encompassing the lower and upper frequency limits of an AC signal that can be converted into proportional voltage. Control gate signal: It is a signal used in the FVC circuit for enabling a AND gate during its high state, and disable the gate and resets a digital counter during its low state. Clock edge transition: The phenomenon in which the logic state of a clock signal changes suddenly from low state to high state or vice versa. The former is known as leading edge transition, while the latter is known as falling edge transition. Frequency to voltage converter (FVC): FVC is a circuit that converts frequency variation of an AC signal into its proportional DC signal levels. This circuit can be a pure analog, digital or a mixed signal electronic circuit. The output of this circuit does not necessarily to be DC signal all the time. If the rate of frequency change in the AC input is appreciably large enough, then the resulting output of FVC will vary rapidly it amplitude with time. If the input to the FVC is frequency modulated signal (FM), the output will be the replica of the modulating message signal. Resolution: The reciprocal of sensitivity gives resolution of a system under test. Resolution is the smallest change of an input parameter that can be detected by the system. In the present work, this term is used to denote the minimum amount of detectable change in frequency of input signal. Sensitivity: For any bounded input and bounded output system, sensitivity is defined as the ratio of the change in system input parameter to the change of system output parameter. In the present work, this term is used to denote DC voltage level change per unit change in frequency.

Brief biography of the author: Hidam Kumarjit Singh is presently Assistant Professor, Department of Electronics and Communication Technology, Gauhati University. His areas of interest include Optoelectronics, Microprocessors, Instrumentation and Control.

Dr. Tulsi Bezbarua is presently Associate Professor, Department of Electronics and Communication Technology, Gauhati University. His areas of interest Microwave Engineering, Signal Processing, Web-based instrumentations.

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INVESTIGATIONS ON DATA ASE TRANSACTION

SUMMARY OF INTERACTIVE WE APPLICATION

ASED ON JAVA TECHNIQUE M. Kalita

1 and T. Bezboruah

2

1,2Depart ent of Electronics Co unication Technolo y, Gauhati University,

Guwahati-781014, Assa , India

ABSTRACT

We proposed to investigate the database transaction summary of interactive web application based on Java technique with the change in number of concurrent users. As such, we developed a prototype research web application based on Java technique. The application executes in an environment that contains a database, implemented with MySQL (Structured Query language) database Server. The application has been tested by deploying it on Mercury LoadRunner to study the feasibility of the proposed investigation. In this paper we have discussed in details the database transaction summary that has been observed during the test.

KEYWORDS: Web, DBMS, SQL.

1.1 INTRODUCTION

The explosive growth of web applications and web services (WS) has changed the present scenario in exchanging the information in government, corporate, educational and research institutes. The productivity and operational efficiencies has been increased to manifold with the development of sophisticated but simple web applications. With such development, the responsibility on the developers side is unlimited. While the applications would be provided with easy to use features, at the same time these applications must also be able to handle large number of concurrent users. In such a situation, as most of the businesses are conducted through web, it is very important and crucial to get the web application be tested and the database transaction summary be monitored in details. It is the software tester who tests and makes the application worth visiting. To perform and execute testing, one should be familiar with the system, the inputs and the way they are combined, and the operating environment of the system [1].

The database is the backbone in the operation of almost every modern organization. Commercially available database management systems (DBMS) provide organizations with efficient access to large amount of data. These kinds of DBMS exempt the user from understanding the low-level details of the storage and retrieval mechanisms. It is essential that these database systems operate correctly and provide acceptable performance [2]. One such commercially available DBMS is MySQL database Server. Database transaction basically reflects the idea of the activities for a particular user, isolated from all concurrent activities. Transaction is a short sequence of interactions with the database using operators such as INSERT, UPDATE, and DELETE that provides one meaningful activity in the users environment. The transaction requires that all its actions are executed individually. Either all the actions are properly reflected in the database or nothing is being happened. To achieve this kind of individuality, four properties must be associated in the transaction. They are: (i) Atomicity, (ii) Consistency, (iii) Isolation and (iv) Durability (ACID) [3]. Atomicity guarantees that the set of

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updates contained in a transaction must succeed or fail as a unit. Consistency means, a transaction will transform a database from one consistent state to another. The isolation property guarantees the partial effects of incomplete transactions which should not be visible to other transactions. Durability means, the effects of committed transactions are permanent. Therefore, transactions can be used to solve problems like creation of inconsistent results, concurrent execution errors and lost of results due to system crash [4].

A database driven application is a set of programs whose environment always contains one or more databases. With the high quality DBMS and increase of applications incorporating in these DBMSs, there is an urgent need for software testing techniques which test an application and its interaction with the database [5].

In view of the above, we have designed, developed, implemented and tested a prototype research web application using Java technique to investigate the database transaction summary. The web application has been developed by using NetBeans (Version: 6.5.1) Integrated Development Environment (IDE). The Apache Tomcat is deployed as web server. The MySQL (Version: 5.0) DBMS is used as a database server. The use of IDE can increase the efficiency during development, as the plug-ins can alert coders if they introduce errors while writing codes [6]. The testing tool Mercury LoadRunner (Version 8.1) is used to test the database driven application. The application has been tested considering different stress levels and the results of database transaction summary and statistical testing are presented in this paper.

1.2 THE SOFTWARE TESTING

The software testing is a process to evaluate the efficiency of a system. In software development, testing is used at key checkpoints in an overall process to determine whether objectives are being met or not. When the design of a web application is completed, coding follows. The code is then tested at the unit or module level by the programmer [7]. One of the best ways to measure an applications quality of service (QoS) is to conduct load testing. After verifying the correctness of the code, the load and stress testing is performed to measure the performance and scalability of the application under heavy load. After analyzing the results obtained during this phase, it is possible to determine the bottlenecks, memory leakage or performance problems and transaction summary related to the database layer (DL).

The load testing is done to have an overall insight of the system. It models the behavior of users in real world. The load generator mimics browser behavior and each emulated browser is called a virtual user [8]. In load testing the system is subjected through reasonable load in terms of number of virtual users to find out the performance of the system. In this case the load is varied from zero to the maximum up to which the system can handle in a decent manner.

The stress testing is performed to determine the stability of a given system. It involves testing beyond the normal operational capacity. The stress testing is performed to uncover memory leakage, bandwidth limits, transactional problems, resource locking, hardware limitations and synchronization problems that occur when an application is loaded beyond the limits determined by the performance statistics [9] [10] [11].

Different testing tools are used to simulate the scenario and to evaluate the performance parameters of the application before it is actually deployed. They create stress on the system by simulating large number of virtual users. They also collect the system performance parameters in the form of various graphs which can be used later to analyze the behavior of the application.

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The testing on our implemented application is carried out to observe the database transaction summary of the combination of Java technology with MySQL database Server under a given workload. The operations performed are INSERTION, UPDATION, DELETION and SEARCH. The testing is object based in the sense that the whole application has been divided into different objects [12].

1.3 THE ARCHITECTURE

The Java language is a natural choice for developing web applications. Its strong security guarantees, concurrency control and wide spread deployment in both browsers and servers make it relatively easy to create web applications. The Java server faces (JSF) is a standard user interface (UI) framework for Java web applications. The JSF follows the Model View Control (MVC) design paradigm. The rapid web application development is promoted by easily assembling UI components, plumbing them to the back end Business Layer (BL) components, and wiring UI generated component events to server-side event handlers. The JSF is a specification for a component based web application framework [13, 14].

1.3.1 The multi-tier architecture of the PReWebN

The web application has been implemented using visual web JSF to act as the front-end interface to dynamic web content generator. The web content generator is a combination of web server software, the Apache Tomcat and back-end MySQL database server. The objective of the experiments is to measure the database transaction summary of the application written in JSF with the MySQL as the database server. The architecture of the web application is shown in fig.1. The JSF provides a component-centric Application Programming Interface (API) from which web application user interfaces can be assembled. The JSF specification defines a set of basic UI components that can be extended to achieve more specialized behavior. The events from client-side UI controls are dispatched to JavaBeans models which provide Server-side application behavior. In JSF, the UI components are loosely coupled to Server-side Java Plain Old Java Objects (POJO) which is declared as managed beans. The front end controller servlet handles all Faces requests and dispatches them with the necessary application data to the appropriate view. The Database manages the physical storage and retrieval of data. It receives the data from the model and sends it to the database and vice versa. The database queries have been written to access the data from the database and to perform operations like insert, update and delete. The MySQL acts as the data layer (DL) in our design.

Figure 1: Architecture of the web application

Creates/

Response

Accesses

Dispatches

Request

The Model consists of

ana ed beans.

The View consists of JSP

pa es.

The Faces Servlet

acts as the Controller STAFF PAPER

INSERTFACULTY.JSP

DATABASE

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1.4 THE DESIGN ASPECT OF THE WEB APPLICATION

The web applications design is essentially its look and feel [15]. We have taken into account of all the web elements e.g. audience information, purpose and objective statement, domain information, web specification and combine them to produce an arrangement for implementing the application.

The application has been developed by considering the profile of the Department of Electronics and Communication Technology (ECT), Gauhati University as the sample data. The Create, Read, Update, Delete (CRUD) operations are performed to generate the response. It is an operation in which data is created, retrieved, updated and deleted according to the user requirement. There are two types of account available for accessing the application. The USER ACCOUNT which is available for the registered users that has limited access to application. The other one is the ADMINISTRATIVE ACCOUNT available for Administrator that has full access to the application. The flowchart for basic working principle is presented elsewhere [16]. The algorithm for developing the web application is given in fig.2.

Step Instruction

1. begin 2. open home page of the application 3. want to login 4. if yes then 5. go to step 12 6. else go to step 7 7. procedure SEARCH 8. do search operation 9. if want more search then 10. go to step 8 11. else go to step 31 12. if ADMIN then 13. process registration 14. update database 15. if more registration then 16. go to step 13 17. else 18. go to step 31 19. else if USER then 20. open menu 21. if operation INSERT then 22. enter login information 23. if successful then 24. update database 25. else go to step 22 26. else if operation MODIFY then 27. repeat steps 22, 23, 24 and 25 28. else if operation DELETE then 29. repeat steps 22, 23, 24 and 25 30. logout 31. end

Figure 2: Algorithm for developing the web application

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1.5 Database Design

Suitable database design is one of the most important factors in successful implementation of any database driven application. We have designed the database, keeping in mind to reduce the database anomalies like redundancy, update anomalies and data inconsistency. For our application, the database connection is provided through the IDE services window. The disconnected RowSet object is used for the database transactions. One of the sample database tables is shown in Table 1 below.

TABLE 1: SAMPLE DATABASE

Field Names Data Types Size Allow Nulls Constraints

StaffId Nvarchar 50 No Pri ary key

staffNa e Nvarchar 50 No

Desi nation Nvarchar 50 Yes

Address Nvarchar 50 Yes

TelNo Nvarchar 50 Yes

Doj Dateti e 8 Yes

1.6 TECHNICAL SPECIFICATION & TESTING OF THE APPLICATION

The technical specification of the hardware and the software for the development as well as testing environment for the web application is as given below:

The hardware and software configuration 1 The hardware Platform

PC: Intel Pentium Dual CPU E2200 Processor speed: @ 2.20 GHz RAM: 1 GB Memory space: 150 GB

2 The software Platform Web Server: Apache Tomcat 6.0.18. Database Server: MySQL 5.0. Operating system: Window XP Professional Service Pack 2. Software Platform: NetBeans 6.5.1. Browser: Mozilla Firefox. Network bandwidth: 128 kbps.

1.6.1 The testing procedure

The Mercury LoadRunner is used for testing the application. It is an automated performance and load testing tool for studying system behavior and performance, while generating actual load [17]. Using limited hardware resources, LoadRunner emulated hundreds or thousands of concurrent users through the rigors of real-life user loads. It has excellent monitoring and analysis interface where reports are presented with easily understandable charts [18] [19].

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During the experiments, the stress level is gradually varied, so that it can saturate the server. This can lead to find out the capability of the server. Each HTTP requests causes a Standard Query Language (SQL) INSERT commands to insert two text fields in the database table. After invoking the application, users will log into the web application using a unique username and password. Successful Login will authenticate users to perform the transaction. Real life values are inserted into the text fields. The values can then be saved into the corresponding database table by pressing the SAVE button. User think time of approximately 10 seconds is incorporated in performing the transactions. An average steady state period of 30 minutes is fixed for all the experiments. The algorithm for the testing procedure is given in fig.3.

Step Instruction

1 begin 2 prepare test plan 3 create test environment 4 set stress level 5 create new scenario 6 set performance parameters 7 execute the test 8 if more test to perform then 9 repeat steps 4 to 7 10 else 11 analyze the result 12 if satisfied with result then 13 go to step 16 14 else 15 repeat steps 7 to 11 16 if system exhausted then 17 go to step 20 18 else 19 repeat steps 4 to 12 20 end

Figure 3: Algorithm for the testing procedure

1.6.2 TESTING PARAMETERS & THE TRANSACTION SUMMARY

The performance has been analyzed from the transaction summary available in the testing result. The numbers of virtual users are increased and the result for transaction summary is monitored.

1.6.2.1 The testing parameters

There are three main parameters which are varied during the testing procedure. They are: (a) the workload intensity measured in terms of number of virtual users, i.e. stress level, (b) the workload mix which defines what users will do in each session and (c) the user behavior parameter, which is the think time.

1.6.2.2 The test responses

The metrics of the load and stress testing which we have been monitoring include the passed transactions and failed transactions while performing load and stress testing.

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1.6.2.3 The experimental results

The performance testing is carried out for 10, 20, 30, 40, 50, 75, 100 and 125 virtual users. All the tests were carried out in 128Kilobytes/s bandwidth. It is observed that up to 40 users the application runs smoothly. The tests were conducted with ramp up schedule of 30 seconds. They are phased out at the same time after the completion of the steady state period [20]. The delays for the users think time is included to emulate the behavior of real users. 10 seconds of user think time is included in each of the test cases. The results of database transaction summary with increase in stress levels for insert operations are given in Table 2

Some sample responses of the database transaction summary are shown in fig.4, 5, 6 and 7. Fig.4 shows the response for transaction summary for 10 virtual users. In this case 238 transactions are allowed to perform database transaction. The fig.5 shows the response for transaction summary for 30 virtual users. It is observed that 474 transactions are allowed to perform database transaction. The fig.6 shows the response for transaction summary for 75 virtual users. It is observed that 118 transactions are allowed and 2036 transactions are failed. The fig.7 shows the response for transaction summary for 125 virtual users. It is observed that 71 transactions are allowed and 11427 transactions are failed.

TABLE 2 : SUMMARY OF DATABASE TRANSACTION

Scenario No. of

Users

Transaction Summery Connection

refusal in ( %) Passed Failed

Insert

Operation

10 2 8 0 0

20 54 0 0

0 474 0 0

40 687 0 0

50 470 159 0

75 118 20 6 26

100 54 1885 50

125 71 11427 62

Figure 4: Transaction summery for 10 users Figure 5: Transaction summery for 30 users

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Figure 6: Transaction summery for 75 users Figure 7: transaction summery for 125 users

1.6.3 THE STATISTICAL ANALYSIS

The statistical analysis of the implemented web application is performed for 10 virtual users run for 5 minutes in steady state. The user think time incorporated during transaction is 10 seconds. The same set of test scenario was repeated for 30 times. The observed metrics are given in Table 3 below to analyze for evaluating the reliability and stability of the database transaction of the application.

1.6.3.2 Analysis of distribution for passed transaction

The difference between best case and worst case in passed transaction is divided into 3 bins of equal width according to our convenience. The class width and observed frequency for passed transactions are shown in Table 3.

TABLE 3: OBSERVATION FREQUENCY WITH TRANSACTION

Passed

Transaction

Observed

Frequency

28 - 0

> 0 - 2 4

> 2 - 4 4

> 4 - 6 8

> 6 - 8 7

> 8 - 40 4

Our objective is to determine the distribution of passed transactions. One of the ways of determination is to plot a histogram of the passed transactions as shown in fig.8. The applied distribution is normal distribution according to the histogram.

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Figure 8: Histogram for passed Figure 9: Quantile plot for Figure 10: Normal probability transactions passed transaction plot for throughput

A better technique is to plot the observed quantiles versus the recorded data in a quantile plot [21]. If the distribution of observed data is normal, the plot is close to be linear. The resultant plot is shown in fig.9. Based on the observed plot the distribution appears to be linear. The test of linearity can be verified graphically, using the normal probability plot. If the data samples are taken from a normal distribution, the plot will appear to be linear. The normal probability plot of the passed transaction is shown in fig.10. The data follows a straight line, which predicts that the distribution is a normal one.

1.7 DISCUSSION AND CONCLUSION

The objective of our present investigation is to study the transaction summary of Java technique implementing with MySQL database server for developing web application. The analysis of the recorded data predicts that up to 40 virtual users the application shows ideal response without any refusal in connectivity with all the transactions being passed. As we increase the number of virtual users the transaction errors per session of the application as well as connectivity errors increases. For 40 virtual users 687 transactions are passed and 0 transactions are failed having no refusal of connection. Similarly, for 75 virtual users the number of passed transaction is 118, the number of failed transaction is 2036 and 26% connection is refused. For 100 virtual users the number of passed transactions are 54, number of failed transactions are 1885 with 50% connection refusal. Finally for 125 virtual users number of passed transactions are 71, failed transactions are 11,427 with 62% connection refusal.

The histogram, quantile plot and normal probability plot for pass transaction of the application show linearity and normality which provides enough evidence for the scalability and reliability of database transaction of the web application with large number of virtual users. However, the histogram is left skew. Also, the normal probability plot and quantile plots are not always perfectly straight line but depart from the line at some points. This gives the evidence of longer tails than the normal distribution.

From the above study and statistics we can conclude that for the web application, as we increase the number of virtual users the transaction failures as well as connection refusal increases. The application gets saturated at 75 virtual users. The application almost becomes inoperable near 125 users.

These results will provide Internet practitioners in research and industrial dynamic web application developers with an indication of the performance tradeoffs associated with current technologies for data base transaction summary.

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1.8 FUTURE WORK

Our future work will include detailed investigations on the reasons behind failed database transactions which have hampered the quality of the application. A testing tool devoted in observing DBMS transactions will be incorporated to find out the reasons behind the failure. Also we propose to compare our result with other web application implemented using .NET technique and Microsoft SQL Server as the database server [22, 23]. ACKNOWLEGDEMEMT

One of the authors Dr. Tulshi Bezboruah is thankful to the Director, the Abdus Salam International Centre for Theoretical Physics (ICTP), Trieste, Italy for providing excellent computing facilities under Junior Associate Scheme of ICTP during his present visit to the centre. This work is supported by the University Grant Commission (UGC), Govt. of India. The authors are also thankful to Prof. (Mrs.) K. Boruah, Professor & Head Department of Physics; Prof. H. K. Boruah, Professor, Department of Statistics and Formerly Dean, Faculty of Science, Gauhati University for their valuable suggestions during the statistical analysis of the data.

REFERENCES

[1] Whittaker, James A.: What Is Software Testing? And Why Is It So Hard?, IEEE SOFTWARE January / February 2000.

[2] Chays, D., Deng, Y., Frankl, P., G., Dan, S., Vokolos F., I., and Weyuker, E., J., An AGENDA for testing relational database applications, Software. Testing Verification Reliability, 2004, 14, pp1744.

[3] Haerder, T., and Reuter, A., Principles of Transaction-Oriented Database Recovery, Computing Surveys, Vol.15, No.4, December 1983.

[4] Yuetang Deng, Phyllis Frankl, Zhongqiang Chen, Testing Database Transaction Concurrency, Proceedings of the 18th IEEE International Conference on Automated Software Engineering, IEEE Computer Society Press: Los Alamitos, CA, 2003; 184193.

[5] Kapfhammer, G., M., Soffa, M., L., A Family of Test Adequacy Criteria for Database Driven Applications, ESEC/FSE03, September 15, 2003, Helsinki, Finland.

[6] Securing web application across the software development life cycle. White paper (2010):http://www.findwhitepapers.com/technology/software_development/software_testing.

[7] http://searchwindevelopment.techtarget.com/Definition/0,sid8_gci534970,00.htm1 [8] Menasc, Daniel A.: Load Testing of Web Sites, IEEE Internet Computing, July August 2002,

pp. 70 74. [9] http://www.manageengine.com/products/qengine/stress-testing.html. [10] http://en.wikipedia.org/wiki/Stress_testing. [11] http://www.faqs.org/faqs/software-eng/testing-faq/section-15.html. [12] Subraya, B., M., and Subrahmanya, S., V.: Object driven Performance Testing of Web

Applications, The First Asia-Pacific Conference on Quality Software (APAQS'00), Hong Kong, China, pp. 17-26.

[13] Burns, E., Schalk, C., and Griffin, N.: JavaServer Faces 2.0: The Complete Reference, MaGraw Hill (2010).

[14] Dudney, B., Lehr, J., Willis, B., LeRoy, M.: Mastering Java Server Faces, Wiley Publishing, Inc (2004).

[15] Kalita, M., and Bezboruah, T., On HTML and XML based web design and implementation techniques, Far East Journal of Electronics & Communications, Vol. 1, issue 1 2007, pp. 65-79.

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[16] Kalita, M., Khanikar, S. and Bezboruah, T., Investigations on performance testing and evaluation of PReWebN: A Java technique for implementing web application, IET Software (In press).

[17] http://pcquest.ciol.com/content/software/2004/104093002.asp. [18] www.ciao.co.uk [19] http://learnloadrunner.com/introduction/advantages-of-loadrunner/ [20] Cecchet, E., Chanda, A., Elnikety, S., Marguerite, J., and Zwaenepoel, W., Performance

comparison of middleware architectures for generating dynamic web content, Springer-Verlag, pp. 242-261.

[21] Bogrdi-Mszly, ., Szits, Z., Levendovszky, T., and Charaf, H., Investigating Factors Influencing the Response Time in ASP.NET Web Applications, LNCS 3746, 2005, pp.223-233.

[22] Kalita, M. and Bezboruah, T., Investigation on Performance Testing and Evaluation of PReWebD: A .NET Technique for implementing Web Application, IET Software (In press), 2011

[23] Kalita, M., and Bezboruah T.: Investigations on database transaction summary of interactive web application based on .NET technique, The 3rd International Scientific Conference of Salahaddin University-Erbil, October 18-20, 2011 (submitted).

Brief biography of the author: Dr. Tulsi Bezbarua is presently Associate Professor, Department of Electronics and Communication Technology, Gauhati University. His areas of interest Microwave Engineering, Signal Processing, Web-based instrumentations. Dr. Mitashree Kalita is currently post doctoral fellow in the Department of Computer Science and Engineering, Tezpur University. She has earned her M.Sc in Electronics Science and Ph.D from Gauhati University.

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CODING AND ITS APPLICATION IN

COMMUNICATION Parismita Gogoi Department of Electronics and Communication Technology Gauhati University, Guwahati, Assam, India Email: parismita.ect @gmail.com

ABSTRACT

Error control coding is often used in digital communication systems to protect the digital information from noise and interference and reduce the number of bit errors. This technique is mostly accomplished by selectively introducing redundant bits into the transmitted information stream to provide more reliable information transmission. Error control coding has been used extensively in digital communication systems nowadays because of its cost-effective performance towards achieving efficient, reliable digital transmission. In this paper the development of basic coding theory and various coding techniques are being discussed. The applications of coding to communication systems and future trends are also discussed. With each passing years, results of better error correction are obtained continuously and the performance of the systems are always found to be sailing gradually closing to that Shannons limit. Thus, error control coding promises always to be a very active area of research and in this paper a brief introduction of the area has been tried to put forward.

KEYWORDS

Coding, Shannon, Forward Error Correction, Concatenated Coding.

1. INTRODUCTION

In digital communication systems, error control coding proves to be one of the main communication techniques to protect the digital information from noise and interference and reduce the number of bit errors in various advanced communication systems. For more than sixty years since its inception, error control coding is playing a very important role which has been developed and adopted successfully into many application platforms.

The historical timeline of error correcting codes officially started in the year 1948 with the introduction of an information theory by Claude E. Shannon [1]. He had published a series of remarkable theoretical results which ever since have served as a beacon and goal for digital communication researchers. Among the better-known aspects of this work is a formula for the ''channel capacity'' of a wireless propagation channel of a given bandwidth perturbed by additive thermal noise: specifically, that this capacity, measured in bits/sec received, is linearly proportional to the bandwidth and logarithmically proportional to the received signal-to-noise ratio.

Far more important than Shannon's channel capacity formula is its significance: namely, that it is possible to process the information prior to transmission (encoding) and after reception (decoding) so as to achieve error-free communication asymptotically, provided the transmission rate

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(in bits/sec) does not exceed the channel capacity; conversely, for transmission rates above channel capacity, error-free communication becomes impossible.

Subsequently, there were many pioneer works or milestones after Shannon's discovery. Early attempts at constructing encoders and decoders which could provide performance approaching Shannon's channel capacity were through application of finite-field algebraic concepts. Next, greater effort on searching for good codes structure was done during 1960s. Through the 1970s, the design of families of codes with larger code lengths and better performance was focused as the main target. Then, the transformation from theoretical era to the practice was concentrated in 1980s. During this period of time, new design of encoders and decoders were presented frequently by researchers to digital communication engineering community. In this way, intensive research efforts have been done worldwide in order to achieve coding solution for solving related communication problems. Those are, among other things, 1. To find codes with good structural properties and good asymptotic error performance, 2. To have the better coding gain and to reduce decoding complexity, 3. To devise efficient encoding and decoding strategies for the codes and 4. To explore the applicability of good coding schemes in various digital transmission and storage systems and to evaluate their performance.

As the coding target, performance of the systems sailed gradually closing to that Shannons limit. Resulting to recognized milestones along the past five decades, development of that error control coding came up many successful results. For examples, they are block codes, hamming codes, Convolutional codes and Viterbi algorithm, Bose and Chaudhuri and Hocquenghem codes (BCH), Reed-Solomon codes (RS)[2], and Trellis Coded Modulation (TCM) [3]. The historical breakthrough of turbo codes then arrived at early of 1990s [4].

2. BASIC CODING THEORY The position of the channel encoder is shown in following block diagram of the elements of a

digital communication system (Figure 1). In these communication systems, the information is represented as a sequence of binary bits. The binary bits are then mapped (modulated) to analog signal waveforms and transmitted over a communication channel. The communication channel introduces noise and interference to corrupt the transmitted signal. At the receiver, the channel corrupted transmitted signal is mapped back to binary bits. The received binary information is an estimate of the transmitted binary information. Bit errors may result due to the transmission and the number of bit errors depends on the amount of noise and interference in the communication channel.

Figure 1: Channel encoder/decoder position in the block diagram of a Digital Communication System

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Channel coding is mostly accomplished by selectively introducing redundant bits into the transmitted information stream. The number of bits transmitted as a result of the error correcting code is therefore greater than that needed to represent the information. Without this, the code would not even allow detecting the presence of errors and therefore would not have any error controlling properties. The information is formed into frames to be presented to the encoder, each frame consisting of a fixed number of symbols. These additional bits will allow detection and correction of bit errors in the received data stream and provide more reliable information transmission [5].

An error control code can ease the design process of a digital transmission system in multiple ways such as the following:

a) The transmission power requirement of a digital transmission scheme can be reduced by the use of an error control codec. This aspect is exploited in the design of most of the modern wireless digital communication systems such as a cellular mobile communication system. b)Even the size of a transmitting or receiving antenna can be reduced by the use of an error control codec while maintaining the same level of end-to-end performance, E.g. VSAT (Very Small Aperture Terminal) network terminals. c) Access of more users to same radio frequency in a multi-access communication system can be ensured by the use of error control technique, e.g. cellular CDMA. d) Jamming margin in a spread spectrum communication system can be effectively increased by using suitable error control technique. Increased jamming margin allows signal transmission to a desired receiver in battlefield and elsewhere even if the enemy tries to drown the signal by transmitting high power in-band noise. Claude E. Shannon proved that any communication channel could be characterized by maximum theoretical capacity, C. If the source information rate, R, is less than C (R

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probable information sequence from the knowledge of the received coded sequence. If the elements (bit, dibit or a symbol made of group of bits) of the message sequence at the input to the encoder are defined over a finite field of qi elements and the sequence elements at the output of the encoder are defined over (same or a different) finite field with qo elements, the code rate or 'coding efficiency' R of the code is defined as

log( )log( )

in i

out o

L qRL q

..(3.1) where Lin and Lout denote the lengths of input and output sequences respectively. The code rate is a dimensionless proper fraction. For a binary code, qi = qo = 2 and hence, R = Lin=Lout. A (7, 4) Hamming code is an example of a binary block code whose rate R = 4/7. For an error correction code, R < 1 and this implies that some additional information (in the form of 'parity symbol' or 'redundant symbol') is added during the process of encoding. This redundant information, infused in a controlled way, help in decoding a received sequence to extract a reliable estimate of the information bearing sequence.

The process of error control can be categorized into the following:

1. Forward Error Correction (FEC): Complete process of decoding is applied on the received sequence to detect error positions in the sequence and correct the erroneous symbols. However, the process of error correction is not fool-proof and occasionally the decoder may either fail to detect presence of errors in a

Figure 2: A tree classifying some FEC codes based on their structures.

received sequence or, may detect errors at wrong locations, resulting in a few more erroneous symbols. This happens if, for example, too much noise gets added to the signal during transmission through a wireless channel. There are two main types of FEC codes, namely Block codes and Convolutional codes.

2. Auto Repeat Request (ARQ): In some applications (such as in data communications) it is important to receive only error-free information, even if it means more than usual delay in transmission and reception. A conceptually simple method of error detection and retransmission is

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useful in such situations. The error control decoder, at the receiver, only checks the presence of any error in a received sequence which is a relatively easy task compared to full error correction. In case any error is detected, a request is sent back to the transmitter via return channel, for re-transmitting the sequence (or packet) once again. The process ideally continues till an error-free sequence is received and, this may involve considerable delay in receipt and may result in delay for subsequent sequences.

Another aspect of this scheme is that the transmitter should have enough provision for storing new sequences while a packet is repeated several times. Three important and popular variations of this scheme are: i) Stop and Wait ARQ, ii) Continuous ARQ and iii) Selective Repeat ARQ. 3. Hybrid ARQ: Significant reduction in retransmission request is possible by using a moderately powerful FEC in an ARQ scheme. This saves considerable wastage in resources such as time and bandwidth and increases the throughput of the transmission system at an acceptably small packet error rate compared to any ARQ scheme with only error detection feature. This scheme is popular especially in digital satellite communication systems. Figure 2 shows a tree classifying some FEC codes based on their structures.

There are many differences between block codes and Convolutional codes. Block codes are based rigorously on finite field arithmetic and abstract algebra. They can be used to either detect or correct errors. Block codes accept a block of k information bits and produce a block of n coded bits. By predetermined rules, n-k redundant bits are added to the k information bits to form the n coded bits. Commonly, these codes are referred to as (n,k) block codes. Some of the commonly used block codes are Hamming codes, Golay codes, BCH codes, and Reed Solomon codes (uses non-binary symbols).

Convolutional codes are one of the most widely used channel codes in practical communication systems. These codes are developed with a separate strong mathematical structure and are primarily used for real time error correction. Convolutional codes convert the entire data stream into one single codeword. The encoded bits depend not only on the current k input bits but also on past input bits. The main decoding strategy for convolutional codes is based on the widely used Viterbi algorithm [6]. Convolutional coding with Viterbi decoding has been the predominant FEC technique used in space communication, particularly in geostationary satellite communication networks.

Whether block coding or convolutional coding is used, the encoded sequence is mapped to suitable waveforms by the modulator and transmitted over the noisy channel. The physical channel or the waveform channel consists of all the hardware (for example, filtering and amplification devices) and the physical media that the waveform passes through, from the output of the modulator to the input of the demodulator. The demodulator estimates which of the possible symbols were transmitted based upon an observation of the received signal. Finally, the decoder estimates the transmitted information sequence from the demodulator output. The decoder makes use of the fact that the transmitted sequence is composed of the code words. Transmission errors are likely to result in reception of a non-code sequence [7].

It is often useful to express coding performance not in terms of the error rate reduction for a given signal-to-noise ratio (SNR), but as the SNR difference at a fixed bit error rate. Consider an AWGN channel with one-sided noise spectral density No having no bandwidth restriction. Let Eb denote the received energy per bit. Coding gain is defined as the difference in value of Eb/No required attaining a particular error rate with and without coding. However, coding gain is obtained at the expense of transmission bandwidth. The bandwidth expansion is the reciprocal of the code rate. Coding schemes delivering 2 to 8 dB coding gain are widely used in modern digital communication

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systems. This is because of the phenomenal decrease in the cost of digital hardware and the much less significant decrease in the cost of analog components such as power amplifiers, antennas and so on.

4. CODING FOR DIGITAL COMMUNICATIONS

1) Block Codes and their Decoding An (n, k) block code C over an alphabet of q symbols is a set of qk n-vectors called code

words or code vectors. Associated with the code is an encoder which maps a message to its associated codeword. Since a linear block code C is a k-dimensional vector space, there exist k linearly independent vectors which we designate as go, gl, . . . , gk-1 such that every codeword c in C can be represented as a linear combination of these vectors, C =mo go +ml gl +...+ mk-l gk-1. Since the rows of G generate (or span) the (n, k) linear code C, G is called a generator matrix for C. For a block code to be useful for error correction purposes, there should be a one-to-one correspondence between a message m and its codeword c. However, for a given code C, there may be more than one possible way of mapping messages to code words [9].

A block code can be represented as an exhaustive list, but for large k this would be prohibitively complex to store and decode. The complexity can be reduced by imposing some sort of mathematical structure on the code. The most common requirement is linearity. A block code C over a field F, of q symbols of length n and qk codeword is a q-ary linear (n, k) code if and only if its qk codeword form a k-dimensional vector subspace of the vector space of all the n-tuples F i. The number n is said to be the length of the code and the number k is the dimension of the code. The rate of the code is R =k/n. The Hamming weight wt(c) of a codeword c is the number of nonzero components of the codeword. The minimum weight Wmin of a code C is the smallest Hamming weight of any nonzero codeword.

An encoder is systematic if the message symbols mo, ml. . . mk-1 may be found explicitly and unchanged in the codeword. For a linear code, the generator for a systematic encoder is called a systematic generator. A systematic generator is written in the form G = [P Ik], where Ik is the k x k identity matrix and P is a k x (n - k) matrix which generates parity symbols. The encoding operation is c = m [P Ik]. The codeword is divided into two parts: the part m consists of the message symbols, and the part mP consists of the parity check symbols. The generator matrix and the parity check matrix for a code satisfy GHT=0. The minimum distance dmin of C is equal to the smallest positive number of columns of H which are linearly dependent. E.g. A binary code has the eight code words (000000), (001101), (010011), (011110), (100110), (101011), (110101) and (111000). These codes words form a vector space of dimension three, so the code is a (6, 3) linear code. The minimum weight of the seven nonzero code words is 3, so the minimum distance is 3. Thus, the code is a single error correcting code. This code is said to be in systematic form; the first three bits of any code word can be considered as message bits while the last three bits, which are uniquely determined by the first three bits, are the redundant or parity bits [10].

Many of the important block codes are so-called cyclic codes or are closely related to cyclic codes. Cyclic codes are based on polynomial operations. A natural algebraic setting for the operations on polynomials is the algebraic structure of a ring. An (n,k) block code C is said to be cyclic if it is linear and if for every codeword c = (c0, c 1 , . . . , c n 1) in C, its right cyclic shift c' = (c n 1, c 0, . . . , c n 2) is also in C. The operations of shifting and cyclic shifting can be conveniently represented using polynomials. This class of codes can be easily encoded using simple feedback shift register circuits. Furthermore, because of their inherent algebraic structure, the decoding of cyclic code is straightforward, both conceptually and in practice. Examples of cyclic and related codes include the Bose-Chaudhuri- Hocquenhem (BCH), Reed-Solomon (RS), Hamming, Maximum-Length, Maximum-Distance-Separable (MDS), Reed-Muller, Golay etc. [10].

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The first step of the decoding procedure for block codes involves re-encoding the received information bits to obtain a new parity sequence. The modulo-2 difference between this parity sequence and the original parity sequence is called the syndrome. If no errors have occurred, the parity bits computed at the decoder will be identical to those actually received, and the syndrome bits will be zero. If the syndrome bits are not zero, errors have been detected.

Majority logic decoding is a simple form of threshold decoding and is applicable to both block and convolutional codes. There are codes that, because of the special form of their parity check equations, are majority logic decodable. Reed-Muller codes are the most important class of codes of this type. A Reed-Muller code was used in the Mariner mission to encode photographs of Mars. For error correction, the syndrome is processed further. The algebraic constraints defining a given block code generally yield a decoding technique or algorithm for the code. The decoding algorithm makes further use of the syndrome to calculate the error pattern affecting the received word. Most decoding algorithms require the use of binary quantization (hard decisions) at the demodulator output.

The most prominent decoding method is the iterative algorithm for BCH codes due to Berlekamp [11]. The basic idea is to compute the error-Locator polynomial and solve for its roots. The complexity of this algorithm increases only as the square of the number of errors to be corrected. Thus, it is feasible to decode powerful codes. There are several other algebraic decoding algorithms, some of which utilize soft decisions to improve performance. However, Berlekamp's algorithm is perhaps the deepest and most impressive result, and is straightforward to implement. This algorithm has permitted the use of BCH and Reed-Solomon codes in many applications, from the Voyager mission to compact disks.

2) Convolutional Coding and their Decoding Convolutional codes are widely used as channel codes in practical communication systems for error correction. The encoded bits depend on the current k input bits and a few past input bits. The main decoding strategy for Convolutional codes is based on the widely used Viterbi algorithm. This basic coding scheme has been modified and extended Trellis coded modulation (TCM) and turbo codes are two such examples [5] [9].

Convolutional codes are commonly described using two parameters: the code rate and the constraint length. The code rate, k/n, is expressed as a ratio of the number of bits into the Convolutional encoder (k) to the number of channel symbols output by the Convolutional encoder (n) in a given encoder cycle. The constraint length parameter, K, denotes the length of the Convolutional encoder, i.e. how many k-bit stages are available to feed the combinatorial logic that produces the output symbols. Closely related to K is the parameter m, which indicates how many encoder cycles an input bit is retained and used for encoding after it first appears at the input to the Convolutional encoder. The m parameter can be thought of as the memory length of the encoder.

A simple Convolutional encoder is shown in Figure 3. The information bits are fed in small groups of k-bits at a time to a shift register. The output encoded bits are obtained by modulo-2 addition (EXCLUSIVE-OR operation) of the input information bits and the contents of the shift registers which are a few previous information bits.

If the encoder generates a group of 'n' encoded bits per group of 'k' information bits, the code rate R is commonly defined as R = k/n. For example, in Figure 3, k = 1 and n = 2. The number, K of elements in the shift register which decides for how many code words one information bit will affect the encoder output, is known as the constraint length of the code [9]. A binary Convolutional code is generated by passing the information sequence to be transmitted through a linear finite-state shift

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register. For a (n, 1, K) convolution code, the shift register consists of K stages and n linear modulo-2 function generators. The input data is shifted into and along the shift register a single bit at a time producing an n-tuples output for each shift. Consequently, the code rate for a (n, 1, K) Convolutional encoder is 1/n.

The input stream m (k) passes through two filters (sharing memory elements) producing two output

streams Ck1 = m (k) + m (k-2) and Ck2 = m (k) + m (k-1) + m (k-2). These two streams are interleaved together to produce the coded stream Ck. Thus, for every bit of input, there are two coded output bits, resulting in a rate R = code.

A rate R = k/n Convolutional code has associated with it an encoder; a k n matrix transfer function G(x) called the transfer function matrix. For the rate R = code of this example, Ga(x) = [1 + x2 1 + x + x2]. A Convolutional encoder is basically a state machine. For both encoding and decoding purposes, state diagrams of the state machines, that is, a representation of the temporal relationships between the states portraying state/next-state relationships as a function of the inputs and the outputs is used. Trellis diagram is also a useful graph representing the connections from states at one time instant to states at the next time instant. The Figure 3 represents the Encoder, state diagram, and trellis for

G(x) = [1 + x2 1 + x + x2].

Figure 3: Encoder, state diagram, and trellis for G(x) = [l + x2; 1 + x + x2]

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Several algorithms have been developed for decoding Convolutional codes [12]. The one most commonly used is the Viterbi Algorithm, which is a Maximum Likelihood Sequence Estimator (MLSE). A variation on the Viterbi Algorithm is known as the Soft-Output Viterbi Algorithm (SOVA), which provides not only decoded symbols but also an indication of the reliability of the decoded values.

Another decoding algorithm is the Maximum a Posteriori (MAP) decoder frequently referred to as the BCJR algorithm, which computes probabilities of decoded bits [13]. The BCJR algorithm is somewhat more complex than the Viterbi Algorithm, without significant performance gains compared to Viterbi codes. The Viterbi Algorithm computes the maximum likelihood code sequence given the received data. The Viterbi algorithm is essentially a shortest path algorithm. Each code sequence is represented by a path through the trellis. The degree to which a given code sequence matches the noisy received sequence is measured in terms of a path metric. Paths with high path metrics correspond to the most likely transmitted code sequences. In fact, the algorithm applies to any trellis code, not just the convolution codes. The significance of the trellis viewpoint is that the transmitted code sequence almost always corresponds to the path with the highest path metric. The Viterbi Algorithm has been applied in a variety of other communications problems, including maximum likelihood sequence estimation in the presence of Inter-Symbol Interference and optimal reception of Spread-Spectrum Multiple Access communication. Convolutional codes using the Viterbi Algorithm are often concatenated with powerful Block Codes, especially in deep space applications. The sequence of states through the trellis for this encoder is shown in Figure 4; the solid line shows the state sequence for this sequence of outputs [9].

Figure 4: Path through trellis corresponding to true sequence.

3) Concatenated Coding In the year 1966, Dave Forney, the inventor of "concatenated codes," first published in his MIT PhD Thesis, one of the most important works in all of coding theory [14]. The Concatenated codes, introduced by Dave Forney to address a theoretical issue, immediately gained population and became widely used in space communications in the 1970s.

In his doctoral thesis, Forney showed that concatenated codes could be used to achieve exponentially decreasing error probabilities at all data rates less than capacity, with decoding complexity that increases only polynomially with the code block length N. In the basic concatenated coding scheme of Forney, the inner code is a short block code, like that envisioned by Shannon [1], with rate r close to C, blocks length n, and therefore 2nr codewords. The inner decoder decodes optimally, so its complexity increases exponentially with n; for large enough n it achieves a moderately low decoding error probability. The outer code is an algebraic Reed-Solomon (RS) code

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of length 2nr over the finite field with 2nr elements, each element corresponding to an inner codeword. The overall block length of the concatenated code is therefore N=n2nr, which is exponential in n, so the complexity of the inner decoder is only linear in N. The outer decoder uses an algebraic error-correction algorithm whose complexity is only polynomial in the RS code length 2nr; it can drive the ultimate probability of decoding error as low as desired. The basic concatenated coding scheme considered by Forney is shown in Figure 5 [14].

Figure 5: Illustrating Forney's concatenated coding system

By concatenating codes, very long codes can be achieved, capable of being decoded by two decoders suited to much shorter codes. Thus considerable savings in complexity is obtained, but at some sacrifice in performance. The outer code will always be one of a class of nonbinary BCH codes called Reed- Solomon codes, first because these are the only general nonbinary codes known, and second, because they can be implemented relatively easily, both for coding and for decoding.

Later, Turbo codes were first introduced in 1993 by Berrou, Glavieux, and Thitimajshima, and reported in Proc. Of ICC93, Geneva, Switzerland [4], where a scheme is described that achieves a bit-error probability of 10-5 using a rate 1/2 code over an additive white Gaussian noise (AWGN) channel and BPSK modulation at an Eb/N0 of 0.7 dB. The codes are constructed by using two or more component codes on different interleaved versions of the same information sequence. Turbo codes use multiple carefully chosen codes, a pseudo-random interleaver, and iterative decoding to approach the Shannon limit within 1 dB. The field of channel coding was revolutionized by the invention of turbo codes. This novel method provides virtually error-free communications or obtains much better coding gain beyond that of any other existing codes.

5. APPLICATIONS OF ERROR CONTROL CODING Error-control coding can be used for a number of different applications. Error control codes and its successors have been applied in most communications starting from the ground or terrestrial systems of data storage, ADSL modem, and fiber optic communications. Subsequently, it moves up to the air channel applications by employing to wireless communication systems, and then flies up to the space by using in digital video broadcasting and satellite communications. Undoubtedly, with the excellent error correction potential, it has been selected to support data transmission in space exploring system as well [15].

In presence of interference codes can be used to achieve reliable communication. In military applications error control codes are used to protect information from intentional enemy interference. In case of satellite communication, there are severe limitations on transmitter power. The deep-space communications application has been the arena in which most of the most powerful coding schemes for the power-limited Digital autopilots, digital process-control systems, digital switching systems, and digital radar signal processing all are systems that involve large amounts of digital data transfers

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between interconnected subsystems. In all these cases, error control coding is essential to maintain proper performance [16].

In satellite communication system, because of considerable propagation delay (250-300 ms) in geostationary satellite links, FEC techniques tends to be more widely used than ARQ techniques, which require data retransmission. One of the remarkable features of satellite communication system is that bit errors occur randomly, which is considered to be a significant advantage when applying FEC codes. A recent trend in digital satellite communication systems is to employ powerful FEC codes with large coding gains, making efficient use of limited satellite resources. Since the usable frequency bands are severely limited, it is also desirable to apply high rate FEC codes. The popular satellite error correction codes include:

Convolutional codes: o With constraint length less than 10, usually decoded using a Viterbi algorithm. o With constraint length more than 10, usually decoded using a Fano algorithm.

Reed-Solomon codes usually concatenated with convolutional codes with an interleaving; New modems support superior error correction codes (turbo codes and LDPC codes). The Digital Video Broadcasting standard defines a concatenated code consisting of inner

convolutional (standard NASA code, perforated, with rates 1/2, 2/3, 3/4, 5/6, 7/8), interleaving and outer Reed-Solomon code (block length: 204 bytes, information block: 188 bytes, can correct up to 8 bytes in the block).

In this way, Error coding is used for fault tolerant computing in computer memory, magnetic and optical data storage media, satellite and deep space communications, network communications, cellular telephone networks, and almost any other form of digital data communication. Different error coding schemes are chosen depending on the types of errors expected, the communication medium's expected error rate, and whether or not data retransmission is possible. Faster processors and better communications technology make more complex coding schemes, with better error detecting and correcting capabilities, possible for smaller embedded systems, allowing for more robust communications. However, tradeoffs between bandwidth and coding overhead, coding complexity and allowable coding delay between transmissions, must be considered for each application.

6. CONCLUSION

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