matt warren valeria bartsch, martin postranecky, matthew wing (and alexey lyapin, bino maiheu)
DESCRIPTION
HEP Group Meeting September 2008 ILC/CALICE (DAQ) ILC: International Linear Collider CALICE: Calorimetry for ILC DAQ: Data Acquisition. Matt Warren Valeria Bartsch, Martin Postranecky, Matthew Wing (and Alexey Lyapin, Bino Maiheu). ILC/CALICE DAQ People. Accelerator Guys. Post-Doc - PowerPoint PPT PresentationTRANSCRIPT
HEP Group Meeting September HEP Group Meeting September 20082008
ILC/CALICE (DAQ)ILC/CALICE (DAQ)
ILC: International Linear Collider ILC: International Linear Collider CALICE: Calorimetry for ILCCALICE: Calorimetry for ILCDAQ: Data AcquisitionDAQ: Data Acquisition
Matt WarrenMatt WarrenValeria Bartsch, Martin Postranecky, Matthew WingValeria Bartsch, Martin Postranecky, Matthew Wing
(and Alexey Lyapin, Bino Maiheu)
24 Sep 2008
Group Meeting - ILC/CALICE DAQ - Matt Warren 2
Accelerator Guys
Post-DocValeria Bartsch
ILC/CALICE DAQ PeopleILC/CALICE DAQ People
Engineer Martin Postranecky
Engineer Me
Post-DocAlexey Lyapin
Post-DocBino Maiheu
BossMatthew Wing
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Group Meeting - ILC/CALICE DAQ - Matt Warren 3
Linear Collider (not a circle)Linear Collider (not a circle)• The plan is to build an new The plan is to build an new
machine after the LHC.machine after the LHC.– 2020 (ish)2020 (ish)
• Detector development has Detector development has already startedalready started
• We need to get the data now as We need to get the data now as for testing, calibration and for testing, calibration and optimisation.optimisation.
• UCL are involved in calorimeter UCL are involved in calorimeter (CALICE) DAQ.(CALICE) DAQ. LHC – a circle!
ILC – a line!
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Group Meeting - ILC/CALICE DAQ - Matt Warren 4
ILC vs LHC: Beam structureILC vs LHC: Beam structure
• LHC has collisions LHC has collisions every 25ns every 25ns (40MHz)(40MHz)
/99% 1%
Bunch Train /5 Hz
Buffer data • Triggerless data readoutTriggerless data readout
25ns
• ILC (or CLIC) have periodic ‘Bunch Trains’ with long ILC (or CLIC) have periodic ‘Bunch Trains’ with long gaps between.gaps between.
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Group Meeting - ILC/CALICE DAQ - Matt Warren 5
ILC vs LHC: Trigger(less)ILC vs LHC: Trigger(less)• LHC modules store event data for LHC modules store event data for
each beam-crossing (BX)each beam-crossing (BX)– External system decides which data External system decides which data
to keep – sends ‘trigger’to keep – sends ‘trigger’
– Module “reads-out”Module “reads-out”
– DAQ expects dataDAQ expects dataTrigger
DAQ
• ILC wants to data from every BXILC wants to data from every BX– To reduce readout volume front-end modules decide what to keep: To reduce readout volume front-end modules decide what to keep:
auto-trigger.auto-trigger.
– Data is stored until end of train and read/SENT out in the gap.Data is stored until end of train and read/SENT out in the gap.
– DAQ expects only blocks of data for each trainDAQ expects only blocks of data for each train
pipeline
memory
DAQ
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Group Meeting - ILC/CALICE DAQ - Matt Warren 6
DAQ ConceptDAQ Concept
•Building for multiple ILC CAL sub-detector prototypesBuilding for multiple ILC CAL sub-detector prototypes
•Generic DAQ for many (economies of scale)Generic DAQ for many (economies of scale)
•Modular/Generic Structure:Modular/Generic Structure:•Generic readout system as much as possibleGeneric readout system as much as possible
•Detector specific interfaces only at ends of chainDetector specific interfaces only at ends of chain
•Other ‘bespoke’ functionality in FPGA with custom firmwareOther ‘bespoke’ functionality in FPGA with custom firmware
–Commercial components and protocols where possibleCommercial components and protocols where possible•Readout links use standard connectors and protocolsReadout links use standard connectors and protocols
•Currently on PCs with PCIe cardsCurrently on PCs with PCIe cards
•Future could be use telecoms standard ATCA (or uTCA) crates Future could be use telecoms standard ATCA (or uTCA) crates
–Use something “off-the-shelf” … DOOCsUse something “off-the-shelf” … DOOCs
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Group Meeting - ILC/CALICE DAQ - Matt Warren 7
DAQ PC
DAQ architectureDAQ architectureDetector Unit: Detector Unit: ASICsASICs
DIF:DIF: Detector InterFace connects Detector InterFace connects Generic DAQ and servicesGeneric DAQ and services
LDA:LDA: Link/Data Aggregator – Link/Data Aggregator – fanout/in DIFs and drives link to fanout/in DIFs and drives link to ODRODR
LDA
LDA
ODR
CCC
DetectorUnit
DIF
ODRODR:: Off Detector Receiver – PC Off Detector Receiver – PC interface for system.interface for system.
CCCCCC:: Clock & Control Card: Fanout Clock & Control Card: Fanout to ODRs (or LDAs)to ODRs (or LDAs)
CONTROL PCCONTROL PC:: DOOCS GUI DOOCS GUI (run-control)(run-control)
StorageControl
PC (DOOCS)
DAQ PC
ODR
DetectorUnit
DIF
DetectorUnit
DIF
DetectorUnit
DIF
UCL
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Group Meeting - ILC/CALICE DAQ - Matt Warren 8
ODR Hardware ODR Hardware •Using development board that suits our needs well:Using development board that suits our needs well:
•Based on Xilinx Virtex 4 FX100 FPGA (huge + 2xCPU)Based on Xilinx Virtex 4 FX100 FPGA (huge + 2xCPU)–We co-develop firmware with RHUL in VHDLWe co-develop firmware with RHUL in VHDL
•Receives data on 4 1.25Gb fibre optic receiversReceives data on 4 1.25Gb fibre optic receivers
•Can write data to RAM at 600MB/s, to disk at 170MB/sCan write data to RAM at 600MB/s, to disk at 170MB/s
•4x 2.5 Gbit4x 2.5 Gbit
•4 more via plug-ins4 more via plug-ins
•128 MByte RAM128 MByte RAM
•8 lane PCI-Express8 lane PCI-Express
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Group Meeting - ILC/CALICE DAQ - Matt Warren 9
Clock & Control Custom HardwareClock & Control Custom Hardware
CPLD
Debug Header
SMAs (vertical)
Add-ons interface
HDMIs
LEMO (NIM)
RS232
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Group Meeting - ILC/CALICE DAQ - Matt Warren 10
Future ideas: ATCAFuture ideas: ATCA• ATCA is a telecoms standardATCA is a telecoms standard
• Cards communicate using an Cards communicate using an array of links provided by the array of links provided by the backplanebackplane
• Backplanes have HUB slotsBackplanes have HUB slots– Point-to-point links from all other Point-to-point links from all other
slotsslots
• Global clock links, config links. Global clock links, config links.
• ATCA cards can host ATCA cards can host Mezzanines (AMC) – “AODR”Mezzanines (AMC) – “AODR”
• μμTCA is a crate for AMCsTCA is a crate for AMCs– Useful for debuggingUseful for debugging
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Group Meeting - ILC/CALICE DAQ - Matt Warren 11
Conclusion/Future plansConclusion/Future plans
• Beyond halfway through, but much to deliver:Beyond halfway through, but much to deliver:–Testbeam next year (or 2010) – we need to demonstrate this Testbeam next year (or 2010) – we need to demonstrate this
system workssystem works
–ODR works now, but plenty of room to improveODR works now, but plenty of room to improve
–Software growingSoftware growing
• Planning for phase 2Planning for phase 2–Even more generic (looking at SLHC work)Even more generic (looking at SLHC work)
–Use TCAUse TCA