max11261 evaluation kit - evaluates: max11261 · 2018-05-10 · max11261 evaluation kit evaluates:...

Evaluates: MAX11261MAX11261 Evaluation Kit

General DescriptionThe MAX11261PMB peripheral module (Pmod™) provides the necessary hardware to interface to the MAX11261, a 24-bit, 6-channel, 16ksps, integrated PGA delta-sigma ADC to any system that utilizes Pmod-compatible expan-sion ports configurable for I2C communication. The peripheral module includes a graphical user interface (GUI) that provides communication from the target device to the PC through the USB2PMB2#. The peripheral module can operate in multiple modes:Using USB2PMB2# Adapter: In “standalone” mode, the peripheral module is connected to the PC through a USB2PMB2# adapter board and performs a subset of the complete peripheral module functions with limitations for sample rate, sample size, and no support for coherent sampling.User-Supplied I2C Mode: The peripheral module provides a 12-pin Pmod-style header for user-supplied I2C interface to connect the signals for SCL, SDA, RSTB, and RDYB.

The peripheral module includes Windows XP®, Windows® 7, Windows 8.1, and Windows 10-compatible software for exercising the features of the IC. The peripheral module GUI allows different sample sizes, adjustable sampling rates, internal or external reference options, and graphing software that includes the FFT and histogram of the sampled signals.The peripheral module can be powered by a local +3.3V supply and comes installed with a MAX11261ENX+ in a 36-bump wafer-level package (WLP).

Features ● Various Sample Sizes and Sample Rates ● Time Domain, Frequency Domain, and Histogram

Plotting ● On-Board Voltage Reference (MAX6071) ● Proven PCB Layout ● Fully Assembled and Tested

319-100171; Rev 0; 3/18

Ordering Information appears at end of data sheet.

Windows are registered trademarks and registered service marks of Microsoft Corporation.

MAX11261 EV Board Photo

Maxim Integrated │ 2www.maximintegrated.com


Quick StartRequired Equipment

● MAX11261PMB1 EV kit (includes micro-USB cable) ● USB2PMB2 USB to I2C interface board ● Windows PC

Note: In the following sections, software-related items are identified by bolding. Text in bold refers to items directly from the EV kit software. Text in bold and underlined refers to items from the Windows operating system.

ProcedureThe EV kit is fully assembled and tested. Follow the steps below to verify board operation:1) Visit http://www.maximintegrated.com and search

for MAX11261 product page. Click on the Design Resources tab. The software associated with this part will be listed under Software.

2) Connect the MAX11261PMB1 board to the USB-2PMB2 board.

3) Connect the USB cable from the PC to the USB2PMB2 board. Windows may require some time to install its device driver.

4) Open the EV kit GUI, MAX11261EVKit.exe and select DeviceMAX11261PMB option (or MAX11261PMB).

5) In the center of the Configuration tab, inside the Delta-Sigma Modulator block, set Conversion Mode to Single Continuous and then click Convert and Read All. The status will be updated with the measurement data. See Figure 1.

6) On the Scope tab, click Capture. A data sample is collected and plotted on the graph. The frequency spectrum can be viewed on the FFT tab. The Scope, DMM, Histogram, and FFT tabs support data cap-ture for Single Continuous mode.

7) In the center of the Configuration tab, inside the Delta-Sigma Modulator block, set Conversion Mode to Continuous and then click Convert and Read All.

8) On the Scope tab, click Capture. A data sample is collected and plotted on the graph. The frequency spectrum can be viewed on the FFT tab. The Single Continuous and Continuous modes support different sets of sample rates. The Scope, DMM, Histogram, and FFT tabs support data capture for Continuous mode.

9) In the center of the Configuration tab, inside the

Delta-Sigma Modulator block, set Conversion Mode to Single Cycle and then click Convert and Read All. (Note: The Scope, DMM, Histogram, and FFT tabs do not support data capture for Single Cy-cle mode, so the Capture button will be disabled in this mode.)

10) In the Scan Mode tab, inside Read Data group, click Scan to ensure that the Conversion mode has been set to Single Cycle.

11) In the Sequence Settings group, click Enable All Channels to configure channels CH0-CH5 to be scanned in order, with GPO0-5 assigned to individ-ual channels. The channels can be scanned in any order, and the GPO’s can be assigned in any order.

12) Set Sequence Mode to Mode 2 or Mode 3, then click Scan to perform a scan and Read Data to read the data. Mode 2 and Mode 3 perform a single scan each time Scan is clicked, but Mode 4 scans per-petually until another mode is selected.

13) Set Sequence Mode to Mode 4, click Touch Detect Demo then click Scan. The registers will be config-ured for comparator mode 10 to trigger on a level change exceeding ±4096 LSB. Whenever the RDYB interrupt is asserted, the GUI will read the data and update its display.

Detailed Description of SoftwareThe main window of the peripheral module software con-tains seven tabs: Configuration, Scope, DMM, Histogram, FFT, Scan Mode, and Registers. The Configuration tab provides control for the ADC configuration including cali-bration and data capture. The other six tabs are used for evaluating the data captured by the ADC.The Scope, DMM, Histogram, and FFT tabs support data capture for Continuous and Single Continuous conversion modes (Sequence Mode 1). When in Single Cycle mode, the Capture button is disabled.The Scan Mode tab supports data capture for Conversion Mode = Single Cycle, Sequence Mode = Mode 1, 2, 3, or 4.

Evaluating Single Conversions (Sequence Mode 1)In the Configuration tab, when Conversion Mode is set to Single Cycle or Single Continuous, conversions can be performed by clicking Convert followed by Read Data and Status.Note: The Scope, DMM, Histogram, and FFT tabs require using Continuous or Single Continuous Conversion Mode instead of Single Cycle mode.

http://www.maximintegrated.com



Evaluating Continuous Conversions (SEQ Mode 1)In SEQ Mode 1, with Continuous conversion, the Scope, Histogram, and FFT tabs can be used to capture data.

Evaluating I2C SCLK RatesDifferent I2C clock rates can be selected from the menu OptionsI2CSCLK Rate. Be sure to set the SEQ register SIF_FREQ bits to the right range for the selected clock rate.

Evaluating I2C Voltage LevelsDifferent I2C voltage levels can be selected from the menu OptionsI2CVoltage. When selecting 1.8V operation, install a shunt at J7 and disable the CAPREG LDO.

Evaluating Sequence Modes 2 (01) and 3 (10)In Single Cycle Conversion mode, Sequence Mode 2 (01) and Mode 3 (10) can be evaluated using the Scan Mode tab.In the Scan Mode tab, inside Read Data group, click Scan to ensure that the Conversion mode has been set to Single Cycle.In the Sequence Settings group, click Enable All Channels to configure channels CH0-CH5 to be scanned in order, with GPO0-5 assigned to individual channels. The channels can be scanned in any order, and the GPO’s can be assigned in any order.Set Sequence Mode to Mode 2 (01) or Mode 3 (10); then click Scan to perform a scan and Read Data to read the data. Mode 2 and mode 3 perform a single scan each time Scan is clicked.

Evaluating Sequence Mode 4 (11)In Single Cycle Conversion mode, Sequence Mode 4 (11) can be evaluated using the Scan Mode tab.In the Scan Mode tab, inside Read Data group, click Scan to ensure that the Conversion mode has been set to Single Cycle.In the Sequence Settings group, click Touch Detect Demo to configure channels CH0-CH5 to be scanned in order, with GPO0-5 assigned to individual channels, set CMP mode 10, and set the limit registers to default values. The channels can be scanned in any order, and the GPO’s can be assigned in any order.

Set Sequence Mode to Mode 4 (11); then click Scan to perform a scan and Read Data to read the data.Mode 4 scans perpetually until another mode is selected.When Mode 4 is active, the software responds to RDYB hardware pin low, by performing Read Data and clearing the interrupt status. The channel Out-of-Range status bit indicates that a touch event happened on that channel (the internal high-pass filtered data exceeded the configured threshold).

ADC CalibrationTwo types of software calibration for offset and gain are available: self-calibration and system calibration. The primary mode for calibration is using the drop-down list to select a calibration mode, followed by clicking the Calibrate button. The checkboxes for Self Offset, Self Gain, System Offset, and System Gain allow for the user to enable or disable the calibration values. The cali-bration values can also be changed manually by entering a hex value in the numeric box.

Evaluating the PGA (Programmable Gain Amplifier)Using the internal PGA requires performing System Offset / System Gain calibration.On the Configuration Tab, under Calibration, make sure “Internal Values” is selected instead of “Interface Values”.Self Offset/Gain, Calibrate, Read All; verify that Self Offset and Self Gain values have changed slightly.After selecting Input Path = PGA 1V/V: On the Configuration Tab, under Calibration, make sure System Offset and System Gain are checked (enabled).Apply 0.0V to the input, select System Offset and Calibrate. Then Read All and verify the System Offset value changed.Apply full-scale 2.490V to the input, select System Gain and Calibrate. Then Read All and verify the System Offset value changed. Note: if the Status register shows Data Overrange or Sys Gain Overrange, you will need to slightly reduce the fullscale input voltage and try again.



Figure 1. MAX11261 EV Kit Configuration Window



Figure 2. MAX11261 EV Kit Scope Window



Figure 3. MAX11261 EV Kit DMM Window



Figure 4. MAX11261 EV Kit Histogram Window



Figure 5. MAX11261 EV Kit FFT Window



Figure 6. MAX11261 EV Kit Scan Mode Window



Detailed Description of HardwareU1, the MAX11261, is a 6-channel, 24-bit delta-sigma ADC with I2C Interface. Connect analog inputs to header J3 or terminal block J11 (these are equivalent). Set the common-mode level using jumper J2. Open-drain digital output control signals GPO[0:5] are provided on header J9 along with the SYNC and RDYB signals.

U2, the MAX8610, is a low-dropout linear regulator that provides the 3.0V AVDD supply.U3 and U4 are MAX6071, which provides the 2.500V VREF reference voltage and the 1.250V VCOM common-mode voltage.The EV kit includes the USB2PMB2 master for all I2C communication. Header J10 provides probe access to the signals on the PMOD interface connector J1.

Figure 7. MAX11261 EV Kit Registers Window



*Default J1 is the PMOD header J3 is an input header J9 is the GP0[0:5]/SYNC/RDYB header J10 is the SCL/SDA/RDYB/RSTB header J11 is an input terminal block

Table 1. Jumper Functions

#Denotes RoHS compliant.

JUMPER STATE FUNCTION

JMP1/JMP2

1-2*/1-2* Select address 0x30

1-2/1-3 Select address 0x31





1-4/1-2 Select address 0x3C

1-4/1-3 Select address 0x3D

1-4/1-4 Select address 0x3F

J21-2 Use MAX6071 as VCOM

2-3* Use GND as VCOM

J41-2* Select +3.3V for DVDD

Open Select user-provided supply for DVDD at J4-1

J51-2* Select +3.0V for AVDD

Open Select user-provided supply for DVDD at J5-1

J61-2* Select GND for AVSS

Open Select user-provided supply for AVSS at J6-1

J7Open* Use internal 1.8V subregulator if DVDD ≥ 2.0V

1-2 Use DVDD for internal logic if DVDD ≤ 2.0V

J81-2* Select VREF from the on-board MAX6071 as the voltage reference

2-3 Select AVDD as the voltage reference

PART TYPE

MAX11261SYS1# EV Kit

Ordering Information



MAX11261 EV Kit Bill of Materials

ITEM

QTY

REF

DES

Var S

tatu

sM

AXI

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MFG

PA

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#M

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MAX11261 EV Kit Bill of Materials (continued)

221

TP4

Pref

02-

TPM

INI5

004-

0050

04KE

YSTO

NE

N/A

TEST

PO

INT;

PIN

DIA

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CO

LD T

EST

231

U1

Pref

00-S

AMPL

E-01

MAX

1126

1EN

X+M

AXIM

MAX

1126

1EN

X+EV

KIT

PAR

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261E

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241

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Pref

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MAX

8510

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30-X

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8510

EXK3

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MAX

8510

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Pref

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MAX

1126

1PM

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L94

ITEM

QT Y

REF

DES

Var S

tatu

sM

AXI

NV

MFG

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RT

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CR

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HIE

LD Z

IP 4

inX6

in;W

/ESD

LO

GO

- PA

CKO

UT

31

PAC

KOU

T_BO

XPr

ef85

-MAX

KIT-

PNK

85-M

AXKI

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KN

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NK

FOAM

;FO

AM;A

NTI

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TIC

PE

12in

X12i

nX5M

M -

PAC

KOU

T

41

PAC

KOU

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RT

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TN

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EB IN

STR

UC

TIO

NS

FOR

MAX

IM D

ATA

SHEE

T

51

PAC

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03-0

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EV K

IT B

OX)

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DO

NO

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RC

HAS

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NP)

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KOU

T (T

hese

are

pur

chas

ed p

arts

but

not

ass

embl

ed o

n PC

B an

d w

ill be

shi

pped

with

PC

B)



GPO

4G

PO5

GPO

3

GPO

0G

PO1

GPO

2

RDYB

SYNC

CH5-

CH1+

CH0+

CH3+

CH2-

CH2+

CH1-

CH4-

CH3-

CH0-

CH4+

CH5+

AVSS

MAX

1126

1ENX

+

1UF

MAX

6071

AAUT

12+

1M

+3.0

V

PBC0

9SAA

N

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VPB

C12S

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1000

PF

10

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V+3

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10

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10

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10

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1000

PF

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10 10

282828

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101010

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10

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1000

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1000

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V

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MAX

6071

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F

0.01

UF

2.2K 4.

7UF

4.7U

F

1M

10

1M

MAX

8510

EXK3

0+

0.1U

F1U

F

0.1U

F

U1

U4

C23

U2

C17

C19

JMP1

JMP2

J2

R1R2R34

R35

R31

R33

R32

J3

R6R5R4R3

J10

C10

C12

C9C8

J1

C1C2

1

C20

C24

J7

J9

J11

R18

R17

R30

R29

C7

R16

R15

R28

R27

C6

R14

R13

R26

R25

C5

R12

R11

R24

R23

C4

R10

R9

R22

R21

C3

R8R7

J6

C13

C15

TP4

C27

U3

C18

J4

TP7

TP3

TP1

TP2

TP5

TP6

C11

C22

C26

C16

C14

J8

J5

C25

R20

R19

C2

GP0

4

RDYB

AIN0

PG

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2G

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SDA

RDYB

AVSS

RSTB

SYNC

GP0

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N3N

AIN2

NAI

N1N

AIN0

N

AIN5

PAI

N4P

AIN3

PAI

N2P

AIN1

P

ADR0

AIN4

P

AIN2

N

VREF

AVDD

AVDD

AVSS

GP0

1G

P02

RDYB

SDA

SCL

AVSS

AIN3

N

ADR1

SDA

AIN0

P

AIN0

N

AIN1

P

AIN3

P

VCO

M

VREF

SDA

AIN1

N

AIN4

N

AVSS

PMO

D7

PMO

D10

PMO

D9

RDYB

RSTB

SCL

SDA

AVDD

RDYB

SYNC

GP0

5

AIN2

P

REFP

GP0

3G

P04

RSTB

GP0

0

RSTB

REFP

AIN5

N

AIN5

P

VCO

M

ADR1GP05SCL

F6F5F4F3F2F1

E6 E5 E4 E3 E2 E1 D6 D5 D4 D3 D2 D1

C6C5C4C3C2C1

B6B5B4B3B2B1A6A5A4A3A2A1

5 6

4

2

13

51

2

43

4

3

2

1

4

3

2

1

3

2

1

121110987654321

654321

121110987

654321

21

987654321

1211109876543212

1

5 6

4

2

1

3

21

3

2

1

21

AIN0

P

DVDDCAPREG

DGNDADR1GPO5

SCL

GPO

3G

PO2

GPO

1AD

R0SD

ARD

YB_I

NTB

GPO

GND

RSTB

GPO

4SY

NCG

PO0

AVDD

AVSSCAPPCAPNREFNREFPAVSS

AIN5

NAI

N4N

AIN3

NAI

N2N

AIN1

NAI

N0N

AIN5

PAI

N4P

AIN3

PAI

N2P

AIN1

P

OU

T

ININ

OUT

F

OUT

SIN EN

GND

SG

NDF

BPSH

DN

OUT

GND

IN

ININININ

ININ

OU

T

OU

T

OU

T

OU

T

OU

TO

UT

INININININININ

IN

OU

T

IN

IN

IN

IN

IN

ININININININININININININ

ININININININININININININ

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

TOU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

J1-1

2J1

-11

J1-1

0J1

-9J1

-8J1

-7

J1-6

J1-5

J1-4

J1-3

J1-2

J1-1

OUT

F

OUT

SIN EN

GND

SG

NDF

MAX11261 EV Kit Schematic



MAX11261 EV PCB Top Silkscreen

MAX11261EV PCB Top Layer

MAX11261 EV Kit PCB Layout Diagrams

1.0’’

1.0’’



MAX11261EV PCB Layer 2


1.0’’

1.0’’

MAX11261 EV Kit PCB Layout Diagrams (continued)




MAX11261EV PCB Bottom Silkscreen

MAX11261 EV Kit PCB Layout Diagrams (continued)

1.0’’

1.0’’

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc. │ 18


REVISIONNUMBER

REVISIONDATE DESCRIPTION PAGES

CHANGED

0 3/18 Initial release —

Revision History

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

max11261 evaluation kit - evaluates: max11261 · 2018-05-10 · max11261 evaluation kit evaluates:...

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