max9247/max9248 evaluation kit · 2009. 12. 16. · max9247/max9248 evaluation kit evaluates:...
TRANSCRIPT
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX9247/MAX9248 Evaluation Kit
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General DescriptionThe MAX9247/MAX9248 evaluation kit (EV kit) pro-vides a proven design to evaluate the MAX9247 27-bit, 2.5MHz to 42MHz DC-balanced LVDS serializer and the MAX9248 27-bit, 2.5MHz to 42MHz DC-balanced LVDS deserializer. The MAX9247 serializes 27 bits of parallel input data, 18 bits of video, and 9 bits of control to a serial data stream. The MAX9248 deserializes the LVDS serial input, which converts to 18 bits of parallel video data and 9 bits of parallel control data.
The EV kit PCB has a MAX9247ECM+ or MAX9247GCM+ and a MAX9248ECM+ or MAX9248GCM+ installed.
FeaturesS 27-Bit Parallel Interface
S Rosenberger Connector (Cable Included)
S Independent Evaluation of the MAX9247/MAX9248 Serializer/Deserializer (SerDes)
S Proven PCB Layout
S Fully Assembled and Tested
Ordering Information
Component List
19-4940; Rev 0; 9/09
+Denotes lead(Pb)-free and RoHS compliant.
PART TYPE
MAX9247EVKIT+ orMAX9248EVKIT+
EV Kit
DESIGNATION QTY DESCRIPTION
C1–C15, C27–C41
0Not installed, ceramic capacitors (0603)
C16–C20, C48, C58–C61
1010FF Q10%, 16V X5R ceramiccapacitors (0805)Murata GRM21BR61C106K
C21, C25, C42, C44, C46, C51, C54, C57, C62,
C64
100.001FF Q10%, 50V X7R ceramiccapacitors (0603)Murata GRM188R71H102K
C22, C23, C24, C26, C43, C45, C47, C49, C50, C52, C53, C55, C56, C63, C65
150.1FF Q10%, 16V X7R ceramiccapacitors (0603)Murata GCM188R71C104K
JU1–JU5 5 4-pin headers
JU6, JU7, JU8 3 3-pin headers
JU9–JU21 13 2-pin headers
H1, H2 22 x 20 shrouded-plug connectors (0.100in centers)
H3–H9 72 x 10 shrouded-plug connectors (0.100in centers)
DESIGNATION QTY DESCRIPTION
P1, P2 2LVDS connectors, waterblue (with EMI/EMC washer)Rosenberger D4S20D-40ML5-Z
P3, P4 2 SMA vertical-mount connectors
R1, R2, R3, R6, R7, R9, R10,
R11, R13, R15, R16, R20–R48
0 Not installed, resistors (0603)
R4, R14 2 82.5I Q5% resistors (0603)
R5, R12 2 130I Q5% resistors (0603)
R8, R19 2 49.9I Q1% resistors (0603)
R17, R18 2 1kI Q1% resistors (0603)
U1 127-bit deserializer (48 LQFP)Maxim MAX9248ECM+ or Maxim MAX9248GCM+
U2 127-bit serializer (48 LQFP)Maxim MAX9247ECM+ orMaxim MAX9247GCM+
— 1Cable assembly (2m)MD Elektronik PT1482
— 16 Shunts
— 1PCB: MAX9247/9248 EVALUATION KIT+
MAX9247/MAX9248 Evaluation Kit
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Quick StartRequired Equipment
• MAX9247/MAX9248 EV kit (cable included)
• Two 3.3V DC power supplies
• Digital data generator (e.g., HP/Agilent 16522A)
• Two low-phase-noise clock generators (e.g., HP/Agilent 8133A)
• Logic analyzer or data-acquisition system (e.g., HP/Agilent 16500C)
• High-performance oscilloscope (e.g., HP/Agilent DSO80304B; see the Pseudo-Random Bit Sequence (PRBS) Mode section)
ProcedureThe MAX9247/MAX9248 EV kit is fully assembled and tested. Follow the steps below to verify board operation. Caution: Do not turn on the power supplies or signal sources until all connections are completed.
1) Verify that all jumpers (JU1–JU21) are in their default positions, as shown in Table 1.
2) Connect the first 3.3V power supply across the DVCC1 and GND1 pads of the EV kit.
3) Connect the second 3.3V power supply across the DVCC2 and GND2 pads of the EV kit.
4) Connect the GND1 and GND2 pads together.
5) Connect the Rosenberger cable from the P1 to the P2 connector of the EV kit.
6) Connect the data generator to the H6–H9 connectors and set to generate 27-bit parallel data at LVCMOS/LVTTL levels. See Table 2 for input bit locations.
7) Connect the first clock generator to the P4 SMA con-nector and set its output frequency between 2.5MHz and 42MHz (see Table 3 for PCLK_IN location).
8) Connect the second clock generator to the P3 SMA connector and set to within Q2% of the MAX9247 seri-alizer PCLK_IN frequency (see Table 3 for REFCLK location).
9) Connect the logic analyzer or data-acquisition system to connectors H1 and H2, as shown in Table 4.
10) Turn on the power supplies.
11) Enable the clock generators.
12) Enable the data generator.
13) Enable the logic analyzer or data-acquisition system and begin sampling data.
Component Suppliers
Note: Indicate that you are using the MAX9247 and the MAX9248 when contacting these component suppliers.
Table 1. MAX9247/MAX9248 EV Kit Jumper Descriptions (JU1−JU21)
JUMPER FUNCTIONSHUNT
POSITIONDESCRIPTION
JU1
MAX9248 falling latch edge
1-2* Connects the R/F pin of the MAX9248 to GND2 for falling output latch edge
MAX9248 latch edge 1-3 Connects the R/F pin of the MAX9248 to header H4-9
MAX9248 rising latch edge
1-4 Connects the R/F pin of the MAX9248 to DVCC2 for rising output latch edge
SUPPLIER PHONE WEBSITE
MD Elektronik GmbH 011-49-86-38-604-0 www.md-elektronik-gmbh.de
Murata Electronics North America, Inc. 770-436-1300 www.murata-northamerica.com
Rosenberger Hochfrequenztechnik GmbH 011-49-86 84-18-0 www.rosenberger.de
MAX9247/MAX9248 Evaluation Kit
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Table 1. MAX9247/MAX9248 EV Kit Jumper Descriptions (JU1−JU21) (continued)
JUMPER FUNCTIONSHUNT
POSITIONDESCRIPTION
JU2
MAX9248 LVTLL/LVCMOS range input
1-2*Connects the RNG1 pin of the MAX9248 to GND2 for logic 0 (see the MAX9248 IC data sheet to determine the frequency range)
MAX9248 LVTLL/LVCMOS range input
1-3 Connects the RNG1 pin of the MAX9248 to header H4-7
MAX9248 LVTLL/LVCMOS range input
1-4Connects the RNG1 of the MAX9248 to DVCC2 for logic 1 (see the MAX9248 IC data sheet to determine the frequency range)
JU3
MAX9248 LVTLL/LVCMOS range input
1-2*Connects the RNG0 pin of the MAX9248 to GND2 for logic 0 (see the MAX9248 IC data sheet to determine frequency range)
MAX9248 LVTLL/LVCMOS range input
1-3 Connects the RNG0 pin of the MAX9248 to header H4-5
MAX9248 LVTLL/LVCMOS range input
1-4Connects RNG0 pin of the MAX9248 to DVCC2 for logic 1 (see the MAX9248 IC data sheet to determine the frequency range)
JU4
MAX9248power-down
1-2 Pulls the PWRDWN pin of the MAX9248 to low for shutdown
MAX9248power-down
1-3 Connects the PWRDWN pin of the MAX9248 to header H4-3
MAX9248power-down
1-4* Pulls the PWRDWN pin of the MAX9248 high for full functionality
JU5
MAX9248 spreadspectrum
1-2Connects the SS pin of the MAX9248 to GND2 for data and clock output spread ±2% relative to REFCLK
MAX9248 spreadspectrum
1-3 Connects the SS pin of the MAX9248 to header H4-1
MAX9248 spreadspectrum
1-4*Connects the SS pin of the MAX9248 to DVCC2 for data and clock output spread ±4% relative to REFCLK
JU6
MAX9247 hardwired inputs
1-2* Connects even pins of headers H5–H9 to DVCC2
MAX9247 hardwired inputs
2-3 Connects even pins of headers H5–H9 to GND2
JU7
MAX9247preemphasis
or MOD11-2*
Connects the PRE pin of the MAX9247 to DVCC2 for enabling preempha-sis
MAX9247preemphasis
or MOD12-3
Connects the PRE pin of the MAX9247 to GND2 for disabling preemphasis or used for PRBS mode
MAX9247/MAX9248 Evaluation Kit
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Table 1. MAX9247/MAX9248 EV Kit Jumper Descriptions (JU1−JU21) (continued)
JUMPER FUNCTIONSHUNT
POSITIONDESCRIPTION
JU8
MAX9247MOD0
1-2* Connects the I.C. pin (24) of the MAX9247 to DVCC
MAX9247MOD0
2-3Connects the I.C. pin (24) of the MAX9247 to GND2 for enabling PRBS mode
JU9 MAX9247 IN+ Open* Used for probing IN+
JU10 MAX9247 IN- Open* Used for probing IN-
JU11 MAX9247 REFCLK Open* Used for probing REFCLK
JU12 MAX9248 OUT- Open* Used for probing OUT-
JU13 MAX9248 OUT+ Open* Used for probing OUT+
JU14
MAX9247LVTLL/LVCMOS range
input1-2*
Connects the RNG1 pin of the MAX9247 to DVCC1 for logic 1 (see the MAX9247 IC data sheet to determine the frequency range)
MAX9247LVTLL/LVCMOS range
inputOpen
Internally connects the RNG1 pin of the MAX9247 to ground when left unconnected
JU15
MAX9247LVTLL/LVCMOS range
input1-2*
Connects the RNG0 pin of the MAX9247 to DVCC1 for logic 1 (see the MAX9247 IC data sheet to determine the frequency range)
MAX9247LVTLL/LVCMOS range
inputOpen
Internally connects the RNG0 pin of the MAX9247 to ground when left unconnected
JU16
Board-supply connectivity
1-2*Connects DVCC2 to PVCC2. This shunt reduces the number of supplies required to operate the EV kit.
Board-supply connectivity
OpenDisconnects DVCC2 from PVCC2. The 2-pin header can be utilized for supply current measurements.
JU17
Board-supply connectivity
1-2*Connects DVCC2 to LVCC2. This shunt reduces the number of supplies required to operate the EV kit.
Board-supply connectivity
OpenDisconnects DVCC2 from LVCC2. The 2-pin header can be utilized for supply current measurements.
JU18
Board-supply connectivity
1-2*Connects DVCC2 to OVCC. This shunt reduces the number of supplies required to operate the EV kit.
Board-supply connectivity
OpenDisconnects DVCC2 from OVCC. The 2-pin header can be utilized for sup-ply current measurements.
JU19
Board-supply connectivity
1-2*Connects DVCC1 to IVCC. This shunt reduces the number of supplies required to operate the EV kit.
Board-supply connectivity
OpenDisconnects DVCC1 from IVCC. The 2-pin header can be utilized for sup-ply current measurements.
JU20
Board-supply connectivity
1-2*Connects DVCC1 to PVCC1. This shunt reduces the number of supplies required to operate the EV kit.
Board-supply connectivity
OpenDisconnects DVCC1 from PVCC1. The 2-pin header can be utilized for supply current measurements.
MAX9247/MAX9248 Evaluation Kit
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Table 1. MAX9247/MAX9248 EV Kit Jumper Descriptions (JU1−JU21) (continued)
Detailed Description of HardwareThe MAX9247/MAX9248 EV kit provides a proven design to evaluate the MAX9247 27-bit, 2.5MHz to 42MHz DC-balanced LVDS serializer and the MAX9248 27-bit, 2.5MHz to 42MHz DC-balanced LVDS deserializer. The MAX9247 serializes 27 bits of parallel input data, 18 bits of video, and 9 bits of control to a serial data stream. The MAX9248 deserializes the LVDS serial input, which converts to 18 bits of parallel video data and 9 bits of parallel control data.
Input SignalsThe MAX9247 accepts 27-bit parallel data, 18 video data bits, and 9 control data bits. The 27-bit pattern is sup-plied to the EV kit by connecting a data generator to the four 20-pin headers (H6–H9), or by connecting selected pins of H6–H9 to high/low LVCMOS/LVTTL states. See Table 2 for input bit locations designated on H6–H9.
Data-Enable Input (DE_IN)The MAX9247 DE_IN pin is accessible through header H6-13. Driving the pin high selects RGB_IN[17:0] to be latched. Driving the pin low selects CNTL_IN[8:0] to be latched.
Input and Output ClocksThe MAX9247 parallel input clock (PCLK_IN) is acces-sible through H5-5 or SMA connector P4 (see Table 3). Apply a clock frequency to the access points, which latches data and control inputs and provides the PLL clock.
The MAX9248 reference clock (REFCLK) input is acces-sible through H3-5 or SMA connector P3 (see Table 3). Apply a reference clock to the access point that is within Q2% of the MAX9247 serializer PCLK_IN frequency.
Output SignalsThe MAX9248 outputs 27-bit parallel data, 18 video data bits, and 9 control data bits at LVCMOS/LVTTL levels on the 40-pin headers (H1 and H2). To sample the 27-bit
*Default position.
Table 2. Video and Control Data Inputs
Table 3. Input/Output Clock Locations
JUMPER FUNCTIONSHUNT
POSITIONDESCRIPTION
JU21
Board-supply connectivity
1-2*Connects DVCC1 to LVCC1. This shunt reduces the number of supplies required to operate the EV kit.
Board-supply connectivity
OpenDisconnects DVCC1 from LVCC1. The 2-pin header can be utilized for supply current measurements.
INPUT SIGNALS DESIGNATION DESCRIPTION
RGB_IN0 H9-1 Input video bit 0
RGB_IN1 H9-3 Input video bit 1
RGB_IN2 H9-5 Input video bit 2
RGB_IN3 H9-7 Input video bit 3
RGB_IN4 H9-9 Input video bit 4
RGB_IN5 H9-11 Input video bit 5
RGB_IN6 H9-13 Input video bit 6
RGB_IN7 H8-1 Input video bit 7
RGB_IN8 H8-3 Input video bit 8
RGB_IN9 H8-5 Input video bit 9
RGB_IN10 H8-7 Input video bit 10
RGB_IN11 H8-9 Input video bit 11
RGB_IN12 H8-11 Input video bit 12
RGB_IN13 H8-13 Input video bit 13
RGB_IN14 H7-1 Input video bit 14
RGB_IN15 H7-3 Input video bit 15
RGB_IN16 H7-5 Input video bit 16
RGB_IN17 H7-7 Input video bit 17
CNTL_IN0 H7-9 Input control bit 0
CNTL_IN1 H7-11 Input control bit 1
CNTL_IN2 H7-13 Input control bit 2
CNTL_IN3 H6-1 Input control bit 3
CNTL_IN4 H6-3 Input control bit 4
CNTL_IN5 H6-5 Input control bit 5
CNTL_IN6 H6-7 Input control bit 6
CNTL_IN7 H6-9 Input control bit 7
CNTL_IN8 H6-11 Input control bit 8
SIGNAL DESIGNATION
PCLK_IN H5-5 or P4
REFCLK H3-5 or P3
MAX9247/MAX9248 Evaluation Kit
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pattern, connect a logic analyzer or data-acquisition sys-tem to H1 and H2. See Table 4 for the output bit locations on the H1 and H2 headers.
Data-Enable Output (DE_OUT)The MAX9248 DE_OUT pin is accessible through header H2-21. A high output indicates that RGB_OUT[17:0] are active and a low output indicates that CNTL_OUT[8:0] are active.
Rising and Falling Input Latch Edge (R/F)The MAX9248 has a selectable rising or falling output latch edge through logic setting on the R/F pin. Drive
the R/F pin low by placing a shunt in the 1-2 position of jumper JU1 (see Table 1). Drive the R/F pin high by plac-ing a shunt in the 1-4 position of JU1.
Frequency Range Setting (RNG1 and RNG0)The parallel clock frequency range for the MAX9247 can be configured through jumpers JU14 and JU15. Place a shunt on JU14 and JU15 to drive RNG1 and RNG0 high, or leave JU14 and JU15 unconnected to drive RNG1 and RNG0 low. Refer to the MAX9247 IC data sheet for actual frequency settings.
The operating frequency range for the MAX9248 can be configured through jumpers JU2 and JU3. Place a shunt in the 1-4 position of JU2 and JU3 to drive RNG1 and RNG0 high, or place a shunt in the 1-2 position of JU2 and JU3 to drive RNG1 and RNG0 low. Refer to the MAX9248 IC data sheet for actual frequency settings.
Power-Down (PWRDWN)The power-down mode in the MAX9247 and MAX9248 puts the outputs in high impedance, stops the PLL, and reduces supply current to 50FA or less.
The MAX9247 PWRDWN pin is accessible through header H6-15. Drive the pin high for normal operation of the MAX9247 or drive the pin low to power down the MAX9247.
The MAX9248 PWRDWN pin is accessible through jumper JU4 (see Table 1). Drive the pin high by placing a shunt in the 1-4 position of JU4 for normal operation. Drive the pin low by placing a shunt in the 1-2 position of JU4 to power down the MAX9248.
Spread-Spectrum Frequency (SS)The MAX9248 can set the frequency spread to ±4% or ±2% by moving the shunt of jumper JU5 to the appropri-ate position (see Table 1).
Pseudo-Random Bit Sequence (PRBS) ModeThe MAX9247/MAX9248 EV kit offers the user an internal test mode to quickly check full functionality and verify the quality of the SerDes link. This mode is called the pseudo-random bit sequence, or PRBS mode.
The MAX9247 features an on-chip PRBS generator that can be utilized to generate a pseudo-random bit stream to evaluate the quality and performance by comparing the output of the serializer (prior to the link/cable) with the input of the deserializer (after the link/cable).
Table 4. Video and Control Data OutputsOUTPUT SIGNALS
DESIGNATION DESCRIPTION
CNTL_OUT0 H2-3 Output control bit 0
CNTL_OUT1 H2-5 Output control bit 1
CNTL_OUT2 H2-7 Output control bit 2
CNTL_OUT3 H2-9 Output control bit 3
CNTL_OUT4 H2-11 Output control bit 4
CNTL_OUT5 H2-13 Output control bit 5
CNTL_OUT6 H2-15 Output control bit 6
CNTL_OUT7 H2-17 Output control bit 7
CNTL_OUT8 H2-19 Output control bit 8
RGB_OUT0 H2-27 Output video bit 0
RGB_OUT1 H2-29 Output video bit 1
RGB_OUT2 H2-31 Output video bit 2
RGB_OUT3 H1-3 Output video bit 3
RGB_OUT4 H1-5 Output video bit 4
RGB_OUT5 H1-7 Output video bit 5
RGB_OUT6 H1-9 Output video bit 6
RGB_OUT7 H1-11 Output video bit 7
RGB_OUT8 H1-13 Output video bit 8
RGB_OUT9 H1-15 Output video bit 9
RGB_OUT10 H1-17 Output video bit 10
RGB_OUT11 H1-19 Output video bit 11
RGB_OUT12 H1-21 Output video bit 12
RGB_OUT13 H1-23 Output video bit 13
RGB_OUT14 H1-25 Output video bit 14
RGB_OUT15 H1-27 Output video bit 15
RGB_OUT16 H1-29 Output video bit 16
RGB_OUT17 H1-31 Output video bit 17
MAX9247/MAX9248 Evaluation Kit
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To activate this feature, the MAX9247 must first enter power-down mode by driving H6-15 low. Place a shunt in the 2-3 position of JU7 and JU8. Activate the internal PRBS mode by applying a negative DC voltage (-1.0V to -3.0V) to the VNEG pad.
To monitor the SerDes signal integrity, connect one channel of the digital oscilloscope with differential probe capabilities to OUT+ and OUT- signal lines from jumpers JU12 and JU13 (MAX9247). Repeat the same test for the deserializer (MAX9248) on signal lines IN+ and IN-, accessible through jumpers JU9 and JU10.
Power SuppliesThe MAX9247 is powered by connecting PVCC1, LVCC1, IVCC, and DVCC1 to a DC power supply at 3.0V to 3.6V. The MAX9247 can be configured to reduce wiring to the supply and ground pads by placing shunts on jumpers JU19, JU20, and JU21. The MAX9248 is powered by applying 3.0V to 3.6V to the PVCC2, LVCC2, OVCC, and DVCC2 pads. The MAX9248 can be configured to reduce wiring to the supply and ground pads by placing shunts on jumpers JU16, JU17, and JU18.
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Figure 1a. MAX9247/MAX9248 EV Kit Schematic (Sheet 1 of 2)
1R/
F2
RNG1
3VC
CLVD
S4
IN+
5IN
-6
LVDS
GND
7PL
LGND
8VC
CPLL
9RN
G010
GND
11VC
C12
REFC
LK
13PWRDWN
14SS
15CNTL_OUT0
16CNTL_OUT1
17CNTL_OUT2
18CNTL_OUT3
19CNTL_OUT4
20CNTL_OUT5
21CNTL_OUT6
22CNTL_OUT7
23CNTL_OUT8
24DE_OUT
36RG
B_OU
T7
25VC
COGN
D
26VC
CO
27LO
CK
28PC
LK_O
UT
29RG
B_OU
T0
30RG
B_OU
T1
31RG
B_OU
T2
32RG
B_OU
T3
33RG
B_OU
T4
34RG
B_OU
T5
35RG
B_OU
T6
48RGB_OUT17
37VCCOGND
38VCCO
39RGB_OUT8
40RGB_OUT9
41RGB_OUT10
42RGB_OUT11
43RGB_OUT12
44RGB_OUT13
45RGB_OUT14
46RGB_OUT15
47RGB_OUT16
C24
0.1µ
F
C23
0.1µ
F
C1OP
ENC2
OPEN
C3OP
ENC4
OPEN
C5OP
ENC6
OPEN
C7OP
ENC8
OPEN
C9OP
ENC1
0OP
ENC1
1OP
ENC1
2OP
ENC1
3OP
ENC1
4OP
ENC1
5OP
EN
C34
OPEN
C27
OPEN
C35
OPEN
C28
OPEN
C36
OPEN
C29
OPEN
C37
OPEN
C30
OPEN
C38
OPEN
C31
OPEN
C39
OPEN
C32
OPEN
C40
OPEN
C33
OPEN
C41
OPEN
C21
0.00
1µF
C26
0.1µ
FC2
50.
001µ
F
C20
10µF
H4-1
H4-1
1
H4-1
3
H4-1
5
H4-7
H4-5
H4-3
H4-9
H4-2
H4-1
2
H4-1
4
H4-1
6
H4-8
H4-6
H4-4
H4-1
0
H4
OVCC
P1
H4-1
7
H4-1
9
H4-1
8
H4-2
0
H1-4
0
H1-3
0
H1-2
8
H1-2
6
H1-3
4
H1-3
6
H1-3
8
H1-3
2
H1-3
9
H1-2
9
H1-2
7
H1-2
5
H1-3
3
H1-3
5
H1-3
7
H1-3
1
H1
H1-2
4
H1-2
2
H1-2
3
H1-2
1
H1-1
1
H1-9
H1-7
H1-1
5
H1-1
7
H1-1
9
H1-1
3
H1-5
H1-3
H1-1
H1-2
0
H1-1
8
H1-1
6
H1-1
4
H1-1
2
H1-1
0
H1-8
H1-6
H1-4
H1-2
H2-4
0
H2-3
0
H2-2
8
H2-2
6
H2-3
4
H2-3
6
H2-3
8
H2-3
2
H2-3
9
H2-2
9
H2-2
7
H2-2
5
H2-3
3
H2-3
5
H2-3
7
H2-3
1
H2
H2-2
4
H2-2
2
H2-2
3
H2-2
1
H2-1
1
H2-9
H2-7
H2-1
5
H2-1
7
H2-1
9
H2-1
3
H2-5
H2-3
H2-1
H2-2
0
H2-1
8
H2-1
6
H2-1
4
H2-1
2
H2-1
0
H2-8
H2-6
H2-4
H2-2
MAX9248
U1
55
66
77
88
11
44
33
22
C22
0.1µF
R2OP
ENR1OP
EN
R6OP
EN
R9OP
EN
R11
OPEN
R513
0Ω R482
.5Ω
R12
130Ω R1
482
.5Ω
R10
OPEN
R13
OPEN
R7 OPEN
JU9
JU10
JU11
REFC
LKP3 RE
F
4 2
31JU
5
R3OP
EN
4 2
31JU
4
4 2
31JU
3
4 2
31JU
2
4 2
31JU
1
R849
.9Ω 1%
H3-1
H3-1
1
H3-1
3
H3-1
5
H3-7
H3-5
H3-3
H3-9
H3-2
H3-1
2
H3-1
4
H3-1
6
H3-8
H3-6
H3-4
H3-1
0
H3
H3-1
7
H3-1
9
H3-1
8
H3-2
0
C19
10µF
PVCC2
C18
10µF
LVCC2
C17
10µF
DVCC2
C16
10µF
VTEST
GND2
JU17
JU18
JU16
C47
0.1µ
FC4
60.
001µ
F
C45
0.1µ
FC4
40.
001µ
F
C43
0.1µ
FC4
20.
001µ
F
MAX9247/MAX9248 Evaluation Kit
Eva
lua
tes: M
AX
92
47
/MA
X9
24
8
_______________________________________________________________________________________ 9
Figure 1b. MAX9247/MAX9248 EV Kit Schematic (Sheet 2 of 2)
1GN
D2
VCCI
N3
RGB_
IN10
4RG
B_IN
115
RGB_
IN12
6RG
B_IN
137
RGB_
IN14
8RG
B_IN
159
RGB_
IN16
10RG
B_IN
1711
CNTL
_IN0
12CN
TL_I
N1
13GND
14VCC
15CNTL_IN2
16CNTL_IN3
17CNTL_IN4
18CNTL_IN5
19CNTL_IN6
20CNTL_IN7
21CNTL_IN8
22DE_IN
23PCLK_IN
24I.C.
36RN
G0
25
PRE
26PL
LGND
27VC
CPLL
28PW
RDW
N
29CM
F
30LV
DSGN
D
31LV
DSGN
D
32OU
T-
33OU
T+
34VC
CLVD
S
35RN
G1
48RGB_IN9
37GND
38VCC
39RGB_IN0
40RGB_IN1
41RGB_IN2
42RGB_IN3
43RGB_IN4
44RGB_IN5
45RGB_IN6
46RGB_IN7
47RGB_IN8
C53
0.1µ
FC5
40.
001µ
FC5
50.
1µF
C62
0.00
1µF
C61
10µF
VNEG
C63
0.1µ
F
C50
0.1 µ
FC5
10.
001 µ
F
C56
0.1µ
FC5
70.
001µ
F
JU12
JU13
JU15
JU14
H5-20
H5-10
H5-8
H5-6
H5-14
H5-16
H5-18
H5-12
H5-19
H5-9
H5-7
H5-5
H5-13
H5-15
H5-17
H5-11H5
H5-4
H5-2
H5-3
H5-1
H6-20
H6-10
H6-8
H6-6
H6-14
H6-16
H6-18
H6-12
H6-19
H6-9
H6-7
H6-5
H6-13
H6-15
H6-17
H6-11
H6
H6-4
H6-2
H6-3
H6-1
H7-20
H7-10
H7-8
H7-6
H7-14
H7-16
H7-18
H7-12
H7-19
H7-9
H7-7
H7-5
H7-13
H7-15
H7-17
H7-11
H7
H7-4
H7-2
H7-3
H7-1
H8-20
H8-10
H8-8
H8-6
H8-14
H8-16
H8-18
H8-12
H8-19
H8-9
H8-7
H8-5
H8-13
H8-15
H8-17
H8-11
H8
H8-4
H8-2
H8-3
H8-1
H9-20
H9-10
H9-8
H9-6
H9-14
H9-16
H9-18
H9-12
H9-19
H9-9
H9-7
H9-5
H9-13
H9-15
H9-17
H9-11
H9
H9-4
H9-2
H9-3
H9-1
C60
10µF
PVCC1
C59
10µF
LVCC1
C58
10µF
DVCC1
C48
10µF
IVCC
GND1
JU21
IVCC
JU20
JU19
C64
0.00
1µF
C65
0.1µ
F
P2
C52
0.1µ
F
C49
0.1µ
F
44
33
22
11
88
55
66
77
R15
OPEN
R16
OPEN
IVCC
1 32JU
6
MAX9247
U2
R17
1kΩ
1%
R18
1kΩ
1%
1 32JU
7
1 32JU
8
R20
OPEN
R29
OPEN
R36
OPEN
R43
OPEN
R44
OPEN
R45
OPEN
R46
OPEN
R47
OPEN
R48
OPEN
R21
OPEN
R22
OPEN
R23
OPEN
R24
OPEN
R25
OPEN
R26
OPEN
R27
OPEN
R28
OPEN
R30
OPEN
R31
OPEN
R32
OPEN
R33
OPEN
R34
OPEN
R35
OPEN
R36
OPEN
R37
OPEN
R39
OPEN
R40
OPEN
R41
OPEN
R19
49.9Ω
1%
R42
OPEN
P4PC
LK
MAX9247/MAX9248 Evaluation Kit
Eva
lua
tes:
M
AX
92
47
/MA
X9
24
8
10 _____________________________________________________________________________________
Figure 2. MAX9247/MAX9248 EV Kit Component Placement Guide—Component Side
Figure 3. MAX9247/MAX9248 EV Kit PCB Layout—Component Side
MAX9247/MAX9248 Evaluation Kit
Eva
lua
tes: M
AX
92
47
/MA
X9
24
8
______________________________________________________________________________________ 11
Figure 4. MAX9247/MAX9248 EV Kit PCB Layout—Inner Layer 2
Figure 5. MAX9247/MAX9248 EV Kit PCB Layout—Inner Layer 3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX9247/MAX9248 Evaluation Kit
Eva
lua
tes:
M
AX
92
47
/MA
X9
24
8
Figure 6. MAX9247/MAX9248 EV Kit PCB Layout—Solder Side
Figure 7. MAX9247/MAX9248 EV Kit Component Placement Guide—Solder Side