may 9, 20012 home network ready! design issues and verification challenges thomas chow mentor...
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May 9, 2001 2
Home Network Ready! Design Issues and
Verification Challenges
Home Network Ready! Design Issues and
Verification ChallengesThomas Chow
Mentor Graphics CorporationInventra, IP Division
Thomas ChowMentor Graphics Corporation
Inventra, IP Division
May 9, 2001 3
Historic TrendHistoric Trend
May 9, 2001 4
Appliance Semiconductor Market Snap ShotAppliance Semiconductor Market Snap Shot
May 9, 2001 5
Technology TrendTechnology Trend
May 9, 2001 6
Home NetworkGateway GrowthHome NetworkGateway Growth
May 9, 2001 8
InternetInternetHN
DeviceHN
Device
HNDevice
HNDevice
HNHNDeviceDevice
HNHNDeviceDevice
GatewayGateway
NetworkShops
NetworkShops
NetworkBank
NetworkBank
NetworkBtoB
Typical Home Network Typical Home Network
May 9, 2001 9
Typical NetworkAppliance ArchitectureTypical NetworkAppliance Architecture
Device logic and
User I/F
Device logic and
User I/FI/FI/F
uP / uCuP / uCuP / uCuP / uC FirmwareFirmware
Network Transfer ProtocolNetwork Transfer Protocol
May 9, 2001 10
SoC is DifficultBecause It’s a SYSTEMSoC is DifficultBecause It’s a SYSTEM
Multiple Technologies - Hardware/Software, Analog/Digital Multiple Teams - Hardware (Analog/Digital), Software, System Multiple Embedded Systems - IP Cores
Multiple Technologies - Hardware/Software, Analog/Digital Multiple Teams - Hardware (Analog/Digital), Software, System Multiple Embedded Systems - IP Cores
Digital Digital Logic/Logic/
MemoryMemory
Digital Digital Logic/Logic/
MemoryMemoryEmbeddedEmbeddedSoftwareSoftware
EmbeddedEmbeddedSoftwareSoftware
HARDWAREHARDWAREHARDWAREHARDWARESOFTWARESOFTWARESOFTWARESOFTWARE
ManufacturingManufacturingManufacturingManufacturing
Rei
tera
tion
Loop
Rei
tera
tion
Loop
Rei
tera
tion
Loop
Rei
tera
tion
Loop
Integration &Integration &VerificationVerification
Integration &Integration &VerificationVerification
AnalogAnalogAnalogAnalogEmbeddedEmbeddedCoresCores
EmbeddedEmbeddedCoresCores
SystemSystemTrade-OffsTrade-Offs
SystemSystemTrade-OffsTrade-Offs
Integration &Integration &VerificationVerification
Integration &Integration &VerificationVerification
Rei
tera
tion
Loop
Rei
tera
tion
Loop
Rei
tera
tion
Loop
Rei
tera
tion
Loop
Integration &Integration &VerificationVerification
Integration &Integration &VerificationVerification
May 9, 2001 11
SoC Design FlowSoC Design Flow
INSPIRATION
Hardware Design Re-usable IP Infrastructure Services
Hardware Design Re-usable IP Infrastructure Services
EARLY DESIGNEARLY DESIGN
Multi-core Debugging Co-Verification HW Acceleration
Multi-core Debugging Co-Verification HW Acceleration
PRE-SILICONPRE-SILICON
NEW PRODUCTSNEW PRODUCTS
POST-SILICONPOST-SILICONOn-Chip Debug IPSynchronized Debugging
On-Chip Debug IPSynchronized Debugging
May 9, 2001 12
Traditional WaterfallASIC Design FlowTraditional WaterfallASIC Design Flow
Specification DevelopmentSpecification DevelopmentSpecification DevelopmentSpecification Development
RTL Code DevelopmentRTL Code DevelopmentRTL Code DevelopmentRTL Code Development
Functional VerificationFunctional VerificationFunctional VerificationFunctional Verification
SynthesisSynthesisSynthesisSynthesis
Prototype Build and TestPrototype Build and TestPrototype Build and TestPrototype Build and Test
Place and RoutePlace and RoutePlace and RoutePlace and Route
Timing VerificationTiming VerificationTiming VerificationTiming Verification
Deliver to system integration and software test
RMM II, Chapter 2, fig. 2.2
May 9, 2001 13
Spiral SoC Design FlowSpiral SoC Design Flow
Parallel, concurrent development of HW-SW Parallel verification and synthesis of modules Floorplanning and P&R included in the
synthesis process Planned iteration throughout
Parallel, concurrent development of HW-SW Parallel verification and synthesis of modules Floorplanning and P&R included in the
synthesis process Planned iteration throughout
May 9, 2001 14
Soft CoreSoft CoreSoft CoreSoft Core
Test benchSelf-stimulating
Test benchSelf-stimulating
I/F BusBehavior
Model
I/F BusBehavior
Model
SRAM/ROMModel
SRAM/ROMModel
8-bit MCUEmbedded8-bit MCUEmbedded
Source Level Debugger Tcl/Tk Command Line Interface
Source Level Debugger Tcl/Tk Command Line Interface
OCI / JTAGOCI / JTAG
IEEE-1284IEEE-1284In Circuit EmulatorIn Circuit Emulator
Test BoardTest BoardTest BoardTest Board
Driver /Driver / ControlControl
AA
Driver /Driver / ControlControl
AA Port BPort BPort BPort B
Port APort APort APort A
Driver /Driver / ControlControl
BB
Driver /Driver / ControlControl
BB
FirmwareFirmwareFirmwareFirmware
M8051 E- Warp Debugger EPPEPP JTAGJTAG
SoC Verification /Debug EnvironmentSoC Verification /Debug Environment
May 9, 2001 15
Choice ProcessorSelection CriteriaChoice ProcessorSelection Criteria
Preserve legacy 8051 investments– Tools (off-the-shelf compilers, debuggers)– Applications
8-bit architecture– Boost performance– Address power consumption issues– Address post-integration issues
Preserve legacy 8051 investments– Tools (off-the-shelf compilers, debuggers)– Applications
8-bit architecture– Boost performance– Address power consumption issues– Address post-integration issues
May 9, 2001 16
M8051WarpPower/Performance BalanceM8051WarpPower/Performance Balance
In other words, M8051Warp executes 6X faster than the standard part
Power management– Gated clock
Separate clock controls for state machine, CPU, Timers and Serial I/F
In other words, M8051Warp executes 6X faster than the standard part
Power management– Gated clock
Separate clock controls for state machine, CPU, Timers and Serial I/F
'MIPS
'
10010 20 30 40 50 60 70 80 90
10
20
30
40
50
Clock Speed (M Hz)
12 MH
z 80C
51 Par
t
40 MH
z 80C
51 Par
t
60 MH
z M805
1 Core
100 MHz M8051W arp Core
33 MH
z 'Turb
o' Part
X1
X3
X6
May 9, 2001 17
Fully Evolved: The M8051E-WarpFully Evolved: The M8051E-Warp
Debugger system available through partnership with First Silicon Solutions (FS2)– PC (Windows) Based Software– In-Target System Analyzer provides
interface to PC On-Chip Instrumentation (OCI)
designed into M8051E-Warp for test access via JTAG port
Performance and low-power benefits of the M8051Warp retained
Debugger system available through partnership with First Silicon Solutions (FS2)– PC (Windows) Based Software– In-Target System Analyzer provides
interface to PC On-Chip Instrumentation (OCI)
designed into M8051E-Warp for test access via JTAG port
Performance and low-power benefits of the M8051Warp retained
M8051E-WarpIn-Circuit Debug
M8051E-WarpIn-Circuit Debug
The need to test SW on an embeddedThe need to test SW on an embeddedcore grew in importance:core grew in importance:
Post Silicon IPPost Silicon IP
The need to test SW on an embeddedThe need to test SW on an embeddedcore grew in importance:core grew in importance:
Post Silicon IPPost Silicon IP
May 9, 2001 18
Embedded System DevelopmentEmbedded System Development
System Design
Hardware Design
Prototype Build
Hardware Debug
Software Design
Software Coding
Software Debug
Project Complete
May 9, 2001 19
Stub Code to Emulate HardwareStub Code to Emulate Hardware
Benefits for Software DesignersBenefits for Software Designers
HW SimulationHW SimulationEmbedded CodeEmbedded Code
More time to develop and debug your code Validate code against hardware as you develop Maintain software design integrity
More time to develop and debug your code Validate code against hardware as you develop Maintain software design integrity
May 9, 2001 20
Device logic and
User I/F
Device logic and
User I/FI/FI/FI/FI/F
uP / uCuP / uC FirmwareFirmware
Network Transfer ProtocolNetwork Transfer ProtocolNetwork Transfer ProtocolNetwork Transfer Protocol
Typical Network Appliance ArchitectureTypical Network Appliance Architecture
May 9, 2001 21
Network Transport Selection - USB 2.0Network Transport Selection - USB 2.0
Topology Tiered Star 127 connections (max) 6 Tiers (max)
Bus Transactions 480 / 12 / 1.5 Mbps
Configuration Dynamic insertion/removal Auto configuration
Physical Layer 2-wire differential signaling,
NRZI, bit-stuffing, CMOS level (3.3V)
4-pin connector High Speed (480 Mbps)
Multi-Media, Video, Storage, Broadband Access, Imaging
Topology Tiered Star 127 connections (max) 6 Tiers (max)
Bus Transactions 480 / 12 / 1.5 Mbps
Configuration Dynamic insertion/removal Auto configuration
Physical Layer 2-wire differential signaling,
NRZI, bit-stuffing, CMOS level (3.3V)
4-pin connector High Speed (480 Mbps)
Multi-Media, Video, Storage, Broadband Access, Imaging
USBUSB
PenPen MouseMouse
KbdKbd
MicMic PhonePhone
PCPC
HUB HUBHUBHUB HOST/HUB HOST/HUB
MonitorMonitor
SpeakerSpeaker
May 9, 2001 22
BANDWIDTH BANDWIDTH APPLICATIONSAPPLICATIONS ATTRIBUTESATTRIBUTES
Very Low costEase of UseLots of fanout
Very Low costEase of UseLots of fanout
Low costGuaranteed latency Low costGuaranteed latency
LOW10 - 100Kb/sLOW10 - 100Kb/s
Input DevicesControl FunctionsInput DevicesControl Functions
FULL200K - 10Mb/sFULL200K - 10Mb/s
COMPUTE1+ Gb/sCOMPUTE1+ Gb/s
Primary DiskHome BackbonePrimary DiskHome Backbone
Very High bandwidthFiber capabilityVery High bandwidthFiber capability
USBUSB1.11.1
USBUSB1.11.1
Telephony/ Modem Audio, ScannerTelephony/ Modem Audio, Scanner
HIGH100 - 400Mb/sHIGH100 - 400Mb/s
Entertainment, A/VImagingEntertainment, A/VImaging
Peer-to-peerMultiple channelsPeer-to-peerMultiple channels
1394A1394Afor CEfor CE
1394A1394Afor CEfor CE
1394B1394BGigabitGigabit
1394B1394BGigabitGigabit
DEVICE COSTDEVICE COST
$5-25$5-25
$15-150$15-150
$200-500$200-500
$100-500$100-500
STD FEATURESTD FEATURE
19971997
19971997
19991999
19991999
HIGH120 - 480Mb/sHIGH120 - 480Mb/s
Entertainment, A/VImagingEntertainment, A/VImaging
High SpeedHigh SpeedUSBUSB2.02.0
USBUSB2.02.0
$60 - 300$60 - 300 2000+2000+
USB Focus on Low Cost,High Volume ApplicationsUSB Focus on Low Cost,High Volume Applications
May 9, 2001 23
Inventra USB 2.0 Device Demo System and DiagramInventra USB 2.0 Device Demo System and Diagram
May 9, 2001 24
High Speed Function ControllerHigh Speed Function Controller
Configurable – 1 to 16 endpoints– Endpoint Direction – FIFO depth
16/32bit VCI-compliant CPU Interface
DMA access to FIFOs Synchronous Single-
port RAM interface for FIFOs
Configurable – 1 to 16 endpoints– Endpoint Direction – FIFO depth
16/32bit VCI-compliant CPU Interface
DMA access to FIFOs Synchronous Single-
port RAM interface for FIFOs
USB 2.0 compliant for high/full speed functions
Outside of Soft Core
PHY
High Speed Function Controller Soft Core
CONTROL(Transaction State M achine)
USB Bus M CRe-
SyncFIFO
Controller
M CUI/F
Add
Cntl
Data
Packet Enc/DecCRC Gen/CheckP
HY
DMA
May 9, 2001 27
USB High Speed Function Controller - TestbenchUSB High Speed Function Controller - Testbench
Host Model USB Bus
USBHSFC Testbench Architecture
BehavioralRAM
UTMITransceiverMacroCell
Model
8/16 Bit
SynthesisableUSB Function
Controller Core
16/32 BitBVCI
InterfaceModel
MCU DataBuffers
Host DataBuffers
May 9, 2001 28
USB High Speed Function Core - DeliverablesUSB High Speed Function Core - Deliverables
VHDL or Verilog RTL source code Test bench (VHDL or Verilog)
– Achieves > 99% code coverage Example synthesis and scan-test scripts (dc_shell)
– Targeted an example 0.18 micron technology– Fault cover of > 98%
Simulation scripts (ModelSim) Sample Firmware
– C code generated to match your configuration Configuration GUI User Guide, Product Spec, Datasheet sheet
VHDL or Verilog RTL source code Test bench (VHDL or Verilog)
– Achieves > 99% code coverage Example synthesis and scan-test scripts (dc_shell)
– Targeted an example 0.18 micron technology– Fault cover of > 98%
Simulation scripts (ModelSim) Sample Firmware
– C code generated to match your configuration Configuration GUI User Guide, Product Spec, Datasheet sheet
May 9, 2001 29
Designed for Ease of ReuseDesigned for Ease of Reuse
High quality RTL code Tested on popular EDA tools
Mentor Graphics: ModelSim, Leonardo Spectrum Synopsys: Design Compiler TransEDA: VHDLCover, Verisure Cadence: VerilogXL
VCI complaint CPU Interface Configuration GUI
High quality RTL code Tested on popular EDA tools
Mentor Graphics: ModelSim, Leonardo Spectrum Synopsys: Design Compiler TransEDA: VHDLCover, Verisure Cadence: VerilogXL
VCI complaint CPU Interface Configuration GUI
May 9, 2001 30
Friendly GUI Let You Define Your Own USB ParametersFriendly GUI Let You Define Your Own USB Parameters
May 9, 2001 31
Gatecount ExampleGatecount Example
Gatecount Analysis
05
10152025303540
1 2 4 8 10 13 15
# User Endpoints
Are
a (
kg
ate
s)
High Speed
Full Speed
FIFO depths fixed at 64bytes
Number of endpoints varied
FIFO depths fixed at 64bytes
Number of endpoints varied
High Speed: Approx. 1500 gates for each additional endpoint
Full Speed: Approx. 800 gates for each additional endpoint
High Speed: Approx. 1500 gates for each additional endpoint
Full Speed: Approx. 800 gates for each additional endpoint
May 9, 2001 32
From SoC to Final ProductFrom SoC to Final Product
EmbeddedEmbeddedCoreCore
CustomCustomLogicLogic
ROMROM
RAMRAM
I/O
Log
icI/
O L
ogic
Cus
tom
Cus
tom
Log
ic L
ogic
May 9, 2001 33
Xilinx HomeNetworking ForumXilinx HomeNetworking Forum
Xilinx selected Inventra USB 2.0 + M8051E-Warp cores for Home Networking Reference Design– Our cores plus Kawasaki’s UTMI PHY are in two
Spartan devices Press Release on January 29, 2001 Demonstrated at their Forum during
February 1,2001 Additional solutions to follow
Xilinx selected Inventra USB 2.0 + M8051E-Warp cores for Home Networking Reference Design– Our cores plus Kawasaki’s UTMI PHY are in two
Spartan devices Press Release on January 29, 2001 Demonstrated at their Forum during
February 1,2001 Additional solutions to follow
May 9, 2001 35
For More information about Inventra IP’s USB products,
please visit:
www.mentor.com/inventra and
www.usb.org
For More information about Inventra IP’s USB products,
please visit:
www.mentor.com/inventra and
www.usb.org