mb86r11 errata sheet rev.1 - fujitsu global€¦ · · 2012-02-20mb86r11 errata sheet fujitsu...

1

MB86R11 Errata Sheet

FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL

All rights reserved, Copyright FUJITSU SEMICONDUCTOR LIMITED 2011

Revision History

Date Ver. Contents

2011/01/27 1.00 First release

2011/03/07 1.01 C4 2D Graphics Engine (Interrupt)

Added the workaround.

C10 3D Graphics Engine(Hang-up or wrong drawing result)

Added the occurrence conditions.

Addition C12,C13,C14

2011/03/15 1.02 Addition Effected samples

2011/03/31 1.03 Addition C15

2011/06/01 1.04 Addition C16,C17,C18,C19,C20,C21

2011/06/02 1.05 C19.4 update Correction schedule.

Addition C22

2011/07/20 1.06 C14 Pv6 -> IPv6.

C19 GMII/RMII -> GMII/RMII/RGMII

C22 GMII -> GMII/RGMII

2011/09/01 1.07 C19 GMII/RMII/RGMII -> RGMII

2011/09/06 1.08 Add C23 and C24

2011/09/12 1.09 Marge tables(Issue list and Effected Samples).

Corrected C22.1 Phenomenon/C22.2Workaround.

2011/09/20 1.10 C24 Corrected English expression

2011/10/04 1.11 Addition C25

2011/10/31 1.12 Addition C26

2011/11/15 1.13 Addition C27,C28

2011/11/18 1.14 C28 Updated workaround

Addition ES3 information

2011/11/25 1.15 Addition C29

2011/12/5 1.16 C2 Please see CA9+MP+Errata+v11.1.pdf -> deleted


Rev.1.16

This document describes the content of the hardware failures and measures of MB86R11.

2



Issue list ID Module Item ES1 ES2 ES3

C1 Operating condition Chip recommended operation

conditions

X - -

C2 Cortex-A9 Cortex-A9 errata X - -

C3 ADC 1st conversion after power down is

failed

X - -

C4 PixelEngine Interrupt X - -

C5 Ethernet Wake-On-Lan X - -

C6 Ethernet IEEE1588 X X X

C7 Ethernet MDIO interface X - -

C8 TCON RSDS Interface X - -

C9 RLD Data allocation X - -

C10 3D Graphics Engine Hang-up or wrong drawing result X - -

C11 Display Controller L4DA upper bit disappearance X - -

C12 DDR Controller Write leveling issue X - -

C13 3D Graphics Engine Wrong processing order of overlapped

pixels

X - -

C14 Ethernet IPv6 Routing Extension Header X X X

C15 3D Graphics Engine Hang-up in Bit Block Transfer with

AlphaMap.

X - -

C16 CRG STOP mode may not work correctly. X - -

C17 MediaLB Support Standard. X - -

C18 HS_SPI RX Data may be corrupted. X X X

C19 Ethernet GMII/RMII/RGMII interface AC

problem.

X X X

C20 Video Capture Unit Capture 1920 width limitation. X X -

C21 SDIO Controller 50MHz HighSpeed isn't supported. X - -

C22 Ethernet GMII/RGMII interface I/O buffer

problem.

X X X

C23 Display Controller Unable to read L2AM-bit X X -

C24 GDC Controller Y component of YCbCr is shifted left. X X -

C25 CRG_S Writing in the register might fail. X - -

C26 EBC CS2 in NAND Flash mode X X X

C27 CRG_S Software Reset might fail X X X

C28 Reset Debug reset might also assert with

software/watchdog reset.

X X X

C29 USART(Loopback) At operation mode 3 ,when you use

loopback, LIN communication does not

work well.

X X X

X:effected

-:not effected

3



C1 Chip recommended operating conditions

ES1 ES2 ES3

X - -

X:effected -:not effected

C1.1 Occurrence conditions

The recommended operating conditions is following.

3.3V standard CMOS I/O recommended operating conditions

Parameter Symbol Value Unit

Min. Typ. Max.

Supply voltage VDDE

VDDI, PLLVDD

3.0

1.2

3.3

1.25

3.6

1.3

V

Operating ambient temperature TA 0 25 degC

Junction temparature TJ 0 65 degC

SSTL15 IO(SSTL15 mode) recommended operating condtions


Min. Typ. Max.

Supply voltage DDRVDD

VDDI

1.425

1.2

1.500

1.25

1.575

1.3

V


SSTL15 IO(SSTL18 mode) recommended operating condtions


Min. Typ. Max.

Supply voltage DDRVDD

VDDI

1.7

1.2

1.8

1.25

1.9

1.3

V


USB2.0 recommended operating condtions


Min. Typ. Max.


C1.2 Phenomenon

LSI CHIP may not work collectly.

C1.3 Workaround

Please use LSI under above condistions.

C1.4 Correction schedule

This shall be fixed in LSI ES2.

4



C2 ARM Cortex-A9 Errata

ES1 ES2 ES3

X - -



CA9: r2p2 is implemented in LSI.

Please see ARM Cortex-A9 MPCore(MP004, AT396, AT397) Errata Notice.

C2.2 Phenomenon

CA9: r2p2 is implemented in LSI.

Please see ARM Cortex-A9 MPCore(MP004, AT396, AT397) Errata Notice.



5



C3 ADC(1st conversion after power down is failed)

ES1 ES2 ES3

X - -



1st conversion after power down released.

C3.2 Phenomenon

The conversion value is unstable.

C3.3 Workaround

Please do not use the value 1st converted after Power down released.



6



C4 Pixel Engine (Interrupt)

ES1 ES2 ES3

X - -



Interrupt is generated by Pixel Engine.

C4.2 Phenomenon

GIC module in Cortex A9 cannot detect the interrupt of Pixel Engine.

C4.3 Workaround

Checking Pixel Engine status in a regular period by timer interruption.



7



C5 Ethernet(Wake-On-Lan)

ES1 ES2 ES3

X - -



The function Wake-On-Lan of Ethernet cannot be used.

C5.2 Phenomenon

N/A

C5.3 Workaround

N/A



8



C6 Ethernet (IEEE1588)

ES1 ES2 ES3

X X -



The function IEEE 1588 of Ethernet cannot be used.

C6.2 Phenomenon

N/A

C6.3 Workaround

N/A


This shall be not fixed.

9



C7 Ethernet(MDIO Interface)

ES1 ES2 ES3

X - -



The function MDIO Interface of Ethernet cannot be used.

C7.2 Phenomenon

The MDIO Interface can not access to External PHY.

C7.3 Workaround

Please use I2C interface or GPIO for initialization of PHY.



10



C8 TCON(RSDS Interface)

ES1 ES2 ES3

X - -



The function RSDS Interface of TCON cannot be used. Because, AC-timing spec is fail.

C8.2 Phenomenon

N/A

C8.3 Workaround

Please use the TTL mode or Bypass mode.



11



C9 RLD(Data allocation)

ES1 ES2 ES3

X - -



Scenario:

1/ rle-coded data in DDR

2/ decompressed data in DDR (located at the same memory space of source data)

3/ Stride-function is selected

Condition:

while transfering in burst-mode and RLD reached the end of line (next stride),

RLD releases the burst-state for single-transfer-state. The next transfer in single-transfer-state begins with

next stride.

At that time fifo is empty and RLD is waiting for rle-coded data at the input,

but it never arrives because the write access is busy (DDR).

C9.2 Phenomenon

At that time fifo is empty and RLD is waiting for rle-coded data at the input,

but it never arrives because the write access is busy (DDR).

C9.3 Workaround

1/ if stride disable : no restriction on RLD-functionality

2/ rle-coded data (SRAM) are located in different space to destination data (DDR Ram) : no restriction

on RLD-functionality

3/ if stride enable and rle-coded data (DDR Ram) and destination data (DDR Ram)in the same location :

not supported



12



C10 3D Graphics Engine(Hang-up or wrong drawing result)

ES1 ES2 ES3

X - -



This phenomenon happens in a triangle drawing. It does not happen in a line drawing.

C10.2 Phenomenon

Triangle type primitives and PointSprite may be incorrectly drawn (pixels,

depth buffer, stencil function writing shift). The accumulation of

incorrectly drawn pixels may lead finally to a hang-up.

C10.3 Workaround

This phenomenon can be avoided in a special mode which can be specified by

the SetDebugParam display list command. After inserting the following

display list command, operation is changed to the special mode:

F4200000h // SetDebugParam with the special sub command 20h

00000001h

In this special mode, performance is reduced to 44%-95% of the original

rate. The exact performance loss depends on the specific application.



13



C11 Display Controller(L4DA upper bit disappearance)

ES1 ES2 ES3

X - -



L4DA register set more than 0x0fff_ffff.

C11.2 Phenomenon

Because the register bit doesn't exist in bit31-28 of L4DA, the address where the space of

256Mbyte or more is exceeded cannot be set.

When the capture buffer is displayed, it is no problem because L4DA is not referred.

C11.3 Workaround

The L4 display image is allocated in the space of 256Mbyte or less.



14



C12 DDR Controller(Write leveling issue)

ES1 ES2 ES3

X - -



This is issue of the case to connect DDR3SDRAM.

The case connected DQ0 pin of DDR3SDRAM to the MDQ pin(except the MDQ0/MDQ16 pin).

The case connected DQ8 pin of DDR3SDRAM to the MDQ pin(except the MDQ8/MDQ24 pin).

C12.2 Phenomenon

Response check of Wire leveling becomes abnormal.

A reply of swlvl_resp of Wire leveling is fixed 0.

DDR3SDRAM

connection pin

MB86R11

connection pin

Response check of Wire leveling

DQ0 of DRAM0 MDQ1-7(except MDQ0) swlvl_resp_0(MCR_40 Register 3840_00A0h) is 0

fixation.


fixation.


fixation.


fixation.

DRAM0: It is DDR3SDRAM connected to MDQ0-MDQ15 pin.

DRAM1: It is DDR3SDRAM connected to MDQ16-MDQ31 pin.

C12.3 Workaround

The work around chooses any of the following case for Wire leveling.

Case1:

Connect DQ0 of DDR3SDRAM to MDQ0/MDQ16 pin.And connect DQ8 of DDR3SDRAM to

MDQ8/MDQ24 pin.

The Response check of Wire leveling replies normally.

Case2:

Connect DQ0 of DDR3SDRAM to MDQ0/MDQ16 pin.

The Response check(swlvl_resp_0 and swlvl_resp_2) of Wire leveling replies normally.

And adjustment does wrlvl_delay_0 and wrlvl_delay_2 by Write leveling.

wrlvl_delay_1 sets a value same as wrlvl_delay_0, and the Response check of swlvl_resp_1 skips.


Case3:

Connect DQ8 of DDR3SDRAM to MDQ8/MDQ24 pin.

The Response check(swlvl_resp_1 and swlvl_resp_3) of Wire leveling replies normally.

And adjustment does wrlvl_delay_1 and wrlvl_delay_3 by Write leveling.

15







16



C13 3D Graphics Engine(Wrong processing order of overlapped pixels)

ES1 ES2 ES3

X - -



This phenomenon happens in a triangle drawing. It does not happen in a line drawing.

C13.2 Phenomenon

When a later pixel position is overlapping with a previous pixel, a later pixel may outstrip a previous pixel.

It depends on a hardware internal condition.

C13.3 Workaround

No workaround.



17



C14 Ethernet (IPv6 Routing Extension Header)

ES1 ES2 ES3

X X X



C14.2 Phenomenon

The Segments Left field in the IPv6 Routing extension header indicates the number of remaining route

segments, that is, the number of explicitly listed intermediate nodes to be visited before reaching the final

destination (end node). A value of zero in the Segment Left field indicates an end node. The Receive

Checksum Offload Engine in the F_GMAC4 is targeted and designed only for the end node applications.

Therefore, the F_GMAC4 should process the routing header only if the value in the Segment Left field is

zero.

However, because of this defect, the F_GMAC4 processes the payload of all routing headers without

looking at the Segment Left field in the IPv6 Routing extension header. Therefore, for packets with non-

zero value in the Segment Left field, it may result in incorrect payload checksum calculation if the final

payload is TCP, UDP, or ICMPv6. This is because correct IPv6 Destination address is not considered for

checksum calculation. This results in the packet may get dropped in the RxFIFO. If your chip is expected

to process or forward such intermediate node IPv6 packets, then do not enable the Checksum Offload

Engine in the F_GMAC4.

C14.3 Workaround

1. F_GMAC4 is not used as a Router : There are not problem

If it is not router, it doesn’t have to send a packet with routing header to the different addresses.

It is not issue even if F_GMAC4 discards the packet.

2. F_GMAC4 is used for as router: One of the followins should be chousen by software

A) Discard error frame

Set IPC (MAC Configuration Register [10]) to "1".

Set DT (Operation Mode Register [26]) to "1".

Ignore checksum error (RDES0 [7] = 1) with the following condition.

A received frame is IPv6 packet and the Segment left field of the Routing Header is not

zero

B) Calculate checksum

In IPv6 environment, set IPC (MAC Configuration Register [10]) to "0".

Calculate checksum of TCP, UDP and ICMP.



18



C15 3D Graphics Engine(Hang-up in Bit Block Transfer with AlphaMap)

ES1 ES2 ES3

X - -



If both of the conditions below are used, a hang-up occurs depending on a hardware internal state.

1. Displaylist command is BltCopyAltAlphaMapP.

2. After the scissor test, a number of pixels for copy meets the below conditions.

[In the case of 32bit/pixel color] : (2 * 128 * n) +1 (n>=1)

[In the case of 16bit/pixel color] : (4 * 128 * n) +m (n>=1, m=1,2,3)

[In the case of 8bit/pixel color] : (8 * 128 * n) +m (n>=1, m=1,2,3,4,5,6,7)

C15.2 Phenomenon

The 3D Graphics Engine hang-up occurs.

C15.3 Workaround

Changing the copy size after the scissor test to the size below.

[In the case of 32bit/pixel color] : X size or Y size is a multiple of two.

[In the case of 16bit/pixel color] : X size or Y size is a multiple of four.

[In the case of 8bit/pixel color] : X size or Y size is a multiple of eight.

Extra pixels caused by the size extension can be specified as transparent pixel by 0% blend ratio in

AlphaMap..



19



C16 CRG(STOP mode)

ES1 ES2 ES3

X - -



C16.2 Phenomenon

STOP mode may not work correctly.

(Electrical characteristics problem)

C16.3 Workaround

Please use STOP mode only in PLLBYPASS mode.



20



C17 MediaLB(Support standard)

ES1 ES2 ES3

X - -



C17.2 Phenomenon

MOST50 cannot be supported.

C17.3 Workaround

Please use MOST25.



21



C18 HS_SPI(RX Data may be corrupted)

ES1 ES2 ES3

X X X



RX Fifo becomes full

C18.2 Phenomenon

One of the following phenomenons may occur

RX Data is lost

Wrong RX Data i.e. sampled at wrong moment

Transfer is stopped too soon in TX-and-RX protocol, i.e. when STOP is set, data is not

transmitted/received anymore after RX FIFO gets full

Transfer is stopped too soon when byte counter is used, i.e. less data than configured by the byte

counter is transferred

C18.3 Workaround

Do not let the RX-FIFO become full (use low RX-FIFO threshold and low interrupt/DMA latency time)



22



C19 Ethernet(GMII/RMII/RGMII Interface:AC)

ES1 ES2 ES3

X X X



In LSI ES1,the function GMII/RMII/RGMII Interface of Ethernet can not be used because of no

adjustment of AC timing.

In LSI ES2,the function RGMII Interface of Ethernet can not be used because of no adjustment of AC

timing.

C19.2 Phenomenon

In LSI ES1,the GMII/RMII/RGMII Interface can not be used.

In LSI ES2,the RGMII Interface can not be used.

C19.3 Workaround

No workaround.



23



C20 Video Capture Unit(Capture 1920 width limitation)

ES1 ES2 ES3

X X -



Capture unit 0 is used, and

Scaling ratio is not 1:1, and

Width of capture result is larger than 1280 pixel

C20.2 Phenomenon

It is assumed that capture unit 0 accept picture width

up to 1920 pixel, but error data like noise appeas at

right and left side of output picture if it is wider

than 1280 pixel.

C20.3 Workaround

Limit capture usage to 1:1 scaling if output picture

is larger than 1280



24



C21 SDIO Controller(50MHz HighSpeed)

ES1 ES2 ES3

X - -



50MHz HighSpeed isn't supported.

(AC electrical characteristics problem.)

C21.2 Phenomenon

C21.3 Workaround

No workaround.



25



C22 Ethernet(GMII/RGMII Interface:I/O buffer)

ES1 ES2 ES3

X X X



The function GMII/RGMII Interface of Ethernet can not be used because of I/O buffer problem.

C22.2 Phenomenon

The GMII/RGMII Interface can not be used.

Tr/Tf characteristic of MB86R11 at C_load 5pf is 1.50 ns and this cannot satisfy the specification.

C22.3 Workaround

Then if this spec is not meet to PHY macro, user should insert the buffer on board or other way to solve

Tr/Tf spec.



26



C23 Display Controller (Read error of L2AM-bit)

ES1 ES2 ES3

X X -



Read L2Blend register

C23.2 Phenomenon

L2AM-bit can not be read as proper value.

C23.3 Workaround

No workaround.



27



C24 GDC Controller (Misalignment of Y component)

ES1 ES2 ES3

X X -



YCbCr output is used.

C24.2 Phenomenon

Y component is shifted left by one pixel. Left edge is missing and right edge is repeated twice.

C24.3 Workaround

1) If YCbCr output is used finally as composite analog output, horizontal shift by one pixel is not

distinguished by filter effect in general. Check if the effect is negligible.

2) Avoid left edge and right edge when displayed picture is designed.



28



C25 CRG_S (Register access)

ES1 ES2 ES3

X - -



SSCGCTL.CLKSEL(CCNT Register) is 1.

C25.2 Phenomenon

Writing in the CRG_Sregister might fail.

(Problem of asynchronization)

C25.3 Workaround

Please set SSCGCTL.CLKSEL==0.



29



C26 EBC (CS2 in NAND Flash mode)

ES1 ES2 ES3

X X X



CS2 is NAND mode(Mode register2 NAND bit is '1') and GLBCTL.CS_MOD of CCNT register is '1'.

C26.2 Phenomenon

CS2 isn't masked.

So,coflict of data or freeze may happen.

C26.3 Workaround

Please don't use CS2 in NAND mode.

When you want to use CS2 NAND mode,please set GLBCTL.CS_MOD=0.



30



C27 CRG (Software Reset)

ES1 ES2 ES3

X X X



Execute Software Reset(CRG_S:0x3B500024) when CCNT.SSCGCTL.CLKSEL=1.

C27.2 Phenomenon

Software Reset sometimes fail.

C27.3 Workaround

Please set CCNT.SSCGCTL.CLKSEL=0 and SSCG of CRG_S is disabled.



31



C28 Reset (Debug Reset)

ES1 ES2 ES3

X X X



1) Software reset is asserted when CRRSC.SWRSTM==0(CRG_S Register).

2)Watchdog reset is asserted when CRRSC.WDRSTM==0(CRG_S Register).

C28.2 Phenomenon

Debug reset might also occure.

This phenomenon occurs when Tb exceeds Tbmax cycle(*1,*2).

*1 Tb depends on CRRSC.SRSTMODE(CRG_S Register) setting.

*2 In case 400MHz(max frequency) and SRSTMODE==15(default setting),

Tbmax is 384*2.5(ns)=960(ns)

XSRST

Ta Tb

SRSTMODE Ta Tbmax

0 8 cycles 16 cycles















15(default) 1536 cycles 384 cycles

32



C28.3 Workaround

CRRSC.SWRSTM CRRSC.WDRSTM Workaround

0 0 2)

0 1 1) or 2)

1 0 2)

1 1 unnecessary

1) Please assert software reset in PLLBYPASS mode.

2)Please pull-up XSRST outside LSI and stand up less than Tbmax cycles.



33



C29 USART(Loopback)

ES1 ES2 ES3

X X X



When you use Loopback at operation mode3 under the setting of SMRn.MD[1:0]==3 and

EFERHn.INTLBEN==1.

C29.2 Phenomenon

For the sake of receiving Sync Field to Frame-ID continuously, you must set RXE==0 until detecting Sync

Field, then Frame-ID is detected by automatic header reception, finally you should set RXE==1.

But when you use USART Loopback, hardware will set RXE==1,then fail to receive frame header. And

then, LIN communication does not work well.

C29.3 Workaround

Please avoid to use Loopback at operation mode3 by the setting of SMRn.MD[1:0]==3 and

EFERHn.INTLBEN==1.



mb86r11 errata sheet rev.1 - fujitsu global€¦ · · 2012-02-20mb86r11 errata sheet fujitsu...

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