mcp3202 - 2.7v dual channel 12-bit a/d converter with spi...

MCP32022.7V Dual Channel 12-Bit A/D Converter

with SPI Serial Interface

Features• 12-bit resolution• ±1 LSB maximum DNL• ±1 LSB maximum INL (MCP3202-B)• ±2 LSB maximum INL (MCP3202-C)• Analog inputs programmable as single-ended or

pseudo-differential pairs• On-chip sample and hold• SPI Serial Interface (Modes 0,0 and 1,1)• Single supply operation: 2.7V-5.5V• 100 ksps maximum sampling rate at VDD = 5V• 50 ksps maximum sampling rate at VDD = 2.7V• Low power CMOS technology• 500 nA typical standby current, 5 µA maximum• 550 µA maximum active current at 5V• Industrial temp range: -40°C to +85°C • 8-pin MSOP, PDIP, SOIC and TSSOP packages

Applications• Sensor Interface• Process Control• Data Acquisition• Battery Operated Systems

Functional Block Diagram

DescriptionThe MCP3202 is a successive approximation 12-bitanalog-to-digital (A/D) converter with on-board sampleand hold circuitry.

The MCP3202 is programmable to provide a singlepseudo-differential input pair or dual single-endedinputs. Differential Nonlinearity (DNL) is specified at±1 LSB, and Integral Nonlinearity (INL) is offered in±1 LSB (MCP3202-B) and ±2 LSB (MCP3202-C)versions.

Communication with the device is done using a simpleserial interface compatible with the SPI protocol. Thedevice is capable of conversion rates of up to 100 kspsat 5V and 50 ksps at 2.7V.

The MCP3202 operates over a broad voltage range,2.7V to 5.5V. Low-current design permits operation withtypical standby and active currents of only 500 nA and375 µA, respectively.

The MCP3202 is offered in 8-pin MSOP, PDIP, TSSOPand 150 mil SOIC packages.

Package Types

Comparator

Sampleand Hold

12-Bit SAR

DAC

Control Logic

CS/SHDN

VSSVDD

CLK DOUT

ShiftRegister

CH0 ChannelMux

Input

CH1

DIN

MC

P3202

1

234

8

765

CH0CH1VSS

CS/SHDN VDD/VREF

CLK

DOUT

DIN

PDIP, MSOP, SOIC, TSSOP

1999-2011 Microchip Technology Inc. DS21034F-page 1

MCP3202

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †VDD - VSS .........................................................................7.0VAll Inputs and Outputs w.r.t. VSS ............. -0.6V to VDD + 0.6VStorage Temperature.....................................-65°C to +150°CAmbient temperature with power applied.......-65°C to +150°CMaximum Junction Temperature (TJ) ......................... .+150°CESD Protection On All Pins (HBM) 4 kV

† Notice: Stresses above those listed under “AbsoluteMaximum Ratings” may cause permanent damage to thedevice. This is a stress rating only and functional operation ofthe device at those or any other conditions above thoseindicated in the operational listings of this specification is notimplied. Exposure to maximum rating conditions for extendedperiods may affect device reliability.

ELECTRICAL CHARACTERISTICSElectrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.5V, VSS = 0V,TA = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE.

Parameter Sym Min. Typ. Max. Units ConditionsConversion Rate:Conversion Time tCONV — — 12 clock

cyclesAnalog Input Sample Time tSAMPLE 1.5 clock

cycles

Throughput Rate fSAMPL ——

——

10050

kspsksps

VDD = VREF = 5VVDD = VREF = 2.7V

DC Accuracy:Resolution 12 bitsIntegral Nonlinearity INL —

—±0.75

±1±1±2

LSBLSB

MCP3202-BMCP3202-C

Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes overtemperature

Offset Error — ±1.25 ±3 LSBGain Error — ±1.25 ±5 LSB

Dynamic Performance:Total Harmonic Distortion THD — -82 — dB VIN = 0.1V to 4.9V@1 kHzSignal-to-Noise and Distortion (SINAD)

SINAD — 72 — dB VIN = 0.1V to 4.9V@1 kHz

Spurious Free Dynamic Range SFDR — 86 — dB VIN = 0.1V to 4.9V@1 kHzAnalog Inputs:

Input Voltage Range for CH0 or CH1 in Single-Ended Mode

VSS — VDD V

Input Voltage Range for IN+ in Pseudo-Differential Mode

IN+ IN- — VDD+IN- See Sections 3.1 and 4.1

Input Voltage Range for IN- in Pseudo-Differential Mode

IN- VSS-100 — VSS+100 mV See Sections 3.1 and 4.1

Leakage Current — .001 ±1 ASwitch Resistance RSS — 1 k — Ω See Figure 4-1Sample Capacitor CSAMPLE — 20 — pF See Figure 4-1

Digital Input/Output:Data Coding Format Straight BinaryHigh Level Input Voltage VIH 0.7 VDD — — VLow Level Input Voltage VIL — — 0.3 VDD VNote 1: This parameter is established by characterization and not 100% tested.

2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.

DS21034F-page 2 1999-2011 Microchip Technology Inc.

MCP3202

TEMPERATURE CHARACTERISTICS

High Level Output Voltage VOH 4.1 — — V IOH = -1 mA, VDD = 4.5VLow Level Output Voltage VOL — — 0.4 V IOL = 1 mA, VDD = 4.5VInput Leakage Current ILI -10 — 10 µA VIN = VSS or VDDOutput Leakage Current ILO -10 — 10 µA VOUT = VSS or VDDPin Capacitance(All Inputs/Outputs)

CIN, COUT — — 10 pF VDD = 5.0V (Note 1)TA = +25°C, f = 1 MHz

Timing Parameters:Clock Frequency fCLK — — 1.8

0.9MHzMHz

VDD = 5V (Note 2)VDD = 2.7V (Note 2)

Clock High Time tHI — 2 MHzClock Low Time tLO — 2 MHzCS Fall To First Rising CLK Edge

tSUCS 100 — — ns

Data Input Setup Time tSU 50 — — nsData Input Hold Time tHD 50 — — nsCLK Fall To Output Data Valid tDO — — 200 ns See Test Circuits, Figure 1-2CLK Fall To Output Enable tEN — — 200 ns See Test Circuits, Figure 1-2CS Rise To Output Disable tDIS — — 100 ns See Test Circuits, Figure 1-2

Note 1CS Disable Time tCSH 500 — — nsDOUT Rise Time tR — — 100 ns See Test Circuits, Figure 1-2

Note 1DOUT Fall Time tF — — 100 ns See Test Circuits, Figure 1-2

Note 1Power Requirements:Operating Voltage VDD 2.7 — 5.5 VOperating Current IDD — 375 550 µA VDD = 5.0V, DOUT unloadedStandby Current IDDS — 0.5 5 µA CS = VDD = 5.0V

Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature RangesSpecified Temperature Range TA -40 — +85 °COperating Temperature Range TA -40 — +85 °CStorage Temperature Range TA -65 — +150 °CThermal Package ResistancesThermal Resistance, 8L-MSOP JA — 211 — °C/WThermal Resistance, 8L-PDIP JA — 89.5 — °C/WThermal Resistance, 8L-SOIC JA — 149.5 — °C/WThermal Resistance, 8L-TSSOP JA — 139 — °C/W

ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.5V, VSS = 0V,TA = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE.

Parameter Sym Min. Typ. Max. Units Conditions

Note 1: This parameter is established by characterization and not 100% tested.2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,

especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.


MCP3202

FIGURE 1-1: Serial Timing.

CS

CLK

DIN MSB IN

tSU tHD

tSUCS

tCSH

tHI tLO

DOUT

tENtDO tR tF

LSBMSB OUT

tDIS

NULL BIT


MCP3202

FIGURE 1-2: Test Circuits.

VIH

TDIS

CS

DOUTWaveform 1*

DOUTWaveform 2†

90%

10%

* Waveform 1 is for an output with internal conditionssuch that the output is high, unless disabled by theoutput control.

† Waveform 2 is for an output with internal conditionssuch that the output is low, unless disabled by theoutput control.

Voltage Waveforms for tDIS

Test Point

1.4V

DOUT

Load Circuit for tR, tF, tDO

3 kΩ

CL = 100 pF

Test Point

DOUT

Load Circuit for tDIS and tEN

3 kΩ

100 pF

tDIS Waveform 2

tDIS Waveform 1

CS

CLK

DOUT

tEN

1 2

B11

Voltage Waveforms for tEN

tEN Waveform

VDD

VDD/2

VSS

3 4DOUT

tR

Voltage Waveforms for tR, tF

CLK

DOUT

tDO

Voltage Waveforms for tDO

tF

VOHVOL


MCP3202

2.0 TYPICAL PERFORMANCE CHARACTERISTICS

Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C.

FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate.

FIGURE 2-2: Integral Nonlinearity (INL) vs. VDD.

FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).

FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V).

FIGURE 2-5: Integral Nonlinearity (INL) vs. VDD.

FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V).

Note: The graphs provided following this note are a statistical summary based on a limited number of samplesand are provided for informational purposes only. The performance characteristics listed herein are nottested or guaranteed. In some graphs, the data presented may be outside the specified operating range(e.g., outside specified power supply range) and therefore outside the warranted range.

-1.0

-0.8-0.6

-0.4-0.2

0.00.2

0.40.6

0.81.0

0 25 50 75 100 125 150

INL (LSB)

Sample Rate (ksps)

Positive INL

Negative INL

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

3.0 3.5 4.0 4.5 5.0

VDD(V)

INL

(LSB

)

Positive INL

Negative INL

fSAMPLE = 100 ksps

-1.0-0.8

-0.6-0.4

-0.20.0

0.20.4

0.60.8

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

Digital Code

INL

(LSB

)

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0 20 40 60 80 100

Sample Rate (ksps)

INL

(LSB

)

VDD = 2.7V

Positive INL

Negative INL

-1.0

-0.8-0.6

-0.4

-0.20.0

0.2

0.4

0.60.8

1.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD(V)

INL

(LSB

)

Positive INL

Negative INL

fSAMPLE = 50 ksps

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

0 512 1024 1536 2048 2560 3072 3584 4096

Digital Code

INL

(LSB

)

VDD = 2.7VFSAMPLE = 50 ksps


MCP3202
FIGURE 2-7: Integral Nonlinearity (INL) vs. Temperature.

FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate.

FIGURE 2-9: Differential Nonlinearity (DNL) vs. VDD.

FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V).

FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V).

FIGURE 2-12: Differential Nonlinearity (DNL) vs. VDD.

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

-50 -25 0 25 50 75 100

Temperature (°C)

INL

(LSB

)

Positive INL

Negative INL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 25 50 75 100 125 150

Sample Rate (ksps)

DN

L (L

SB) Positive DNL

Negative DNL

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

3.0 3.5 4.0 4.5 5.0

VDD(V)

DN

L (L

SB)

Positive DNL

Negative DNL

fSAMPLE = 100 ksps

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

-50 -25 0 25 50 75 100

Temperature (°C)

INL

(LSB

)

Positive INL

VDD = 2.7VfSAMPLE = 50 ksps

Negative INL

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0 20 40 60 80 100

Sample Rate (ksps)

DN

L (L

SB)

VDD = 2.7V

Positive DNL

Negative DNL

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD(V)

DN

L (L

SB) Positive DNL

Negative DNL

fSAMPLE = 50 ksps


MCP3202
FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part).

FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature.

FIGURE 2-15: Gain Error vs. VDD.

FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V).

FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V).

FIGURE 2-18: Offset Error vs. VDD.

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

0 512 1024 1536 2048 2560 3072 3584 4096

Digital Code

DN

L (L

SB)

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

-50 -25 0 25 50 75 100

Temperature (°C)

DN

L (L

SB) Positive DNL

Negative DNL

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD(V)

Gai

n Er

ror (

LSB

)

fSAMPLE = 50 kspsfSAMPLE = 100 ksps

fSAMPLE = 10 ksps

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

0 512 1024 1536 2048 2560 3072 3584 4096

Digital Code

DN

L (L

SB)


-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

-50 -25 0 25 50 75 100

Temperature (°C)

DN

L (L

SB) Positive DNL


Negative DNL

0.00.20.40.60.81.01.21.41.61.82.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD(V)

Offs

et E

rror

(LSB

)

fSAMPLE = 10 ksps

fSAMPLE = 50 kspsfSAMPLE = 100 ksps


MCP3202
FIGURE 2-19: Gain Error vs. Temperature.

FIGURE 2-20: Signal-to-Noise Ratio (SNR) vs. Input Frequency.

FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency.

FIGURE 2-22: Offset Error vs. Temperature.

FIGURE 2-23: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency.

FIGURE 2-24: Signal-to-Noise and Distortion (SINAD) vs. Signal Level.

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

-50 -25 0 25 50 75 100

Temperature (°C)

Gai

n Er

ror

(LSB

)

VDD = 5VfSAMPLE = 100


0102030405060708090

100

1 10 100

Input Frequency (kHz)

SNR

(dB

)


VDD = 5VfSAMPLE = 100 ksps

-100-90-80-70-60-50-40-30-20-10

0

1 10 100


THD

(dB

)



0.00.20.40.60.81.01.21.41.61.82.0

-50 -25 0 25 50 75 100

Temperature (°C)

Offs

et E

rror

(LSB

) VDD = 5VfSAMPLE = 100 ksps


0

10

20

30

40

50

60

70

80

90

100

1 10 100


SIN

AD

(dB

)VDD = 2.7VfSAMPLE = 50 ksps


0

10

20

30

40

50

60

70

80

-40 -35 -30 -25 -20 -15 -10 -5 0

Input Signal Level (dB)

SIN

AD

(dB

)




MCP3202
FIGURE 2-25: Effective Number of Bits (ENOB) vs. VDD.

FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency.

FIGURE 2-27: Frequency Spectrum of 10 kHz input (Representative Part).

FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.

FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency.

FIGURE 2-30: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V).

9.0

9.5

10.0

10.5

11.0

11.5

12.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0

VDD (V)

ENO

B (r

ms)

fSAMPLE = 50ksps

fSAMPLE = 100 ksps

0102030405060708090

100

1 10 100


SFD

R (d

B)



-130-120-110-100-90-80-70-60-50-40-30-20-10

0

0 10000 20000 30000 40000 50000

Frequency (Hz)

Am

plitu

de (d

B)

VDD = 5VfSAMPLE = 100 kspsfINPUT = 9.985 kHz4096 points

8.0

8.5

9.0

9.5

10.0

10.5

11.0

11.5

12.0

1 10 100


ENO

B (r

ms)

VDD = 5VFSAMPLE = 100 ksps

VDD = 2.7VFSAMPLE = 50 ksps

-80

-70

-60

-50

-40

-30

-20

-10

0

1 10 100 1000 10000

Ripple Frequency (kHz)

Pow

er S

uppl

y R

ejec

tion

(dB

)

-130-120-110-100-90-80-70-60-50-40-30-20-10

0

0 5000 10000 15000 20000 25000

Frequency (Hz)

Am

plitu

de (d

B)

VDD = 2.7VfSAMPLE = 50 kspsfINPUT = 998.76 Hz4096 points


MCP3202
FIGURE 2-31: IDD vs. VDD.

FIGURE 2-32: IDD vs. Clock Frequency.

FIGURE 2-33: IDD vs. Temperature.

FIGURE 2-34: IDDS vs. VDD.

FIGURE 2-35: IDDS vs. Temperature.

FIGURE 2-36: Analog Input leakage current vs. Temperature.

0

50

100

150

200

250

300

350

400

450

500

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

IDD

(µA

) All points at FCLK = 1.8 MHz exceptat VDD = 2.5V, FCLK = 900 kHz

0

50

100

150

200

250

300

350

400

450

500

10 100 1000 10000

Clock Frequency (kHz)

IDD

(µA

)

VDD = 5V

VDD = 2.7V

0

50

100

150

200

250

300

350

400

450

500

-50 -25 0 25 50 75 100

Temperature (°C)

IDD

(µA

)

VDD = 5VFCLK = 1.8 MHz

VDD = 2.7VFCLK = 900 kHz

0

10

20

30

40

50

60

70

80

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

I DD

S (pA

)

CS = VDD

0.01

0.10

1.00

10.00

100.00

-50 -25 0 25 50 75 100

Temperature (°C)

I DD

S (n

A)

VDD = CS = 5V

0.0

0.20.4

0.60.8

1.0

1.21.4

1.61.8

2.0

-50 -25 0 25 50 75 100

Temperature (°C)

Ana

log

Inpu

t Lea

kage

(nA

)

VDD = 5VFCLK = 1.8 MHz


MCP3202

3.0 PIN DESCRIPTIONSThe descriptions of the pins are listed in Table 3.1.Additional descriptions of the device pins follows.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Analog Inputs (CH0/CH1)Analog inputs for channels 0 and 1 respectively. Thesechannels can be programmed to be used as twoindependent channels in Single-Ended mode or as asingle pseudo-differential input where one channel isIN+ and one channel is IN-. See Section 5.0 “SerialCommunications” for information on programmingthe channel configuration.

3.2 Chip Select/Shutdown (CS/SHDN)The CS/SHDN pin is used to initiate communicationwith the device when pulled low and will end aconversion and put the device in low power standbywhen pulled high. The CS/SHDN pin must be pulledhigh between conversions.

3.3 Serial Clock (CLK)The SPI clock pin is used to initiate a conversion and toclock out each bit of the conversion as it takes place.See Section 6.2 “Maintaining Minimum ClockSpeed” for constraints on clock speed.

3.4 Serial Data Input (DIN)The SPI port serial data input pin is used to clock ininput channel configuration data.

3.5 Serial Data Output (DOUT)The SPI serial data output pin is used to shift out theresults of the A/D conversion. Data will always changeon the falling edge of each clock as the conversiontakes place.

MSOP, PDIP, SOIC, TSSOP Name Function

1 CS/SHDN Chip Select/Shutdown Input

2 CH0 Channel 0 Analog Input

3 CH1 Channel 1 Analog Input

4 VSS Ground

5 DIN Serial Data In

6 DOUT Serial Data Out

7 CLK Serial Clock

8 VDD/VREF +2.7V to 5.5V Power Supply and Reference Voltage Input


MCP3202

4.0 DEVICE OPERATIONThe MCP3202 A/D converter employs a conventionalSAR architecture. With this architecture, a sample isacquired on an internal sample/hold capacitor for1.5 clock cycles starting on the second rising edge ofthe serial clock after the start bit has been received.Following this sample time, the input switch of the con-verter opens and the device uses the collected chargeon the internal sample and hold capacitor to produce aserial 12-bit digital output code.

Conversion rates of 100 ksps are possible on theMCP3202. See Section 6.2 “Maintaining MinimumClock Speed” for information on minimum clock rates.

Communication with the device is done using a 3-wireSPI-compatible interface.

4.1 Analog InputsThe MCP3202 device offers the choice of using theanalog input channels configured as two single-endedinputs or a single pseudo-differential input. Configura-tion is done as part of the serial command before eachconversion begins. When used in the pseudo-differen-tial mode, CH0 and CH1 are programmed as the IN+and IN- inputs as part of the command string transmit-ted to the device. The IN+ input can range from IN- toVREF (VDD + IN-). The IN- input is limited to ±100 mVfrom the VSS rail. The IN- input can be used to cancelsmall signal common-mode noise which is present onboth the IN+ and IN- inputs.

For the A/D converter to meet specification, the chargeholding capacitor (CSAMPLE) must be given enoughtime to acquire a 12-bit accurate voltage level duringthe 1.5 clock cycle sampling period. The analog inputmodel is shown in Figure 4-1.

In this diagram, it is shown that the source impedance(RS) adds to the internal sampling switch (RSS) imped-ance, directly affecting the time that is required tocharge the capacitor, CSAMPLE. Consequently, largersource impedances increase the offset, gain, andintegral linearity errors of the conversion.

Ideally, the impedance of the signal source should benear zero. This is achievable with an operationalamplifier such as the MCP601 which has a closed loopoutput impedance of tens of ohms. The adverse affectsof higher source impedances are shown in Figure 4-2.

When operating in the pseudo-differential mode, if thevoltage level of IN+ is equal to or less than IN-, theresultant code will be 000h. If the voltage at IN+ is equalto or greater than [VDD+(IN-)] -1 LSB, then the outputcode will be FFFh. If the voltage level at IN- is morethan 1 LSB below VSS, then the voltage level at the IN+input will have to go below VSS to see the 000h outputcode. Conversely, if IN- is more than 1 LSB above VSS,then the FFFh code will not be seen unless the IN+input level goes above VDD level.

4.2 Digital Output CodeThe digital output code produced by an A/D converteris a function of the input signal and the reference volt-age. For the MCP3202, VDD is used as the referencevoltage. As the VDD level is reduced, the LSB size isreduced accordingly. The theoretical digital output codeproduced by the A/D converter is shown below.

EQUATION 4-1:

Digital Output Code4096•VIN

VDD-----------------------=

where:

VIN = analog input voltageVDD = supply voltage


MCP3202

FIGURE 4-1: Analog Input Model.

FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions.

CPINVA

RSS CHx

7 pF

VT = 0.6V

VT= 0.6VILEAKAGE

SamplingSwitch

SS RS = 1 kW

CSAMPLE= DAC capacitance

VSS

VDD

= 20 pF±1 nA

LegendVA = signal source

RSS = source impedanceCHx = input channel padCPIN = input pin capacitance

VT = threshold voltageILEAKAGE = leakage current at the pin due to various junctions

SS = sampling switchRS = sampling switch resistor

CSAMPLE = sample/hold capacitance

0.00.2

0.40.6

0.81.01.2

1.41.6

1.82.0

100 1000 10000

Input Resistance (Ohms)

Clo

ck F

requ

ency

(MH

z) VDD = 5V

VDD = 2.7V


MCP3202

5.0 SERIAL COMMUNICATIONS

5.1 OverviewCommunication with the MCP3202 is done using astandard SPI-compatible serial interface. Initiatingcommunication with the device is done by bringing theCS line low. See Figure 5-1. If the device was poweredup with the CS pin low, it must be brought high andback low to initiate communication. The first clockreceived with CS low and DIN high will constitute a startbit. The SGL/DIFF bit and the ODD/SIGN bit follow thestart bit and are used to select the input channel config-uration. The SGL/DIFF is used to select Single-Endedor Pseudo-Differential mode. The ODD/SIGN bitselects which channel is used in Single-Ended mode,and is used to determine polarity in Pseudo-Differentialmode. Following the ODD/SIGN bit, the MSBF bit istransmitted to and is used to enable the LSB first formatfor the device. If the MSBF bit is high, then the data willcome from the device in MSB first format and any fur-ther clocks with CS low will cause the device to outputzeros. If the MSBF bit is low, then the device will outputthe converted word LSB first after the word has beentransmitted in the MSB first format. See Figure 5-2.Table 5-1 shows the configuration bits for theMCP3202. The device will begin to sample the analoginput on the second rising edge of the clock, after thestart bit has been received. The sample period will endon the falling edge of the third clock following the startbit.

On the falling edge of the clock for the MSBF bit, thedevice will output a low null bit. The next sequential12 clocks will output the result of the conversion withMSB first as shown in Figure 5-1. Data is always outputfrom the device on the falling edge of the clock. If all12 data bits have been transmitted and the device con-tinues to receive clocks while the CS is held low, (andMSBF = 1), the device will output the conversion resultLSB first as shown in Figure 5-2. If more clocks are pro-vided to the device while CS is still low (after the LSBfirst data has been transmitted), the device will clockout zeros indefinitely.

If necessary, it is possible to bring CS low and clock inleading zeros on the DIN line before the start bit. This isoften done when dealing with microcontroller-basedSPI ports that must send 8 bits at a time. Refer toSection 6.1 “Using the MCP3202 with Microcon-troller (MCU) SPI Ports” for more details on using theMCP3202 devices with hardware SPI ports.

FIGURE 5-1: Communication with the MCP3202 using MSB first format only.

TABLE 5-1: CONFIGURATION BITS FOR THE MCP3202

Config Bits

ChannelSelection GND

SGL/ DIFF

ODD/ SIGN 0 1

Single-Ended Mode

1 0 + — -1 1 — + -

Pseudo-Differential

Mode

0 0 IN+ IN-0 1 IN- IN+

CS

CLK

DIN

DOUT

MS

HI-Z NullBit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*

HI-Z

tSAMPLE

tCONV

SGL/DIFF

Start

tCYC

tCSH

tCYC

* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zerosindefinitely. See Figure 5-2 below for details on obtaining LSB first data.** tDATA: during this time, the bias current and the comparator power down while the reference input becomes ahigh-impedance node, leaving the CLK running to clock out the LSB-first data or zeros.

tDATA**

tSUCS

ODD/SIGN BF Don’t Care SGL/

DIFFStart ODD/

SIGN


MCP3202

FIGURE 5-2: Communication with MCP3202 using LSB first format.

NullBit

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11

CS

CLK

DOUTHI-Z HI-Z

(MSB)tCONV tDATA **

Power Down

tSAMPLE

DIN

tCYC

tCSH

* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zerosindefinitely.

** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes ahigh-impedance node, leaving the CLK running to clock out LSB first data or zeroes.

tSUCSO

DD

/S

IGN

Star

t

SGL/

DIF

F

MSB

F

Don’t Care

*


MCP3202

6.0 APPLICATIONS INFORMATION

6.1 Using the MCP3202 with Microcontroller (MCU) SPI Ports

With most microcontroller SPI ports, it is required tosend groups of eight bits. It is also required that themicrocontroller SPI port be configured to clock out dataon the falling edge of clock and latch data in onthe rising edge. Depending on how communicationroutines are used, it is very possible that the number ofclocks required for communication will not be a multipleof eight. Therefore, it may be necessary for the MCU tosend more clocks than are actually required. This isusually done by sending ‘leading zeros’ before the startbit, which are ignored by the device.

As an example, Figure 6-1 and Figure 6-2 show howthe MCP3202 can be interfaced to a MCU with ahardware SPI port.

Figure 6-1 depicts the operation shown in SPI Mode0,0, which requires that the SCLK from the MCU idlesin the ‘low’ state, while Figure 6-2 shows the similarcase of SPI Mode 1,1 where the clock idles in the ‘high’state.

As shown in Figure 6-1, the first byte transmitted to theA/D converter contains seven leading zeros before thestart bit. Arranging the leading zeros this way producesthe output 12 bits to fall in positions easily manipulatedby the MCU. The MSB is clocked out of the A/D con-verter on the falling edge of clock number 12. After thesecond eight clocks have been sent to the device, theMCU receive buffer will contain three unknown bits (theoutput is at high-impedance until the null bit is clockedout), the null bit and the highest order four bits of theconversion. After the third byte has been sent to thedevice, the receive register will contain the lowest ordereight bits of the conversion results. Easier manipulationof the converted data can be obtained by using thismethod.

FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).

FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

CS

SCLK

DIN

X = Don’t Care Bits

17 18 19 20 21 22 23 24

DOUTNULLBIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0HI-Z

MCU latches data from A/D converter

Data is clocked out ofA/D converter on falling edges

on rising edges of SCLK

MS

BF

Don’t Care

OD

D/

SIG

N

Start

X X X X X X X X X X X X X X X X X X

B7 B6 B5 B4 B3 B2 B1 B0B11 B10 B9 B80X X X X X X X X X X X

1

StartBit

(Null)

MCU Transmitted Data(Aligned with falling

edge of clock)

MCU Received Data(Aligned with rising

edge of clock)

MSBF

SGL/DIFF

X X SGL/DIFF

ODD/SIGN

Data stored into MCU receive register after transmission of first 8 bits

Data stored into MCU receiveregister after transmission ofsecond 8 bits

Data stored into MCU receiveregister after transmission oflast 8 bits

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

CS

SCLK

DIN

X = Don’t Care Bits

17 18 19 20 21 22 23 24

DOUT

Don’t Care

NULLBIT

B11 B10 B9 B8 B6 B5 B4 B3 B2 B1 B0HI-Z

0 0 0 0 0 0 X X X X X X X X X X X X X

B7 B6 B5 B4 B3 B2 B1 B0B11 B10 B9 B80X X X X X X X X X X X

MCU latches data from A/D converteron rising edges of SCLK

Data is clocked out ofA/D converter on falling edges

StartBit

(Null)

Start

MCU Transmitted Data(Aligned with falling

edge of clock)

MCU Received Data(Aligned with rising

edge of clock)

B7

1

SG

L/D

IFF

MS

BF

OD

D/

SIG

N

0 SGL/DIFF

ODD/SIGN MSBF

Data stored into MCU receiveregister after transmission offirst 8 bits

Data stored into MCU receiveregister after transmission ofsecond 8 bits

Data stored into MCU receiveregister after transmission oflast 8 bits


MCP3202
6.2 Maintaining Minimum Clock SpeedWhen the MCP3202 initiates the sample period, chargeis stored on the sample capacitor. When the sampleperiod is complete, the device converts one bit for eachclock that is received. It is important for the user to notethat a slow clock rate will allow charge to bleed off thesample cap while the conversion is taking place. At85°C (worst case condition), the part will maintainproper charge on the sample capacitor for at least1.2 ms after the sample period has ended. This meansthat the time between the end of the sample period andthe time that all 12 data bits have been clocked outmust not exceed 1.2 ms (effective clock frequency of10 kHz). Failure to meet this criteria may inducelinearity errors into the conversion outside the ratedspecifications. It should be noted that during the entireconversion cycle, the A/D converter does not require aconstant clock speed or duty cycle, as long as all timingspecifications are met.
6.3 Buffering/Filtering the Analog Inputs

If the signal source for the A/D converter is not a low-impedance source, it will have to be buffered orinaccurate conversion results may occur. It is alsorecommended that a filter be used to eliminate anysignals that may be aliased back into the conversionresults. This is illustrated in Figure 6-3 below where anop amp is used to drive the analog input of theMCP3202. This amplifier provides a low-impedanceoutput for the converter input and a low-pass filter,which eliminates unwanted high frequency noise.

Low-pass (anti-aliasing) filters can be designed usingMicrochip’s interactive FilterLab® software. FilterLabwill calculate capacitor and resistor values, as well as,determine the number of poles that are required for theapplication. For more information on filtering signals,see the application note AN699 “Anti-Aliasing AnalogFilters for Data Acquisition Systems”.”

FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti-aliasing filter for the signal being converted by the MCP3202.

6.4 Layout ConsiderationsWhen laying out a printed circuit board for use withanalog components, care should be taken to reducenoise wherever possible. A bypass capacitor shouldalways be used with this device and should be placedas close as possible to the device pin. A bypasscapacitor value of 0.1 µF is recommended.

Digital and analog traces should be separated as muchas possible on the board and no traces should rununderneath the device or the bypass capacitor. Extraprecautions should be taken to keep traces with highfrequency signals (such as clock lines) as far aspossible from analog traces.

Use of an analog ground plane is recommended inorder to keep the ground potential the same for alldevices on the board. Providing VDD connections todevices in a “star” configuration can also reduce noiseby eliminating current return paths and associatederrors. See Figure 6-4. For more information on layouttips when using A/D converters, refer to AN688 “LayoutTips for 12-Bit A/D Converter Applications” (DS00688).

FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths.

MCP3202

VDD

10 µF

IN-

IN+-+VIN

C1

C2

0.1 µFMCP601R1

R2

R3R4

VDDConnection

Device 1

Device 2Device 3

Device 4


MCP3202

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

XXXXXXXXXXXXXNNN

YYWW

NNN

8-Lead SOIC (3.90 mm) Example

3202-BI SN 11303

8-Lead PDIP (300 mil) Example

8-Lead MSOP (3x3 mm) Example

3202-B I/P 256 1130

3

3202CI 130256


MCP3202
Package Marking Information (Continued)
Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

8-Lead TSSOP (4.4 mm) Example

202C1130256


MCP3202

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging


MCP3202



MCP3202

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MCP3202



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MCP3202



MCP3202

APPENDIX A: REVISION HISTORY

Revision F (November 2011)Updated Product Identification SystemCorrected MSOP package marking drawings.

Updated Package Specification Drawings with newadditions.

Revision E (December 2008)Updates to packaging outline drawings.

Revision D (December 2006)Updates to packaging outline drawings.

Revision C (August 2001)Undocumented changes.

Revision B (June 2000)Undocumented changes.

Revision A (August 1999)Initial release of this document.


MCP3202

PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX

PackageTemperatureRange

Device

Device MCP3202: 12-Bit Serial A/d ConverterMCP3202T: 12-Bit Serial A/D Converter (Tape and Reel)

(MSOP, SOIC and TSSOP package only)

Performance Grade: B = ±1 LSB INL (TSSOP not available)C = ±2 LSB INL

Temperature Range I = -40C to +85C (Industrial)E = -40C to +125C (Extended)

Package MS = Plastic Micro Small Outline (MSOP), 8-LeadP = Plastic DIP (300 mil Body), 8-LeadSN = Plastic SOIC (150 mil Body), 8-LeadST = TSSOP (4.4 mm Body), 8-Lead (C Grade only)

Examples:

a) MCP3202-CI/MS: Industrial temperature, 8LD MSOP package.

b) MCP3202-BI/P: B Performance grade,Industrial temperature,8LD PDIP package

c) MCP3202-BI/SN: C Performance grade,Industrial temperature,8LD SOIC package

d) MCP3202T-BI/SN: Tape and Reel,B Performance grade,Industrial temperature.,8LD SOIC package

e) MCP3202T-CI/ST: Tape and Reel,C Performance grade,Industrial temperature,8LD TSSOP package.

PerformanceGrade

X


MCP3202
NOTES:

Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

1999-2011 Microchip Technology Inc.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 1999-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-757-7

DS21034F-page 33

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


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