md.ali vlsi resume
TRANSCRIPT
MD.ALI
+91 88612 46782
OBJECTIVE
Seeking work in a company where my technical and interpretational skills can be utilized for the growth and success of the company while offering me the opportunity to explore new avenues in my career field.
ACADEMIC QUALIFICATIONS
Degree and Date Institute Major and Specialization
Percentage / Aggregate
Advanced Diploma in ASIC Design
(Aug 2010)
RV VLSI Design CenterBangalore VLSI COMPLETED
Bachelor of Engineering(May 2009)
New Horizon College of Engineering,
Bangalore(Karnataka)
Electronics & Communication
Engineering53.00
12th Vardamaan Mahaveer College
Physics, Chemistry, Mathematics
73.66
10th Adarsh High school PCM 56.28
CORE COMPETENCIES
Understanding of the VLSI ASIC design flow.
Knowledge of Verilog as a Hardware Description Language and of HDL
Simulators, Mentor Graphics QuestaSim and Synopsys VCS.
Knowledge of Design Verification through SystemVerilog.
Knowledge of Synthesis and Static Timing Analysis and related tools,
Synopsys PrimeTime and Synopsys Design Compiler.
Basic knowledge of Linux and Vi Editor.
Basic knowledge of Perl and C
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TRAINING AT RV-VLSI
Advanced Diploma in ASIC Design
A good understanding of the ASIC design flow was acquired.
Linux, Vi and Perl : A basic understanding of the Linux environment and
command line interface in Linux was introduced. Usage and importance of Vi
Editor was introduced. Perl as a powerful language for textual data manipulation
was introduced. The importance of Regular Expressions for data extraction was
understood.
Logic Design : Important concepts pertaining to logic design was learnt. Key learning includes
Understanding, designing and application of Mealy and Moore machine models.
Flip-flop and latch fundamentals. Metastability issues and the significance of FIFO in matching two
asynchronous systems. Verilog HDL and RTL coding: Basic understanding and importance of HDL was
understood. The fundamentals of Verilog as a industry standard HDL was taught. The significance of RTL specific coding was understood.
Verification using SystemVerilog: The importance of verification in the ASIC design flow was learnt. SystemVerilog as a HVL was understood. Difference between HVL and HDLs was brought out. SystemVerilog based concepts such as OOP, mailbox, semaphores etc., was introduced.
Synthesis: The process of Synthesis was introduced. A conceptual understanding of timing requirements and design constraints was learnt. RTL codes of UART and i2c were constrained and synthesized so as to get a real feel as to how to go about the Synthesis process.
Static Timing Analysis: The importance of and the role played by STA was understood. Gate level netlist are analyzed to get a better understanding of Static Timing Analysis.
Device Physics and CMOS Full Custom/Semi Custom Flow
Physical Design-Floorplanning, routing, CTS, IR Drop Analysis.
Physical Verification- DRC, LVS, PEX.
CMOS fabrication process and exposur
PROJECTS AT RV-VLSI
RC circuit & inverter circuit simulation and layout designTools used : Virtuoso, Spectre and IC Studio
: Timing delays and the effects of resistance and capacitance on timing delays was understood. Simulation of the RC circuit was
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done. Inverter with P-FET and N-FET with different L, W and LOAD was designed and tested to understand the driving capability and effect on Rise time and fall time. The layout of inverter was designed based upon JAZZ foundry by using the tool IC Studio and DRC and LVS was done.
Floor plan, Placement, CTS, and Routing of I2CTools used : Astro
: Different Core Parameters, Power and Ground ring and straps were created and its location were defined, Standard cell placement, Congestion, CTS, Routing and its related optimization, DRC,LVS,PEX Analysis were done.
RTL design of 16550 UART TransmitterTools used : VCS, QuestaSim, Modelsim, LedaDescription : UART 16550 Transmitter was designed using Verilog-RTL based
on the provided specifications. The functionality of same was verified using Verilog-RTL code.
Synthesis and Static Timing Analysis of UART and I2C.Objective : To synthesize the RTL code by applying the constrains as per the
given Specifications and write out the Gate Level Netlist and to close the Timing.
Tools Used : Design Compiler, Prime Time.Key Findings: Learnt the effect of Transition, Load, Operating conditions, Wire load model, on the cell delay. The effect of different constrains on the Gate Level Netlist. Learnt how the sizing the cell, adding buffers affects while fixing the setup and hold violations.
EDA TOOLS USED AT RV VLSI
HDL, HVL Simulation Mentor Graphics QuestaSim, Synopsys VCS ,ModelsimSynthesis Synopsys Design CompilerStatic Timing Analysis Synopsys PrimeTimeAnalog circuit simulation Cadence Virtuoso, Cadence SpectrePhysical design Ic studioPlace and route Astro
ENGINEERING PROJECTTitle : MC 8051 Based Vehicle Diagnostic System.
Tools : Keil µvision.
Brief Description: A vehicle diagnostic system is an electronic device installed in a vehicle to
diagnose the different parameter of the vehicles like ignition, airbag, brake and
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engine temperature. If any failure occurs it will detect and give the information
by displaying. Suppose if ignition is failure it will show on the display as “ignition
failure” and engine will not start. By chance if brake will failure and vehicle is
running it will automatic show that brake is failure. In case of an accident the
airbag will open in Nano second and save the life. Similarly if engine temperature
increases beyond the set value it will give a beep sound and after three minute it
automatic stops the engine until temperature goes below.
CO CURRICULAR ACTIVITIES
Coordinating Member of the National Conference on “Current trends in Electronics & Telecommunication”, Department of Electronics and Communication, NHCE.
Coordinator of the inauguration of The Institute of Electronics and Telecommunication Engineers’ Forum, Department of Electronics and Communication, NHCE.
One day seminar on embedded system, Event Management in college festivals, Participation in cultural events.
Active participation in College activities like Library Week Quiz.
PERSONAL DETAIL
Sex : MaleCitizenship : IndianDate of Birth : 01 JAN 1984Languages known : Fluent in English, Hindi and UrduPermanent Address : Baridargah, Bihar Sharif, Nalanda - 803101Contact Address : Maqbol Jan, 191/117, 31st Cross, Tilak Nagar, Bangalore Contact No : +91 8861246782
PASSPORT DETAILS
Name as upon Passport : MOHAMMED ALIPassport Number : H7137636Date of Issue : 31 Aug 2009Expiry Date : 30 Aug 2019Place of Issue : Bangalore
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