mechanical design considerations for area array solder joints

212 IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 16, NO. 3, MAY 1993

Mechanical Design Considerations for Area Array Solder Joints Peter Borgesen, Che-Yu Li, Member, IEEE, and H.D. Conway

Abstract-Concurrent engineering often requires mechanical reliability to be traded off against a number of other criteria. Rather than simple optimization, mechanical design, therefore, usually relies, explicitly or implicitly, on the assessment of the relative merits of a number of alternatives. However, the evaluation of a large number of designs by finite element and damage integral methods would, at best, be extremely cumbersome. The present paper describes design tools based on elastic stress analysis for rapid assessment of area array assembly designs in terms of mechanical reliability. Examples in the discussion illustrate various means of improving the reliability of such assemblies.

I. INTRODUCTION LIP-CHIP technology has been successfully applied for F more than two decades [l], [2] and mechanical opti-

mization pursued for at least as long [3]. However, current trends suggest requirements for 1 / 0 densities in excess of 2000 per chip by the end of this century. New high performance assemblies will, therefore, most likely include both smaller joints and pitch, as well as larger array dimensions than ever before. At the same time, an increasing emphasis on cost at all levels may lead to the development of approaches based on alternative metallurgies, processing, and design. Area arrays of solder joints are also found at higher packaging levels, such as for attachment of chip carriers to cards, where arrays and joints may be much larger and the metallurgy may be different. Mechanical design and reliability engineers will, therefore, continuously be faced with new challenges.

Concurrent engineering requires the evaluation of trade-offs between mechanical reliability and a number of other factors, such as cost, electrical and thermal performance, manufactura- bility and compatibility with other package components, and processing hierarchy. Even a moderate change in design may thus involve the assessment of the relative merits of a very large number of different options. The present paper addresses the mechanical design tools for such applications.

The reliability of interconnects is strongly influenced by thermal excursions during processing and service. Here, we shall be specifically concerned with the behavior of area array solder joints. A n example to be considered is that of

Manuscript received February 22, 1993. This work was supported by grants from IBM, the Semiconductor Research Corporation, and the Industry-Cornell University Alliance for Electronic Packaging.

P. B~rgesen and C.-Y. Li are with the Department of Materials Science and Engineering, Cornell University, Ithaca, NY 14853.

H. D. Conway is with the Department of Theoretical and Applied Mechan- ics, Cornell University, Ithaca, NY 14853.

IEEE Log Number 9208616.

flip-chip solder joints connecting arrays of 4.5 mil (114 pm) diameter contact pads on a Si chip and a ceramic substrate. During service such an assembly is often heated to 85OC or more, and differences in coefficients of thermal expansion (CTE’s) may lead to appreciable loads on the individual components. As assembly dimensions become larger these loads will, of course, also increase. Simple estimates are often based on the assumption that chip and substrate expand freely, all of the mismatch being absorbed by the elastic and plastic deformation of the solder joints, but this has been shown to lead to very exaggerated estimates of the resulting loads and displacements [4], [5]. Nevertheless, loads may be relaxed through plastic flow in the solder joints during service [6], so that “reverse” loads then build up during subsequent cool down. In any case, fatigue of the solder joints due to repeated thermal excursions is of obvious concern for long term reliability.

Finite element modeling provides a particularly powerful tool for the detailed analysis of stress distributions. However, the deformation of an individual solder joint in an area array depends uniquely on the loads exerted on the chip and substrate by all of the other joints as well [4], [5]. The accurate modeling of the simultaneous deformation of a complete area array as a function of temperature and time thus puts great demands on computer capacity, and parametric studies are, at best, extremely cumbersome. Rather, we propose applying an initial figure-of-merit level of analysis before proceeding to more detailed stress analysis of a few selected designs.

11. ANALYSIS

In the present paper we rely on the assumption that the instantaneous fatigue crack growth rate is determined solely by the temperature and local stress distribution at the time. In fact, we shall take the view that cracks in a solder joint will tend to grow in a direction perpendicular to the largest tensile stress. Indeed, a damage integral approach based on such an assumption was successfully applied to the low cycle thermal fatigue of solder in simpler geometries [6]. For the comparison of mechanical design alternatives we, therefore, define a figure-of-merit in terms of the largest tensile stress in the solder joint in question.

The design variables addressed in the following include size, composition, and shape (stiffness) of the joints, size and pitch of the array, as well as stiffness and CTE of chip and substrate, or chip carrier and board. We shall calculate here the shapes of the solder joints in area arrays under various conditions. Based on an elastic-plastic approximation we then

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B0RGESEN et al.: DESIGN CONSIDERATIONS FOR SOLDER JOINTS 273

evaluate the largest tensile stress in the individual joints. For this purpose we calculate the forces and moments, and from them both shear and tensile stresses, in the elastic regime. In the plastic regime the largest tensile stress is seen to equal the uniaxial flow stress. For a comparison of designs we thus argue that a faster stress increase in the elastic regime leads to a faster increase in drack growth rate there, whereas the crack growth rate in the plastic regime depends only on temperature and flow stress. For some solders, such as near-eutectic Pb/Sn solders, the flow stress is actually somewhat sensitive to the plastic strain rate, which depends on the heating rate and interactions among assembly components. However, we shall argue that this is a minor effect at the present level of analysis.

A. Solder Joint Shape Calculation

In general, the solder joint shapes are determined by the corresponding solder volumes, the contact pad sizes and shapes, and the forces exerted upon the joints during reflow. The forces again depend on the weight of the chip, the pressure in the reflow chamber, interactions between joints, and externally applied loads. In the following, we shall be particularly concerned with interactions between joints because of variations in solder volume within a given array. We shall ignore solder joint shrinkage and shape changes during the subsequent cool down.

The equilibrium shape of a liquid solder drop may be described by the Laplace-Young equation

where A P is the pressure difference across the solder surface, y is the surface tension, and RI and R2 are the radii of surface curvature in two orthogonal directions. The surface free energy of the drop is simply y integrated over the area of the drop. Incorporating the effect of A P into the potential function [7] we then obtain an effective potential energy, which we minimize by the Euler-Lagrange method. For the following examples, we solve the Euler-Lagrange equation numerically [7]. This provides the shape of a solder joint for given boundary conditions (shape, size, and relative position of contact pads), and hence, the corresponding surface free energy.

In an array of solder joints of varying volume (constant pad sizes), for example, the individual joint is exposed to a vertical load due to the presence of the other joints. Mathematically, this is equivalent to varying the weight of the chip. By mapping out the free energy of the drop as a function of pad position it was shown elsewhere [7] that the restoring forces towards the minimum energy position exerted by a liquid solder on two metal pads can be well approximated by linear springs, where the equilibrium heights and spring constants depend on pad size and solder volume. The vertical force produced by a given solder joint during reflow is thus proportional to that joint’s normal displacement from its equilibrium (“load free”) height. During reflow of an array of solder joints of varying volume (constant pad sizes) the loads on a given joint are found by balancing the equations for the total force and

moments on, say, the chip [8]:

F = k,, (& - h:,) + Fext = 0

M” = k,Y,, (h, - h:,) = 0 (2b)

MY = k,,IT,, (hZ3 - hf3) = 0 (2c)

( 2 4 293

,J

2 1 3

where Fext accounts for the weight of the chip and any other external force. 2 and index the individual joints, k,, are the spring constants corresponding to the individual solder volumes, x,, and yZ3 are the distances to the y-axis and x- axis, respectively, of a coordinate system in the plane of the substrate, and hf, are the equilibrium heights of the individual joints. Equation (2a)-(2c) can then be solved for the actual heights, h,, .

B. Force and Moment on Solder Joint

In general, heating of a chip and a substrate connected by an array of solder joints lead to the development of forces and moments on each of these components because of differences between the CTE’s. As a result, solder joints are sheared, bent, and “stretched,” the chip is bent and stretched, and the substrate bent and compressed. While chip and substrate deform only elastically, sufficient heating will of course also lead to plastic deformation of the solder joints. In the elastic regime, continuity of the assembly ensures the matching of displacements and curvature at interfaces, leading to a system of simultaneous linear equations for the forces and moments of interest. From these we may then evaluate the stress distributions in the individual solder joints and, in particular, the largest tensile stress. In the plastic regime we shall simple take the largest tensile stress to equal the flow stress (see the following).

For the use in the following we shall first extend the elastic analysis of Conway et al. [5] to the more general case where solder joint spacings and shapes may vary within an array. The effects of thermal expansion of the joints are still ignored. We shall briefly consider the validity of this in the discussion.

Defining a coordinate system with x- and y-axis in the plane of the substrate and the z-axis normal to that (see the following also), the thermal expansion of an area array (Fig. 1) is evaluated in the 2-2 and y-z planes separately, using beam theory, and the resulting forces and moments then added vectorically. We first consider the two-dimensional deformation of a pair of “beams” (Fig. 2) of width w and thicknesses t,; and ts&,

respectively, connected by a symmetric row of (2n + 1) solder joints, and exposed to a temperature rise, T. Because of the symmetry, the center joint is not loaded, and we need only consider a total of n joints. The spacing between the ith and the ( i - 1)th joints is denoted by Li.

Consider the ith solder joint. As chip and substrate expand differently during heating, the top and bottom of the joint are displaced relative to each other, leading to bending moments and a shear force on the joint and, of course, on chip and substrate. The shear force, Fi, and moment, M:, on the chip are taken to be positive as sketched in Fig. 3. The simultaneous


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L _ _ I - - 7

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Fig. 3 Schematic of single joint in assembly with displacements .rf and x b , and resulting force, F , and moment, .U‘, on chip.

Flg I SchcmdtlCs of d “filled” (squdre) drea arrdy

to an effective shortening of the horizontal projection of the chip mid-plane However, as shown elsewhere [5] this

displacement of a point on the chip surface relative to a corresponding point at the mid-plane. Thus only the latter contribution is included in the following.

Now, the beam segment between the qth and ( q - 1)th joints is compressed by the total shear force

- -L IP 4

chip I I effect remains negligible as compared to the simultaneous I ( ’ ) thftsl

f ti””

/ / //// /’ / / / / / / / / / / ’ 1-2 1 - 1

sub

/ / / / / / / / / / / / ,’ / / / / n

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leading to a shortening of the segment by ALq = S,L,/A,,E,,. A,, = wthl is the cross-sectional area of the beam. Summed over all beam segments between the zth joint and the neutral point this contribution to X: then becomes

1 ri

x; c = (1/‘%,E51) Lq FJ (4) q = l j = q

Fig. 2. Schematics of part of assembly, beam approximation. Si-chip, thickness tsi; ceramic substrate, thickness t,,,,,; solder joints, height h, ; beam, width 71%. (a) Side view. (b) Top view. while the contribution due to thermal expansion of the same

moment, M:, on the substrate follows from these two and rotational equilibrium:

M: = -Fills + M: (3)

where h, is the height of the solder joints. We now define a three-dimensional coordinate system with

the y-axis along the axis of the ith solder joint towards the substrate, the origin at the chip surface, and the Lc-axis along the surface in the direction of the thermal displacement of that origin (Fig. 3). Within this coordinate system, we shall now consider separately the displacements along the .x-axis and changes in the slopes, y’ = dy/d .c , of various interfaces in terms of the moments and forces.

First we describe the displacement, X l , of the top of the solder joint in terms of the deformation of the chip. X,? is then composed of a number of contributions. For one thing, the chip is compressed in the 2-direction by the resulting shear forces at various points along the length, counteracting the simultaneous thermal expansion. Furthermore, bending of the chip leads

segments is

7

~ 2 t . t = asiT Lq (5 ) y = l

and T is the temperature increase. At the ith joint, the chip surface is displaced by -ylt,;/2

relative to the chip centerline, where y: is the slope of the chip at that point. Now, at the neutral point, the chip surface, of course, remains parallel to the x-axis, i.e., the slope y: = 0. From beam theory [9], bending of the segment length Ly due to the total bending moment, M,, on the chip at the qth joint will result in an increase, MqLq/EsiIsi, in the slope of the chip surface relative to that at the (q-1)th joint. E,; is Young’s modulus and Is; = iut:;/12 is the moment of inertia. M, is the sum of the moments (Ad; +Fjt, i /2) at the joints j = q , . . . , n, so the total slope, y:, of the chip surface at the joint z becomes

I B0RGESEN et al.: DESIGN CONSIDERATIONS FOR SOLDER JOINTS 275

chip (7) 4

The total displacement of the top of the solder joint due to heating by T degrees then becomes

x,t = x : , ~ + x:,t - y:tsi/2.

Obviously, the simultaneous displacement of the bottom of the solder joint, X t , can be expressed similarly in terms of the deformation of the substrate. Finally, of course, the solder joint is deformed by a shear force, - F;, and bending moment, -M," at the top. Conway et al. [5] expressed the resulting total elastic displacement, AXi, of top versus bottom of a cylindrical joint as the sum of a shear displacement and a bending displacement:

substrate

-2 I AX, = -Fihs/A;Gs - h:(2Fihs - 3M!)/6EsIi (8)

-4 where Ai and Ii are cross-sectional area and area moment of -4 -2 0 2 4

inertia, respectively, of the solder joint in question. Equating A x i with the difference X t - Xi" and combining it with (3), we then have n equations (i = 1, . . . , n):

Distance (mil)

Fig. 4. Cross section Of (convex) solder joint on 4.5 mil (114 pm) pads.

1 n

T = l j=1

where

s=l

In principle, the 2n equations, (9) and ( l l ) , can now simply be solved for Fi and M!, and M: can then be found from (3). In reality, however, we shall be particularly concerned with the effects of variations in stiffness corresponding to different joint shapes. We, therefore, finally divide the individual joints into a stack of layers, as illustrated in Fig. 4. Each of these layers is then approximated by a layer of constant width exposed to the shear force Fi and the bending moment M! - Fiy at the

( 9 ~ )

(94

where & j is the Kronecker delta, and min(i , j ) denotes the smaller of i or j.

Other n equations follow from equating the slopes of solder and chip, and of solder and substrate, at the corresponding interfaces. For example, bending of a cylindrical solder joint leads to a difference AY' = (2Mt - Fihs)hs/2EsIi between the slopes of the top and bottom surfaces (interfaces with chip and substrate) of the joint. Equating this to the difference between the slopes of chip and substrate surfaces (both evaluated previously) then gives

i n

AY' + ( M j + Fjtsi/2)Lq/Esilsi q = l j=q

top surface, where y is the distance of that surface from the chip. In the following examples, we divided each joint up into 100 such layers.

C. Stress Distributions in Solder Joint

Consider first the case where all stresses are much lower than the plastic flow stress for the temperature, strain rate, and solder composition in question, i.e., the above elastic analysis applies. At a given position (x, y, 2) is a solder joint the shear stresses parallel to the substrate are then [9]

T~~ = {R2 - x2 - z2(1 - 2v)/(3 + 2w)}

. (3 + 2v)Fi/8(1 +.)Is (124 i n T~~ = -xz(l + 2v)Fi/4(1 +.)Is (12b)

= q=1 j=q (Mj" - Fjtsub/2)Lq/Esub1sub (lo) where R is the radius of the joint at the height in question and Is(x, y, z ) = 7rR4/4. The tensile stress in the y-direction is

which is readily rewritten as oyy(xC,y,z) = UT + Mi(Y)Z/IS (1W e (cijFj + dijMj) = 0

j=1 (1la) where Mi(y) = M: - Fiy is the moment at the height

in question, and q~ remains negligible [5]. As mentioned


previously, forces and moments are all determined by adding the beam theory results (above) vectorially. We notice that the coordinate system is oriented to have the z-axis in the direction of thermal displacement for the particular joint in question.

Within the elastic-plastic approximation the plastic regime is readily accounted for. This is so because we are only really concerned with the largest tensile stress (our figure-of-merit). According to (12c), this is always found at (x, 2 ) = ( X , O), i.e., at the solder joint surface, where the shear stresses are zero (12a-12b). Indeed, as illustrated in the following and elsewhere, [4] this is usually also the location where plastic yielding first occurs. After yielding, the local tensile stress there thus also remains equal to the uniaxial yield stress.

111. APPLICATIONS AND DISCUSSION

In the following we shall illustrate and discuss an approach to the rapid relative assessment of various mechanical designs of area array solder joint assemblies in terms of reliability. Here we are specifically concerned with the growth of fatigue cracks in the solder joints during thermal excursions. The reliability thus depends on the rate of crack growth and on the solder joint cross section in the crack region. In most (but not all) of the comparisons in the following, that cross section (near the contact pad) is here kept constant. As described earlier, our approach relies on estimates of the largest tensile stress in an assembly as a figure-of-merit. In particular, although the most vulnerable solder joints usually undergo substantial plastic deformation, we shall be particularly concerned with the increase of the largest tensile stress with temperature in the elastic regime. As shown elsewhere [4], this stress is usually found at the same location where local yielding first occurs in a joint. The rate of increase of the stress in the elastic regime then also determines the temperature at which such yielding occurs, and above which the largest tensile stress remains equal to the uniaxial yield stress. We thus argue that the fastest stress increase in the elastic regime must also correspond to the largest damage integrated over the complete elastic-plastic deformation history.

As mentioned previously, our analysis ignores the effects of thermal expansion of the solder joints themselves. We shall, however, briefly consider the validity of the assumption. For this purpose, we shall ignore collective effects due to the presence of two interfaces and consider the stresses in a solder joint near the chip, where the thermal mismatch is usually the largest. Blech and Levi [ 101 calculated the thermal stress distributions in a plate or block clamped to a massive substrate. In general, the tensile stress normal to the interface was found to peak strongly near the edge, reaching a maximum on the order of 2E,AaT for aspect ratios similar to those of typical joints. For a 97Pb/3Sn joint on an Si chip, this corresponds to a maximum tensile stress of about 0.8 MPa/OC. As we shall see in the following, this is usually lower than the maximum tensile stress due to chip-substrate mismatches. Whereas detailed modeling should clearly include the effect, we may, therefore, ignore it at the present level of analysis.

For the sake of illustration, we shall consider examples of the effects of mechanical design variables, including changes

0 0 0 0 0 0 0 0 0 0 0 0 0

“,--l- o--- L, 0 7 - 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

Fig. 5. Schematic of solder joint array, I-configuration.

in solder joint array size and pitch, as well as solder joint size and shape. Usually, the thermomechanical loads on the outermost, most vulnerable solder joints in an array are substantially reduced by the presence of other joints nearer the neutral point. The addition of extra electrically inactive joints might help further reduce these loads. Also, the loads on the solder joints in a given array increase faster than linearly with distance to the neutral point. We shall, therefore, also consider the potential for reducing the loads on the outermost one by manipulating the solder joint shapes to achieve a more uniform sharing of the loads.

A. Distribution of Loads

Consider first the uniform heating of an array of 97Pb/3Sn solder joints, as sketched in Fig. 5. For a Si chip connected to an A1N substrate, the resulting shear force, per degree of heating, on joints along the center bar of the array would vary with distance to the neutral point as shown in Fig. 6(a). We have here assumed the parameters listed in Table I, a pitch L, = 20 mil (0.5 mm) and solder joints of the shape and dimensions indicated in Fig. 4. For comparison, the shear forces on a single pair of joints separated by 400 mil (10 mm) would increase by 1.9 mN per degree of heating, i.e., although the total load is shared between the joints in a very nonlinear fashion in Fig. 6(a), the maximum shear force (on the outermost joints) is strongly reduced due to the presence of the inner ones. The same is the case for the bending moment at the substrate (Fig. 6(b), where the corresponding “two-joint’’ moment would increase by 7.5 x IO-’ Nm per degree. Actually, we note that the forces and moments are calculated by beam theory, i.e., expressed “per unit beam width.” Anyway, the type of interdependence illustrated in Fig. 6 forms a basis for a significant part of the following discussion.

Fig. 7 shows the variation of oyy and ryz across the outermost joint, next to the substrate, for the example considered earlier. Since the shear force, Fi, is independent of the height, y, the maximum shear stresses are found at chip and substrate where R is smallest (Fig. 4). Also, because the substrate is more rigid than the chip, the bending moment is numerically


0.0

-0.2 - 0 0

z E -0.4

0 Center row !? e -0.6

0

Y 0

0

-1.0 -6 -4 -2

Distance (mm)

(a)

At substrate

Center row

0 0 0 0

Fig. 6. Increase in loads on a row of 21 solder joints of the shape shown in Fig. 4 with temperature. At a 20 mil (0.5 mm) pitch joints connect 25 mil (0.64 mm) thick Si-chip to 70 mil (1.8 mm) thick A1N substrate, see Table I. (a) Shear force. (b) Bending moment at substrate.

the largest here, and cyy reaches its “global” maximum. This, then, represents our figure-of-merit. We notice that the largest tensile stress arises at the joint surface, where shear is absent, and that it is sufficiently much larger than the maximum shear stress at the center to also determine the onset of local yielding. During plastic deformation the largest tensile stress is thus indeed equal to the uniaxial flow stress. In the present case, however, plastic deformation clearly remains negligible up to 100°C or more.

B. Reference for Reliability

In the following, we shall repeatedly compare the loads on solder joints in a particular assembly to those experienced in a current commercial product of established reliability. Fig. 8 shows the stresses in the end joints of the center bar of a similar array as shown previously, but on an alumina substrate. This configuration is currently quite common for memory devices, and Tsukada et al. [11], for example, found such an assembly to be reasonably reliable. Not surprisingly, the stresses are seen to be considerably larger than for the A1N substrate (Fig. 7), and indeed larger than the stresses due to chip-solder mismatch (above). Furthermore, the stresses in Fig. 8 are not even the largest in the array. The stress distributions in the

corner joints of the array have essentially the same shape as in Fig. 8, but all the stresses are about 40% larger. Also, the stress distributions are, of course, rotated around the joint axis to reflect the different direction of displacement of these joints (see above). We notice again, that local yielding occurs first at the location of the largest tensile stress, but this time after less than 10°C of heating.

C. High I10 Assemblies

Consider now first the case of high density square arrays (Fig. 1). In general, the maximum stress in such an array, of course, increases with the total array size. However, for a given pitch the total load is also shared by a larger number of joints, as the array size increases. Although the loads still increase faster than linearly with distance to the neutral point within a given array, the maximum stress in the corner joint, therefore, increases much slower than linearly with total array size. Fig. 9 shows the variation of the maximum tensile stress in the corner joint of an array connecting an Si-chip to an alumina substrate. This stress is found at the intersection of the array diagonal and the joint surface, next to the substrate. The joints were assumed to have the shape sketched in Fig. 4, i.e., to be 3 mil (76 pm) tall on 4.5 mil (114 pm) diameter contact pads. Not surprisingly, a 10 mm square array with 20 mil (0.5 mm) pitch behaves similarly to the above-mentioned commercial product (Fig. 8).

Fig. 9 also shows how a smaller pitch may help reduce the stresses, even if total array dimensions remain the same. In reality, however, future high 1 / 0 assemblies are likely to rely not only on larger, but also on more dense arrays and thus probably on smaller solder joints. This again results in considerably higher stresses, effectively counteracting improvements due to reductions in pitch. As we shall see, there is, therefore, definitely a need for reasonable CTE matching. For a beginning, Fig. 10 shows the maximum tensile stresses in square arrays like those in Fig. 4, connecting a Si chip to an A1N substrate. Even for the largest (2in) arrays the stresses do not increase very rapidly with temperature. However, for joints of the same shape, but with all joint dimensions smaller by a factor of three, the stresses get larger (Fig. 11), in spite of a simultaneous reduction in pitch. This problem is, of course, further exacerbated by the reduced cross section of the joint, i.e., even the same crack growth rate would lead to faster failure. Still, the weak dependence on array size is encouraging for the very large chips envisioned in the near future.

D. Solder Joint Shape

Until now, we have considered explicitly the behavior of solder joints of the shape sketched in Fig. 4. However, a reason for the observed variation in stresses with solder joint size was the effect of joint stiffness on the deformation of chip and substrate. Obviously, this effect must also depend on the actual joint shape.

In principle, different solder joint shapes may be achieved by two types of means. For one, we may, for example, vary either solder volume or pad size. Alternatively, we may somehow apply an additional downward or upward force during reflow. We have calculated [7] the resulting solder joint

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IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 16, NO. 3, MAY 1993

1 1 , , ~ , , , , ~ , , , , 1 , , , , 1 , , , , , ( , , ~

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TABLE I EXAMPLES OF ASSEMBLY PARAMETERS ASSUMED

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Stresses near substrote

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Distance (mil)

Fig. 7. Variation of stress increase, per degree of heating, across solder joint near the substrate in the direction of thermal displacement (z-axis), corresponding to Fig. 6(b). Outermost joint of row of 21 joints of shape shown in Fig. 4 connecting 25 mil (0.64 mm) Si-chip to 70 mil (1.8 mm) AlN, 20 mil (0.5 mm) pitch.

-

, . '\ . . '. tension . . ,

-3 - 2 -I 0 I 2 3 Distance (mil)

Fig. 8. Same as Fig. 7, but with 70 mil (1.8 mm) alumina substrate.

shapes on 1.5 mil (38 pm) pads in both cases and evaluated the results for the stresses in the corner joint of a 161 by 161 array on a 10-mil (0.25 mm) pitch connecting a Si chip to an A1N substrate.

For a given chip weight, and in the absence of spacers, increasing the solder volume clearly leads to a taller joint (Fig. 12) and allows for a larger shear displacement, but the consequence of this is not entirely trivial. Since a larger fraction of the shear displacement is accounted for by joint bending, the shear stress decreases systematically with joint height. However, the tensile stress represents a increasing fraction of a decreasing total load and thus goes through a minimum (Fig. 13). For the array dimensions specified previously an optimum solder joint height should thus be approximately 0.6 mil (15 pm).

- 6 si/AI,o3

convex joints

2 4 o 0 0 2 " pitch c

0 20 40 60 Array size (mm)

Fig. 9. Effect of pitch. Maximum tensile stress, per degree of heating, in the corner joint of a square array, as function of array size. Convex joints of the shape shown in Fig. 4, connecting 25 mil (0.64 mm) Si-chip to 70 mil (1.8 mm) alumina. (0) Array with 0.02 in (0.5 mm) pitch; (A) 0.01 in (0.25 mm) pitch.

1.5 I I , I I I I I , , I , I ,

Si /AIN

0: 1 convex joints

- 4 . 5 m i l pads, 0.02" pitch

Si /AIN

0: 1 convex joints

- 4 . 5 m i l pads, 0.02" pitch

0 20 40 60 Array size (mm)

Fig. 10. Maximum tensile stress, per degree of heating, in the comer joint of a square array, as function of array size. Convex joints (Fig. 4) on 20 mil (0.5 mm) pitch connecting 25 mil (0.64 mm) Si-chip to 70 mil (1.8 mm) A1N.

Of course, solder joint shapes may also be varied, without varying pad size or joint height, by the use of spacers or by additional weighting of the chip during reflow. However, the effect of this is straightforward. For the solder joint shapes sketched in Fig. 14, the shear and tensile stresses at the substrate vary as listed in Table 11, i.e., both of them decreased with decreasing surface curvature. For the ultimate optimization, of course, the height dependence should be considered anew for each value of surface curvature. The curve C shows the shape corresponding to the minimum tensile stress in Fig. 13.

In general, a substantially improved reliability can thus be achieved through manipulation of the solder joint shape.


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v)

- 0.5 - corner joint (square array) 1 I

1.5 mil pads, IOmil pitch, h,= I mil $ 1 0.0

20 40 60 Array size ( m m )

Fig. 11. Effect of small joints, compared to pig. 10. Maximum tensile stress, per degree of heating, in the comer joint of a square array, as function of array size. 1 mil (25 pm) tall joints on 1.5 mil (38 pm) pads, 10 mil (0.25 mm) pitch, connecting 25 mil (0.64 mm) Si-chip to 70 mil (1.8 mm) A1N.

Fig. 12. Calculated volume versus height for joints on 1.5 mil (38 pm) pads connecting 25 mil (0.64 mm) Si-chip to substrate.

8 1.5 - I - Y - c - 0 - L 1.0 - c - 0 - U

c

L

$ 0.5 - e - t j -

Max. tensile /

00 " " ~ " " " ' ~ ~ ~ ~ ~ ~ ~ 00 0 5 I O 1 5 2 0

Joint height (mil)

Fig. 13. Variation of stresses with height of small solder joints. Maximum tensile stress (solid curve) and average shear stress (broken curve) in corner joint of a 161 by 161 array on 10 mil (0.25 mm) pitch connecting 25 mil (0.64 mm) Si-chip to 70 mil (1.8 mm) A1N.

Consider, for example, square arrays of solder joints of the shape sketched in Fig. 15 connecting a Si chip to an alumina substrate and assume a 20-mil (0.5 mm) pitch. The resulting maximum tensile stress (Fig. 16) is about a factor of two lower than for the original convex joints (Fig. 9) for all array

- 8 0.0 U I 1

'i I ' cl

+

-0.5 -1.0 -1.5 I -1.0 -0.5 0.0 0.5 1.0 1.5

Distance (mil)

Fig. 14. Schematics of various solder joint shapes achieved by downward (A and B) or upward (D) forces during reflow. C corresponds to no load except for chip weight.

TABLE I1 MAXIMUM TENSILE STRESS AND AVERAGE SHEAR STRESS, PER DEGREE

OF HEATING, IN THE CORNER JOINT OF AN 161 BY 161 ARRAY FOR THE SOLDER JOINT SHAPES IN FIG. 14

Max. tens. stress Aver. shear stress [MPa/ O C] Curve [MPa/OC]

A 1.72 0.47 B 1.47 0.45 C 1.14 0.40 D 1.03 0.38

substrate

-4 -2- -4 -2 Distance (mil)

Fig. 15. Shape of (concave) solder joint on 4.5 mil (114 p m ) pads connecting 25 mil (0.64 mm) Si-chip to substrate.

sizes. Because of the weak dependence on array dimension this already allows for the use of much larger arrays, and further optimization of joint height and shape is clearly possible.

E. Load Redistribution Via Shape Variations

The only obvious problem with the use of concave joints would seem to be that the necessary process might be more complex/expensive. In particular for low cost applications and the consideration of more commodity oriented approaches, this may be a serious concern. Anyway, even further improvements should be achievable without having to apply any upward forces during reflow. This is so because the shape of a solder joint affects the reliability simultaneously in two distinctly

280 IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, 4ND MANUFACTURING TECHNOLOGY, VOL. 16, NO. 3, MAY 1993

Array size (mm)

Fig. 16. Effect of concave joint shape, compared to Fig. 9. Maximum tensile stress, per degree of heating, in the corner joint of a square array, as function of array size. Concave joints of the shape shown in Fig. 15, connecting 25 mil (0.64 mm) Si-chip to 70 mil (1.8 mm) alumina, 20 mil (0.5 mm) pitch.

different ways. On the one hand, stiffer inner joints help reduce the displacements of the outer joints. On the other hand, a less rigid outer joint will support a smaller stress for a given displacement. As noted previously, the loads on the individual joints in an array are mutually interdependent, but vary strongly with distance to the neutral point. The benefit of concave joints is achieved already if only the outer, most vulnerable joints, rather than all of them, are concave. We may, therefore, help distribute the loads more evenly within an array by making the inner joints stiffer than the outer ones. If, for example, the solder is vapor deposited through a shadow mask onto pads of a given size, such a shape variation may be achieved simply by varying the hole sizes in the mask, and thus the resulting solder volume on the corresponding pads.

For the sake of illustration, consider first the clearly unre- alistic example of a row of 5 joints on a 200-mil (5.1 mm) pitch connecting a Si chip to an alumina substrate. If all the joints have the size and shape (convex) sketched in Fig. 4, the maximum tensile stresses in the individual joints then increase almost linearly with distance to the neutral point, as indicated in Fig. 17. Not surprisingly, the stresses in the outermost joints increase very rapidly with temperature for the present exaggerated case. Using the concave joints of the size and shape sketched in Fig. 15 instead, the stresses in all of them are significantly reduced (Fig. 17). Now, varying the solder volume on the individual pads to create an array with concave outer and convex inner joints (Fig. IS), we may redistribute the loads to further reduce the maximum tensile stress in the most vulnerable outer joints (Fig. 17).

Whereas the above approach may be less expensive than simply using all concave joints in an array, however, the additional reduction in maximum stress does not appear to be significant for more realistic arrays. Fig. 19 shows the example of a row of 61 joints on a 20-mil ( O S mm) pitch connecting a Si chip to an alumina substrate. The individual solder volumes were chosen to give a common height of 3 mil (76 pm) on 4.5- mil (114 pm) diameter pads, but with shapes varying gradually with distance to the neutral point. The outermost joint had the concave shape sketched in Fig. 15 (concave), while the innermost ones were somewhat more convex than sketched in

- 0 0

0 a I .., In e v)

W

v)

c W

-

- f

Fig. 17.

5

4 y convex SI /Al,O,

Distance (mm)

Effect of varying joint shape. Maximum tensile stress, per degree ofheating, in 5 joints of height 3 mil (76 pm) on 200 mil (5.1 mm) pitch connecting 25 mil (0.64 mm) Si-chip to 70 mil (1.8 mm) alumina. (0) Convex joints of shape in Fig. 4; (A) concave joints of shape in Fig. 15; (g) inner joints convex, outer ones concave as shown in Fig. 18.

AI203

Fig. 18. Sketch of varying joint shapes assumed for “optimization” in Fig. 17.

301

0 10 20 0 0 1 I I I l I l

-20 -10 Distance (mm)

Fig. 19. Effect of varying joint shapes. Maximum tensile stress, per degree of heating, in 61 solder joints on 4.5 mil (114 pm) pads with a 20 mil (0.5 mm) pitch connecting 25 mil (0.64 mm) Si-chip to 70 mil (1.8 mm) alumina. Solid curve-convex joints (Fig. 4); (0) shapes vary from concave to strongly convex with decreasing distance to neutral point.

Fig. 4. The result of this shape variation is that stresses on the inner joints are somewhat larger than for the case where all joints are convex, whereas the stresses on the outer joints are significantly reduced. However, the maximum stress is not significantly lower than in a row of concave joints (stresses in Fig. 16 are for square arrays, i.e., larger than for a single row by a). F. Sacrificial Joints

Since the outermost joints support such a large portion of the total stress, and help reduce the stresses on joints further in, it might be tempting to add a single (or a few) “sacrificial” joints

281 B0RGESEN et al.: DESIGN CONSIDERATIONS FOR SOLDER JOINTS

2 . 5 , , , I , , , , , , , , , , , , , , , ,

Si/AI,O,

convex joints, 0.02“ pitch

-6 -4 -2 0 2 4 6

Distance (mm)

Fig. 20. Effect of “sacrificial” outer joint. Maximum tensile stress, per degree of heating, in convex solder joints (Fig. 4) on 4.5 mil (114 pm) pads with 20 mil (0.5 mm) pitch connecting 25 mil (0.64 mm) Si-chip to 70 mil (1.8 mm) alumina. (0) 21 electrically active joints; (#) same plus two extra, inactive joints.

on the outside of an array to enhance reliability. However, for a traditional array of convex solder joints the moderate improvement may not be worth it, considering the cost in extra real estate. Fig. 20 shows the effect of adding a single extra joint at each end of a row of 21 joints on a 20-mil (0.5 mm) pitch connecting a Si chip to an alumina substrate. All of the joints were of the size and shape sketched in Fig. 4. As we see, the maximum tensile stress is only reduced by a few percent. Of course, the effect may be enhanced by simultaneous variation of the solder shapes as discussed previously, i.e., by making the sacrificial and inner joints convex, but the outer “active” joints concave. Still, the benefit is, of course, continuously reduced as cracks grow in the sacrificial joints. Larger, and more durable, benefits might thus often be achieved by filling a relatively “open” array with extra, electrically inactive joints to effectively reduce the pitch (see Fig. 9). This approach might become particularly useful for the large area arrays connecting, say, chip carriers to boards (see the following).

G. Very Large Joints

As mentioned in Section I, considerable experience has been gathered over the years on the reliability of “conventional” flip-chip assemblies, and the above discussion of new develop- ments relies strongly on references to this. However, in some of the newer applications of area array solder joints, the joints are not only much larger, but also often of a very different composition. Whereas we may still compare various design options in terms of our figure-of-merit, we can, therefore, no longer rely directly on such experience for assessment of “absolute” reliability.

Because of the weak strain rate sensitivity of high Pb Pb/Sn solders the effects of plastic deformation are readily included in a simple elastic-plastic picture. However, for the near- eutectic Pb/Sn solders usually used in applications such as the attachment of chip carriers to cards this is no longer quite as obvious. Before considering the effects of component stiffnesses and array dimensions we shall, therefore, briefly discuss the effects of plastic deformation of such joints.

In the examples considered earlier local yielding clearly does not occur simultaneously everywhere in a joint. Rather the effective (von Mises) stress is usually largest at the joint surface and smaller further in (Figs. 7 and 8). The flow stress, and thus the onset of yielding, is readily estimated from the local strain rate as calculated in the elastic regime. However, as we shall see, the plastic strain rate changes as yielding of the individual joints progresses.

Consider first yielding of the outermost joint in an array. As the outer regions of the joint yield, and thus no longer support the same fraction of the full load, the stresses in the inner regions, of course, begin to increase faster with temperature, but general yielding may still require several more degrees of heating. As the joint is no longer able to support as large a fraction of the total load, the displacement of top versus bottom and the loads on the other joints also begin to increase faster with temperature [4]. Eventually, of course, joints further in also begin to yield, allowing, among others, for an even larger strain rate on the outermost joint. In general, the largest tensile stress in the outermost joint, therefore, continues to increase.

Since only a relatively small fraction of a solder joint (usually a layer near the substrate) ends up deforming plastically, even after general yield, the plastic strain rate determining the flow stress of concern may well be considerably larger than the nominal strain rate on the whole joint [12]. Nevertheless, the variation in the total rate of displacement of top versus bottom still provides an indication of the simultaneous variation in the plastic strain rate. Now, even for assemblies where a large number of joints end up deforming plastically, this variation is usually less than a factor of two. Even in the most strain rate sensitive regime such a variation would correspond to less than 30% difference in the flow stress of eutectic Pb/Sn solder [13]. Whereas the effect should clearly be included in more detailed modeling, our present figure-of-merit thus remains useful for comparisons at the present level of analysis.

For the remainder of our discussion, we shall now specifically consider examples of 70 mil (1.8 mm) thick alumina chip carriers connected to 100-200 mil (2.5-5 mm) thick FR-4 boards by convex eutectic solder joints on 25-35 mil (0.64-0.89 mm) diameter pads. In each case the height of the joints has been optimized (compare Fig. 13) to minimize the maximum tensile stress without the application of external loads during reflow. Since the carrier is obviously more rigid than the board, the tensile stresses are then larger near the former. Not surprisingly, the large array dimensions and pitch lead to rapid increases in stress with temperature, and this effect is further exacerbated by the larger elastic modulus of eutectic Pb/Sn solders than of high Pb ones.

Consider first a 21 by 21 array of joints on 25-mil (0.64 mm) pads with a 100-mil (2.5 mm) pitch connecting an alumina carrier to a 100-mil (2.5 mm) thick FR-4 board. For 15-mil (0.38 mm) tall joints of the shape sketched in Fig. 21, Fig. 22 shows the variation of shear and tensile stresses across the corner joint of the array. In spite of the larger flexibilify of the FR-4, the larger thermal mismatch and solder modulus leads to stresses similar to those found in chip-ceramic assemblies with the same array size (Fig. 9).

282

-

IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 16, NO. 3, MAY 1993

- Al,O,/FR-4

r Convex JOlnis, 0.1" pltch -

-10 1

5 -

0 0

E . r 0 - m -

e - m -

- 5

FR-4

-

-

-20 4 -20 -10 0 IO 20

Distance (mil)

Fig. 21. Schematic of solder joint on 25 mil (0.64 mm) pad.

-10 -15 1 -10 -5 I O 15 Distance (mil)

Fig. 22. Variation of stress increase, per degree of heating, across solder joint near the alumina in the direction of thermal displacement (z-axis). Corner joint of a 21 by 21 array on 25 mil (0.64 mm) pads on 100 mil (2.5 mm) pitch connecting 70 mil (1.8 mm) alumina to 100 mil (2.5 mm) FR-4.

The effects of component stiffnesses are not always trivial. In the case above, for example, a thicker board would allow for slightly lower tensile stresses in solder joints of the same size and shape, at the cost of an increase in shear (Fig. 23). Anyway, for both thicknesses we find a decreasing sensitivity to array dimensions as the total number of joints acting to deform the board increases (Fig. 24). Because of the flexibility of the board this effect is clearly much more significant than for chip-ceramic assemblies (Fig. 9), and slightly more so for the thinner of the boards (Fig. 24). Still, the rapid stress increases suggest a need for optimization if assemblies need to endure as large thermal excursions as conventional flip-chip assemblies.

Undoubtedly, reliability may be considerably improved by the optimization of joint shapes along the lines discussed previously. However, we shall here consider only the potential for improvements through, and the sensitivity to, variations in joint size and array density (pitch). Fig. 25 shows the maximum tensile stresses in arrays of solder joints on various contact pad sizes with a 100-mil (2.5 mm) pitch. The board was again assumed to be 100 mil (2.5 mm) thick and the solder joint volumes/heights were optimized (compare Fig. 13) for

I O , , 1 , 1 , , , , 1 , , , 1 1 , , , , 1 , , , , , , , , A1,03/FR-4 0.2"

-I 0 -15 -10 -5 10 15

Distance (mil)

Fig. 23. Same as Fig. 22, but for 200 mil (5.1 mm) FR-4.

0 0

oo A A A A

A A

y0.2" F R - 4

0

A

0 I ' J ~ I ~ ' 1 1 " ~ ~ 1 1 1 1 ( ~ ' ~ ' I I I ' ~ I ~ I ' ' ' ~

0 1 2 3 4 5 6 7 Array size (inches)

Fig. 24. Variation of stress with array size. Maximum tensile stress, per degree of heating, in corner joint of square array of 25 mil (0.64 mm) pads with 100 mil (2.5 mm) pitch connecting 70 mil (1.8 mm) alumina to FR-4 board. (0) 100 mil (2.5 mm) FR-4; ( A ) 200 mil (5.1 q" FR-4.

A1203/FR-4 0.1"

Corner joint, 0.1'' pitch, convex

10 Array size (inches)

Fig. 25. Variation of stress with solder jointlpad size. Maximum tensile stress, per degree of heating, in corner joint of square array with 100 mil (2.5 mm) pitch connecting 70 mil (1.8 mm) alumina to 100 mil (2.5 mm) FR-4. Heights optimized for each pad size. Solid curve-15 mil (0.38 mm) high joints on 25 mil (0.64 mm) pads (Fig. 21); (A)-16 mil (0.41 mm) high joints on 30 mil (0.76 mm) pads; (0)- 18 mil (0.46 mm) high joints on 35 mil (0.89 mm) pads.

each pad size. This means that solder volumes were chosen to give 15-mil (0.38 mm) tall joints on 25-mil (0.64 mm) diameter pads, 16-mil (0.41 mm) joints on 30-mil (0.76 mm) pads, and 18-mil (0.46 mm) joints on 35-mil (0.89 mm) pads.


AI,O,/FR - 4

- 6 0 1 “ pitch

o o o

= 4 o o

0 1 2 3 4 5 6 7 Array size ( inches)

Fig. 26. Effect of solder joint pitch. Maximum tensile stress, per degree of heating, in corner joint of square array on 25 mil (0.64 mm) pads connecting 70 mil (1.8 mm) alumina to 100 mil (2.5 mm) FR-4. (0) 100 mil (2.5 mm) pitch; (A) 50 mil (1.3 mm) pitch.

No attempt was made to vary joint shapes by the application of external forces during reflow. It is evident that stresses can be significantly reduced by maximizing the solder joint size for a given pitch (Fig. 25). Not surprisingly, a similar effect can be achieved by minimizing the solder joint pitch (Fig. 26), i.e., perhaps by “filling” the array with electrically inactive joints. Even without manipulating the solder joint shapes as above it should thus be possible to design a large assembly in which the stresses in the solder joints in the elastic regime do not increase much faster than in a 10-mm flip-chip array connecting a Si chip to an alumina substrate (Fig. 9). Since, furthermore, the plastic flow stresses are generally lower than in the high Pb Pb/Sn joints (at realistic strain rates), and fatigue crack growth rates at a given stress are lower as well [14], reliability of such as assembly should then be acceptable.

IV. CONCLUS~ONS

The optimization of mechanical reliability of area array solder joints depends on a number of parameters and is often subject to a trade-off with other criteria as well. In general, reliability may be optimized by minimizing array dimensions and pitch, while maximizing solder joint size. Significant improvements may also be achieved by filling relatively open arrays with extra, electrically inactive joints. When possible, good CTE matching and “hour glass” shaped joints provide for further improvements in reliability. Usually, final decisions should still rely on a damage integral type of approach and a more detailed finite element modeling.

I11

I21

REFERENCES

P. A. Totta and R. P. Sopher, “SLT device metallurgy and its monolithic extension,” IBM J. Res. Develop. vol. 5, pp. 226-238, 1969. N. G. Koopman, T. C. Reilly, and P.A. Totta, “Chip-to-package Inter- connections,” in Microelectronics Packaging Handbook, R. R. Tummala and E. J. Rymaszewski, eds. New York: Van Nostrand Reinhold, 1989, pp. 361-453.

L. S. Goldman, “Geometric optimization of controlled collapse intercon- nections,” ZBMJ. Res. Develop. vol. 5, pp. 251-265, 1969. P. Bmgesen, C.-Y. Li, and H.D. Conway, “Analytical estimates of thermally induced stresses and strains in flip-chip solder joints,” in Proc. ASMEIJSME Joint Conf. on Electronic Packaging, 1992, pp. 845-854. H. D. Conway, P. Bmgesen, and C.-Y. Li, “Elastic analysis of flip-chip solder joints undergoing thermal excursions,” to be published. R. Subrahmanyan, J.R. Wilcox, and C.-Y. Li, “A damage integral approach to solder joint fatigue,” in Proc. 2nd ASM Int. Electronics Materials and Processing Congress, Metals Park, 1989, pp. 213-221. B. Yost, J. McGroarty, P. Bmgesen, and C.-Y. Li, “The shape of a liquid drop constrained by parallel plates,” pp. xxx-xxx, this issue. J. McGroarty, P. Borgesen, B. Yost, and C.-Y. Li, “Statistics of solder joint alignment for optoelectronic components,” to be published. S. Timoshenko and J.N. Goodier, Theory of Elasticity. New York: McGraw-Hill, 1951. I. A. Blech and A. A. Levi, “Comments on Aleck’s stress distribution in clamped plates,” Trans. ASME, vol. 48, pp. 442-445, 1981. Y. Tsukada, Y. Mashimoto, T. Nishio, and N. Mii, “Reliability and stress analysis of encapsulated flip chip joint on epoxy based printed circuit board,” in Proc. ASMEIJSME Joint Conf. on Electronic Packaging, 1992, pp. 827-835. P. B~rgesen, H. D. Conway, and C.-Y. Li, to be published. J. R. Wilcox, “Inelastic deformation and fatigue damage in metals at high homologous temperatures,” Ph.D. dissertation, Cornell University, 1990. P. Borgesen, J. G. Maggard, D. D. Brown, S. Bolton, and C.-Y. Li, “Effects on composition of fatigue crack growth in Pb/Sn solder,” to be published.

Peter B~rgesen received the Ph.D. degree in physics from the University of Aarhus in Denmark in 1982. He then spent 4 years as a post-Doctoral Fellow at the Max-Planck-Institut for Plasmaphysics in Garching, Germany. He joined Cornell University, where he is now a Senior Research Associate in the Department of Materials Science and Engineering. He has done extensive research in the area of particle solid interactions, including the irradiation of solid hydrogen isotopes at cryogenic temperatures, and more recently on fine lines and electronic packaging.

Che-Yu Li (M’92) for a photograph and biography, please see page 241 of this issue.

H.D. Conway received the B.Sc., Ph.D., and DSc. degrees from London University in 1942, 1945, and 1949, respectively, and the M.A. and Sc.D. degrees from Cambridge University in 1946 and 1972, respectively.

Following his undergraduate education, he worked as a Scientific Officer with the Engineering Division, National Physical Laboratory. He was then a Demonstrator with the Engineering Laboratories, Cambridge University, and Assistant Director of Studies at St. Catherine’s College, Cambridge. In 1947, he joined the faculty of Cornell University, where he is currently Professor Emeritus of Theoretical and Applied Mechanics. From 1953 to 1954, he was a Guggenheim Fellow aid from 1960 to 1961 a National Science Foundation Senior Postdoctoral Fellow at Imperial College, London, U. K. From 1958 to 1959, he was the Julius F. Stone Visiting Professor at Ohio State University.

mechanical design considerations for area array solder joints

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