T.Sakurai

Meeting with the forthcoming IC design– The era of power, variability and NRE explosion

and a bit of the future –

- Solving issues of IC’s by 3D-stacking –Prof. Takayasu Sakurai

Center for Collaborative Research,and Institute of Industrial Science,

University of TokyoE-mail:tsakurai@iis.u-tokyo.ac.jp

ASPDAC’07 Keynote Address II 9am – 10am Jan.25, 2007

T.Sakurai

Moore’s law continues as a backbone but…

Drain Source

Gate

0.2micron

Drain SourceGate

0.2micronSize 1/2

Size x1/2Voltage x1/2Electric Field x1Speed x3Cost x1/4

Power density x1.6RC delay/Tr. delay x3.2Current density x1.6Voltage noise x3.2Design complexity x4

Unfavorable effectsFavorable effects

T.Sakurai

Three explosions threat Moore’s law

Explosion of power

Explosion of integrity attackers

Explosion of complexity

Explosion of NRE*

*) Non-Recurring Engineering Cost

T.Sakurai

3D Stacking for solving issues

Silicon chips stacking

for lower power & lower NRE

Organic sheets stacking

for newer applications

With design tool implications

T.Sakurai

Power is a stumbling block to Moore’s law Po

wer

per

chi

p [W

]

1980 1985 1990 1995 20000.01

0.1

1

10

100

1000

Year

MPU

x4 / 3

years

DSP

x1.4 / 3 years

Processors published in ISSCC

2005 2010 2015

x1.1 / 3 years

ITRS requirement

10000

Dynamic

Leakage1/100

T.Sakurai

Trade-off between power and delay

012345x 10-7

0

10

20

0.30.50.7-0.1

0.10.3VDD [V] V TH [V

]

Pow

er [W

/gat

e]

Del

ay [p

s]

DDs

V

DD VIVCfaPowerTH

⋅⋅+⋅⋅⋅=−

1002

0.30.50.7-0.1

0.10.3VDD [V] V TH [V

]

( ) 31 .THDD

DD

VVVCDelay

−⋅

∝

Equi-delay

65nm node, FO3 INV

(+ other leakage)

Change power depending on required performance.

T.Sakurai

Example of power-aware design

G. Uvieghara, et al., “A Highly-Integrated 3G CDMA2000 1X Cellular-Baseband Chip with GSM/AMPS/GPS/Bluetooth/Multimedia Capabilities and ZIF RF Support,” ISSCC paper#23.3, Feb. 2004.

Multi-VDD: Seven VDD’sDual-VTH: Two VTH’s for PMOS and NMOS eachPower gating: Selective MTCMOS reduced standby to 1/3~1/4.

T.Sakurai

Power-gating to cut-off VDD of inactive blocks is getting a major leakage-

aware design style and seems easy but…

CMOS logic

Low-VTH

st’by

VDD

VSS

Virtual VSS Power switch

Z

T.Sakurai

Pitfalls in power-gating1) Clock buffers

2) Repeaters

3) Gates receiving power-gated signals

4) Registers will lose stored info

5) Other common blocks like analog and sleep signal generator

(1)(2)

(3)

‘0’

Power-gated block

D

(4)

Big and rather slow (µs-order) noise on power supply line when switched off and on.

T.Sakurai

Tool implications of power-gating1) High-level description of power-gating

2) Power estimation tool

3) Sizing of power switch

4) Delay estimation under the effect of the power switch

5) Automatic generation of sleep signal

6) Layout level considerations

7) Power line integrity at sleep and wake-up

New tools for each new design approach

T.Sakurai

Adaptive VDD & VTH control for lower power with variability

T.Sakurai

Adaptive voltage for variation control

V TH

varia

tion

VTH

Del

ayLe

akag

e

CenterLow High

Improved

Improved

VSS

VDD

VBS=VDD=>VDD±v

VBS=0 => 0 ± v

pMOS

nMOS

T.Sakurai

Transmeta Efficeon 1.5 GHz Fixed VDD

VID = 1.0 volt

Power Spec 9.5 watts

Courtesy: Transmeta Corp.

T.Sakurai

Transmeta Efficeon 1.5 GHz with Voltage ID

VID = 0.8, 0.85, 0.9, 0.95, 1.0 volts (5)

Power Spec6.5 watts

Courtesy: Transmeta Corp.

T.Sakurai

1.5 GHz with VTH Control and Fixed VDD

VID = 1.0 voltsPower Spec

4 watts

Courtesy: Transmeta Corp.

T.Sakurai

1.5 GHz with VTH and VDD Control

VID = .85, .90, .95, 1.0, 1.05 (5)

Power Spec 3.6 watts

Courtesy: Transmeta Corp.Statistical simulation tools with VDD and VTH adjustment

T.Sakurai

History and perspective of low-power VLSI systems designOnce upon a time on a peaceful chip of VLSI

before the notorious power war …

We were using single VDD and single VTHfor an entire chip.

Then, the power war began andwe started using multiple VTH and VDDdepending on the location on a chip.

Still, the power war gets severer andwe started to vary VTH and VDD in time

adaptively.

In finer granularity in time and space …with a help from circuit and software.

T.Sakurai

Future power-aware VLSI

Voltage converters & power blocksneed L & C.

• High-voltage VDD distribution to lower noise issues• Distributed voltage conv. for fine-grain adaptive VDD & VTH

1V 50W → 50A current5% noise → 0.05V noise → 1mΩ sheet R → 15µm thick CuThick interconnects on interposer, package or something else

Power-grid

T.Sakurai

Further power-awareness by 3D stacking

Specialized blocksSensors and information collecting circuits

Proc. unit

Stacked analog/RF

Power unit

Stacked memories

Power grid

Power control proc.

T.Sakurai

3-D is good for low-power and high-perf.

System-on-a-Chip

3-D assembly

More devicesin closer vicinity

↓Less R and C

↓Lower power

Higher performance↓

Supporting design tools are the enabling technology.

Substrate< 20µm thick

System simulation & synthesis with 3D, simulation with electro-magnetic interaction

T.Sakurai

Three explosions threat Moore’s law

Explosion of power

Explosion of integrity attackers

Explosion of complexity

Explosion of NRE*

*) Non-Recurring Engineering Cost

T.Sakurai

Exploding NRE (Non-Recurring Eng. Cost)

By Rick Merritt, EE Times Oct 25, 2002

◆ NRE for a SoC is getting $5M~10M and without over $20M sales it is difficult to make a SoC. by Bryan Lewis, Gartner Dataquest

◆ Number of design starts is declining from 1997.

ASIC

ASSP

02000400060008000

100001200014000

2000 2001 2002Year

Des

ign

star

tshttp://www.eetimes.com/printableArticle?doc_id=OEG20021025S0052

Generation [μm]

Mas

k Se

t Cos

t (M

$)

Source: Rahul Goyal, Intel –Nov 2001 SEMI Mtg

0

0.5

1

1.5

2

2.5

0.4 0.25 0.2 0.180.150.1390n65n

T.Sakurai

Development is also risky

Dr. Kurt Keutzer, Ahmed JerrayaSpecial Session: “How do you design a 10M gate ASIC?” 2002 Design Automation ConferenceDr. Fumiyasu Hirose, Cadence Japan

Fix 1

Development (months)

Design, Fab, Test

Rev

enue

12

Time-to-Market (Samples)Time-to-Volume (Production)

ShipmentsWindow

181260

Fix 3

Shipments(months)

621 / 0

Fix 2

2nd Si OK

20%1st Si

OK

60%

3rd Si OK

15%

3rd Si not OK 5%

T.Sakurai

CANDE meeting 2005The final 5-year predictions (to be reviewed in 2010) were:

1) IC-Package CAD will be a part of standard design flow 2) India and China will have more EDA startups than U.S.3) Analog Designers will still resist high-level models and

languages 4) A complete Open Source RTL-GDS tool flow will exist5) Nearly all EDA tools will take advantage of multi-

processors 6) Fewer than 200 commercial chips released in 45 nm

technology7) No practical nanotech computing products 8) SPICE-type simulators will still be the workhorse of

analog designs 9) Moore's law will be dead10) System in Package will boomhttp://www.ics.uci.edu/~rgupta/cande/

T.Sakurai

System-on-a-Chip

3D stacking of chips/packages will be an assembly style suitable for low-NRE systems

MPU Core

CacheROM

Logic

AnalogUSB

DRAM

3D SiP or stacked packages

MPU Core

Logic

AnalogCache

USB ROM

DRAM

System-on-a-BoardLower NRE, QTATHigher-perf., lower power

T.Sakurai

ProcessorFPGAAnalog TCP/IPUSB

Amortizing NRE by volume production

RF

Interface VideoDVI DC-DC Graphics

MemoriesDRAM SRAMNVA/D D/ABluetooth

GSM

“Mix & Match” increases number of chips per development.

Systems

Components

T.Sakurai

Mixed business model

Tota

l cos

t / s

ales

[M$]

Number of chips sold [million units]

SoC total cost with $10M NRE & $10 per unit

0 1 2 3 4 50

50

100

SiP total cost with $0.1M NRE & $15 per unit

Total sales ($20 per chip)

Design tools from high level to physical level are needed.

T.Sakurai

Wired WirelessFa

ce to

face

Mor

e th

an 3

chip

s

[1] T.Ezaki [2] J.Burns [3] K.Kanda [4] D.Mizoguchi, (ISSCC’04, ’01, ’03, ’04)

Interconnections for new 3D SiP’s

Micro-bumps [1]

Substrate vias [2]

Capacitive coupling [3]

Inductive coupling [4]

T.Sakurai

Through substrate via (TSV)

http://www.zy-cube.com

Substrate via

Micro-bump

Adhesive layer

Adhesive layer

Micro-bump

By ZyCube

T.Sakurai

3D wafer stacking for high performance

Courtesy of Kerry Bernstein, IBM T.J. Watson Research Center

Via size is 0.2 microns diameter at the top, and 0.14 microns at the bottom.

SOI wafer is thinned down to several microns.

T.Sakurai

Inductive wireless superconnect

D. Mizoguchi, Y. Yusof, N. Miura, T. Sakurai, T. Kuroda, "A 1.2Gb/s/pin Wireless Superconnectbased on Inductive Inter-chip Signaling (IIS) ,”ISSCC’04, pp. 142-143, Feb. 2004. N. Miura, D. Mizoguchi, Y. B. Yusof, T. Sakurai, and T. Kuroda, “Analysis and Design of Transceiver Circuit and Inductor Layout for Inductive Inter-chip Wireless Superconnect,”Symp. on VLSI Circuits, pp. 246-249 June 2004.

for 3D-stacked VLSI’sMetal Inductor

Chip#1(Logic)

Chip#4

Chip#2(Memory)

Tx

RxChip#3

Tx

RxChip#1

Tx

RxChip#2

VR

VR

ITIT

Chip#3(Memory)

Clock & Power

Analog

T.Sakurai

1Tbps inter-chip wireless by 30µm coils

Tx chip (upper)1024ch data tranceiver

Rx chip (lower)

Coils for data Tx

30μm

Chips photo

15μm

Coils for clock Tx

200μm

Tx chip

Rx chip

Clock tranceiver

BIS

TC

lock

con

trol

0.18μm CMOS, 3fJ/bit energyN.Miura, D.Mizoguchi, M.Inoue, K.Niitsu, Y.Nakagawa, M.Tago, M.Fukaishi, T. Sakurai, T. Kuroda, "A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link," ISSCC'06, Paper#23.4, Feb. 2006.

Low-loss interconnects are preferable for micro transformers.

T.Sakurai

Inductively-coupled inter-chip communicationB

and

wid

th [b

/s]

’961G

10G

100G

1T

Year’98 ’00 ’02 ’04 ’06

Hitachi

NEC

NEC

NEC

TINTT

This Work

Our Work

Intel

Toshiba

Rambus

Hotrail

Sony, TeraChipOur Work

RambusFlexIO

1

10

100

1000

Ener

gy p

er b

it [m

W/G

b/s=

pJ/b

]

’96 ’98 ’00 ’02 ’04 ’06Year

Toshiba

NTT

Hitachi

NEC

NECIntel

TI

NEC

Our Work

Our Work

This Work

TeraChip

RambusFlexIO

N.Miura, H.Ishikuro, T.Sakurai, T.Kuroda, "A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping," Paper#20.2, ISSCC, Feb.2007.

’07

Currentproducts

Circuits and electro-magnetism hybrid simulation.

T.Sakurai

Even wireless power transmission

700x700µm2

K.Onizuka, H. Kawaguchi, M. Takamiya, T. Kuroda and T. Sakurai, “Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications,”Paper#15.1, CICC, Sept. 2006.

1

2

3

0 0.2 0.4 0.6 0.8 1 1.2 1.4Output Voltage (V)

Tran

smitt

ed P

ower

( mW

)MeasuredSimulated

RL=100Ω

T.Sakurai

VDD, High Voltage

LF

CF

RS

Load

Controller

Output filter

VDD,INTERNAL

On-chip distributed DC-DC converter

Need good low-resistive L & high-capacitive C.They are also needed for low-power RF circuits.

Si with L and C

Chopping frequency > 300MHz

T.Sakurai

Distributed DC-DC converter by 3D stacking

K.Onizuka, H. Kawaguchi, M. Takamiya, and T. Sakurai, “Stacked-chip Implementation of On-Chip Buck Converter for Power-Aware Distributed Power Supply Systems,” A-SSCC, Nov. 2006.

01020304050607080

0 20 40 60 80Output Current (mA)

Effic

ienc

y (%

)

MeasuredSimulated(HSPICE)

T = 5nsf = 200MHz

Ripple<10%2mm

Cap1nF

PAD

Output filter chipOn-chippowersupplies SoC/SiP

Package

L&C cells

Pads

Upper Chip(Output Filter)

Lower Chip(Active & Load)

T.Sakurai

5ns transition on-chip power supply

@ 0.18µm CMOS

Quick dropper

Linear regulator

Load 80µm

K.Onizuka and T.Sakurai, "VDD-Hopping Accelerator for On-Chip Power Supplies Achieving Nano-Second Order Transient Time," A-SSCC'05, Paper#6.1, Nov. 2005.

VDDHVDDL

< 5ns

Transition time smaller than 5ns

Measurement

For 25k-gatesequivalent load

T.Sakurai

3D Stacking for solving issues

Silicon chips stacking

for lower power & lower NRE

Organic sheets stacking

for newer applications

With design tool implications

T.Sakurai

Emergency control

On-demand logistics

Wearable

Individual adaptive marketing

Accidentavoidance

Nano sensor-net on bodyPersonal dataSmart shelfSmart cashier

Pedestrian assistance

Productiondata tracking

Anti-theft

Life supporting robots

Remote medicalassistance

Health monitoring

Environment monitoring

Rescue support Anormaly monitoring& alarming

Physical space

Virtual space

New electronics targets physical space

Disaster prevention

Human bodyHuman body

Transportation systemTransportation system

HomeHome

EnvironmentEnvironment

Town & streetTown & street

Original drawing: Courtesy of Prof. Morikawa, Univ. of Tokyo

T.Sakurai

Increasing VLSI penetration into people’s lifePr

oces

sor c

ount

per

per

son

1950 1960 1970 1980 1990 2000 2020Year

Large scale

Office / middle

WS

PC

historicalVac. tube

Transistor

IC

LSI

VLSI

0.001

0.01

0.1

1

10

100

Embedded

UbiquitousComputing

System LSI

1000SiP

Electronics is part of environments enhancing convenience and security of daily life.

People use electronics consciously.

UbiquitousElectronics

Ubiquitous devices

2010

T.Sakurai

Food 25.74％

Housing 7.82％

Electricity/gas 6.63％

White appliances 0.52％

Air conditioner 0.34％

Housing (others) 2.56％

Clothing 5.08％

Medical 3.67％

Transportation 2.46％

Automobile 1.58％

Transportation 4.61％

Communication 1.57％

Phone 1.52％Other comm.0.36％

Education 3.46％

TV 0.24％

Audio0.02％

Tape recorder0.01％

Others 20.92％Edutainment 5.90％

Books1.66％

Education appliance 2.32％

TV game machine 0.09％

Entertainment 2.32％

Video camera0.04％Camera 0.08％

VTR 0.03％

PC 0.46％

Emerging App.: Ubiquitous Electronics

Expenditure distribution of Japanese household

Digital consumer

Ubiquitous electronics is required to provide physical applications.

T.Sakurai

Required innovations forubiquitous electronics

Huge number of devicesExtremely low power (3D SiP)Low cost (3D SiP)

EverywhereVery short distance communication (L & C stacked)Ubiquitous energy source (Large-area electronics)

Interfaces to real-worldSensors & actuators (Large-area electronics)Heterogeneous systems (Heterogeneous ICs stack)

Design tool needs for 3D hybrid systems synthesis and simulation

T.Sakurai

Features of organic IC’s

Advantages

Low-cost manufacturingMechanical flexibility

Disadvantages

Low speed (<10-5 of Si VLSI)Low density (<10-4 of Si VLSI)

T.Sakurai

Organic electronics

RFID tags

Kennedy group

University of TokyoPioneer

Studio Del Sole

Infineon

Polymer Vision

Samsung

Sensors WearableElectronics

Solar Cells

Smart Cards

Message Boards

FlexibleDisplays

Flat PanelDisplay Gyricon

T.Sakurai

Printable electronics

T.Sakurai

Organic transistors

Source Drain

Insulator+ -

Gate

OFF ONVoltage

+ -Current

Pentacene

Organic semiconductors: main elements --- C & HSlow but flexible and low-cost manufacturing

Organic semiconductor

T.Sakurai

SPICE still works•Match level 1 SPICE MOS model with 200kΩ

Mobility 0.5 ~ 1.4cm2/VsIon/Ioff >106

L=100µmW=2mm

-40 -30 -20 -10 00

10

20

30

VDS [V]

I DS

[µA

]

VGS=-40V

-30V

-20V

-10V

200k

200k

MeasurementSimulation

S

DG

Level 1 SPICE MOS model

Bending proof

Preferably new model like μ ∝ (VGS-VTH)γ (0<γ<1)

T.Sakurai

Large-area electronics by stacked sheets

E-skin

IEDM’03ISSCC’04

Sheet scanner

IEDM’04ISSCC’05

Slow but low-cost for large-area (Si can’t cover)

Braille display

IEDM’05ISSCC’06

IEDM’06ISSCC’07

Wireless power

transmission sheet

Pressure sensors + OFETsPhotodetectors + OFETs

Actuators + OFETsCoils + MEMS + OFETs

T.Sakurai

Braille display by organic FETs

Y.Kato, S.Iba, T.Sekitani, Y.Noguchi, K.Hizu, X.Wang, K.Takenoshita, Y.Takamatsu, S.Nakano, K.Fukuda, K.Nakamura, T.Yamaue, M.Doi, K.Asaka, H.Kawaguchi, M.Takamiya, T.Sakurai, and T.Someya, "A Flexible, Lightweight Braille Sheet Display with Plastic Actuators Driven by An Organic Field-Effect Transistor Active Matrix," IEDM'05, Paper #5.1, Dec.2005.

M.Takamiya, T.Sekitani, Y.Kato, H.Kawaguchi, T.Someya, and T.Sakurai, “An Organic FET SRAM for Braille sheet display with back gate to increase the static noise margin,”ISSCC’06, Paper #15.4, Feb. 2005.

T.Sakurai

Plastic actuatorsUp

The displacement of the actuators to read Braille is 0.2 mm.

Actuator

Braille dot

Down

100μF

Equivalent circuit

T.Sakurai

Speed up by higher-voltage drive

Time (s)0 5 10 15 20 25 30 35 40

V AC

T(V

)

0

-1

-2

-3

-4D

ispl

acem

ent

of a

ctua

tor (

mm

)

00.20.40.60.8

VX = –3V

–5V–10V–20V

VX = –3V

–5V

–10V–20V

V PL

(V) 0

VX

17x speeding up

49000/20

Braille dot

DATAb(-20V)

VACT

Actuator

VPL

VPH = floating

Reliability limit

T.Sakurai

Overdrive for speed and reliability

Time (s)0 5 10 15 20 25

Dis

plac

emen

tof

act

uato

r (m

m)

0

0.2

0.4

-0.2

-0.4

10

5

0

-5

-10

Volta

ge (V

)DATA

DATAb

VPL

VPHVACT

1.6 s 0.74 s

Braille dot isUp

Down

~30s 1.6s

Hybrid simulation will be required (Mechanical – Electrical)

T.Sakurai

M.Takamiya, T.Sekitani, Y.Kato, H.Kawaguchi, T.Someya, and T. Sakurai, "An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin," ISSCC'06, Paper#15.4, Feb. 2006.

FrameActuator

OFETsdriver

OFETsSRAM

Braille sheet display stacking four sheets

T.Sakurai

Braille reading test

All of 4 blind subjects can read our Braille correctly.

T.Sakurai

Wireless power transmission sheet with plastic MEMS switches and OFETs

T.Sekitani, M.Takamiya, Y.Noguchi, S.Nakano, Y.Kato, K.Hizu, H.Kawaguchi, T.Sakurai, and T.Someya, "A large-area flexible wireless power transmission sheet using printed plastic MEMS switches and organic field-effect transistors," Paper#11.1, IEDM 2006, Dec. 2006.

M.Takamiya, T.Sekitani, Y.Miyamoto, Y.Noguchi, H.Kawaguchi, T.Someya and T.Sakurai, "Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches," Paper#20.4, ISSCC, Feb. 2007.

T.Sakurai

Efficiency ~ 0.1%

Efficiency > 60%

Position-sensing and selective activation Large coil

30x30 cm2 X 1 coil

Receiver coil

Receiver coil

1 inch2 X 64 coils

Many coils& one selected 1 inch2

Selective activation is the key.

1 inch2

Electro- magnetic induction works

T.Sakurai

Stacking sheets for MEMS and Organic FETs

Wireless power transmission system

Power transmission coils

Plastic MEMSswitches

Low lossSlow ~ 0.1s# of switching limited

Organic FETsPosition-sensing coils Contactless

position-sensing system

21 x 21 cm2 (8 x 8 cells)

ResistiveFaster < ms# of switching unlimited

Hybrid simulation of IC, mechanics and electro-magnetism

T.Sakurai

High power

Contactless position sensingLarge-area & Low cost

Lightweight & Printable

Wireless power transmission sheet (3D-stacked)

Size : 21 x 21 cm2Thickness : 1 mmWeight : 50 gEfficiency : 62.3%Max received power : 29.3 W

T.Sakurai

X’mas tree w/o a battery wirelessly powered

21 LEDs

13.56 MHz

Received power : 2 W

T.Sakurai

No electrical shock

I touched it by my hand. No problem ☺

T.Sakurai

Providing infrastructure ubiquitous electronics

Home-care robot Vacuum cleanerIn the floor

In the wall

TV on a wall

In the table

Mobile phone & PC & e-accessories(data can be wireless but USB’s wire delivers power)

Ambient illumination

Wirelessly powered room in the future

T.Sakurai

Summary

3-D stacking, new frontier of integrated circuits, is opening up new electronics.

Solving issues for higher performance, lower power, lower cost and newer functions

New design tools for hybrid simulation and synthesis to fully enjoy 3-D stacking