melanie berg m iz tech dog ies ncwpo rated nasngsfc ... · r melanie berg m un iz tech n dog ies i...

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Melanie Berg M un iz Tech n dog ies I ncwpo rated NASNGSFC Radiation Effects an

Analysis Group

To be presented by Melanie Berg at Radiation and Its Effects on Components and Systems (RADECS) 2006. Athens Greece. September 27-29,2006.

Field ~ r ~ g r a m ~ a ~ l ~ Gate Array [FPGA) - Definition - fmplementatians in space missions - Available Technologies

Single Event Upsets (SEUs) and Singte Event Transients

- Definition

Testing - Goals - Considerations ’

- Data Analysis

[SETS)

- HOW they Effect FPGAs

SUmmav To be presented by Melanie Bern at Radiation and Its Effeds on CDmponentS and Systems (RADECS) 2066. Athens Greece. September 27-29,2006. Page 2

To be presented by Melanie Berg at Radiation and Its Effects on Components and Systems (RADECS) 2006, Athens Greece, September 27-29,2006. I

https://ntrs.nasa.gov/search.jsp?R=20070024440 2019-12-26T23:39:16+00:00Z

Faulty Chips Delay launch of Japanese lmaqinq Satellite

Wllitc (IGS) p&@m decided Some 10 d i p s need to IC- Aug.ljtoppnerhclamrhaf placed. he said. Deiailr dboul

To be presenled by Melanie Berg a1 Radiation and lls Effens on Components and Systems (RADECS) 2006, Alhens Greece, September 27-29.2006. Page 3

To be presented by Melanie Berg at Radiaon and I t s Effeds on Components and Systems @AOECS) 2006, Athens Greece. September27-29,2006 Page 4

To be presented by Melanie Berg at Radiation and Its Effects on Components and Systems (RADECS) 2006, Athens Greece, September 27-29,2006. 2

To be pressnted by Melame f3erg at Redlatlon and Its Effects MI CWopMlents and Systems (RAOECS) 2006, Athens Gceaoe. September27-29,2006 Page 5

Role of F ~ ~ ~ A ~ I ~ Devices ~ i t ~ i ~ Space issions

To be presemed by Melanie Berg at Radidon and I t s Effeds on Components and Systems (RADECS) 2006, Athens Greece. sepiember27-29.2W6 Page 6


become more susceptible to in~urr in~ faults.

- reduction in core voltage - decrease in transistor

- increase in switching

A Fault Ocxurs when a transistor that is turned oft - Collects Charge at the drain - turns on with enough charge

to change the state of the

Why?

Current Flow - On Transistor -

geometry

speeds,

-

outpt To be presented by elanie Berg at R a d i m and Its E m on components and Systems (WIDECS) 2006, Athens Greeoe, Septemher 27-29, 2006 Page 9

Transient Generation and ~ r ~ ~ a ~ a t i ~ ~

Add something about set capture in dff

3e 10

To be presented by Melanie Berg at Radiation and Its Effects on Components and Systems (RADECS) 2006, Athens Greece, September 27-29, 2006. 5

t F

To be presented by Melam Berg at Radratlon and Its Effeds on Components and Sysrems (RADECS) ZWB, Athens Greece. September27-29,2006 Page 11

To be presenied by Melam Berg at Radiaon and Its Effeds on Cmpments and System5 (FMECS) ZOOS. Athens Greece, September 27-29.2000 Page 12


~ o n ~ g u ~ a t ~ ~ ~ Memory hit: - Largest area of concern for the Device - The entire FPGA can become un-configured. L ~ ~ ~ ~ ~ ~ o ~ n e ~ t ~ ~ Hit - frequency dependency: SETS can be caught by Flip-Flops - Frequency independent: SEU can occur in Flip-Flop

Single Event Functional Interrupt (SEN): Hits to - Power On Reset - Configuration Control logic

To be presented by Melanie Berg at Radiabon and Its Effeds on COmpDnentS and Systems (RADECS) 2006. Athens Greece, September 27-29.2w6 Page 14


To be presented by Melanie Berg at Radiation and Its Effects on Components and Systems (RADECS) 2006, Athens Greece. September27-29,2006 Page 15

Choosing the Most Cost Effective F for a Project with Critical R e q u ~ ~ e ~ e n t ~

Define realistic Requirements Trade-offs: - Reliability - Performance - Schedule - Total Cost

Define a methodology for trade-off analysis

Radiation Testing is key and can be broken into 2 major categories: - Characterization:

- Qualification

General device study Simple Test structures

Project specitics Test structures may be more complex

We'll Focus an Device Characterization

To be presented by Melenie Berg September 27-29,2006.

at Radiation and Its Effeds on Cmponents and Systems (RADECS) 2006, Athens Greece,

To be presented by Melanie Berg at Radiation and Its Effects on Components and Systems (RADECS) 2006, Athens Greece, September 27-29,2006.

Page 16

8

Mow radiatio~-tolerant (in ~ene~a l } is the Device Under Test (DUT}? Test for: - Clock Tree Susceptibility - Rest Tree Susceptibility - Sequential logic Hardness - Combinatorial Error Cross-Section Contribution - 110 Susceptibility - Single Event Functional Interrupts (SEFI)

- Configuration Memory Susceptibility ( ~ ~ M -Based nh!)

To be presented by Melanie Berg ai Radiation and Ns Effeds on Components and sysiems (RADECS) 2005. Athens Greece, September27-29, 2Oog Page 17

Push the limits of the DUT. - Timing variations (very slow to fastest clock rates) - Types of logic cells (check device technology library) - Fill Device with logic - Safe I/O strategies Designs should be simple so that faults are not masked and undecipherable. Designs should represent realistic i ~ p l e ~ e n t a ~ i ~ n s - Proper reset structures - Synchronous design techniques - Various levels of combinatorial logic between DFF structures - Fanout variation

To be presented by Melanie Berg ai Radiatmn and Its E M S on Comwnents and Systems (RADECS) 2008, Athens Greec?, September 27-29.7.W Page 1


I To be presented by Melanie Berg a1 Radiation and Its Effeds on Components and Systems [RADECS) 2006, Athens Greece. September 27-29, 2006 Page 19

To be presented by Melanie Berg at Radiation and Its Effeds on Cornpanenls and Syslems RADECS) 2006, Athens Greece, September 27-29.2006 Page 20


tion to Timing C ~ a r a c t e r ~ s t ~ ~ of th cation of corner case input variati m j n ~ ~ ~ i c DUT Data Capturn

Tester to DUT Inte ce Limitations - Number of I/O - Simultaneously Switching Outputs (SSO) - Interface connector speed

To be presented by Melanie Berg at Radiation and Its Effects on Components and Systems (RAOECS) 2006. Athens Greece. September 27-29,2006 Page 21

'GA

VI

LCDT Board

Spartan 111 FF

' Micro-Strip Connectors

To be presented by Melanie Berg at Radiation and ns Effeds on Components and Systems ( W E C S ) 2006, Alhens Greece, September27-29.2W6 Page22 I


Does the device stay configured? Is the DUT schematic supplied? Is the DUT implementation a reliable design? - Synchronous design techniques - "Single Integrity" solution applied

How reliable is the supplied inputs and data capture scheme of the tester? What are the maximum and minimum frequencies supplied to the DUT during test and how do they relate to the timing specifications of the device? What are the data rates? (May be difficult to determine for complex designs) Are there SEFls Is there speed degradation?

To be presented by Melanie Berg a1 Radialton and 115 Effeds on Components and Syslems (RADECS) 2008, Athens Greece. September 27-29,ZWB Page 23

Actel C~rporati~n in s u ~ p ~ ~ i n ~ SEU Data was supplied at 2MHz testing frequency Simple shift re ister test structures were ~ r n ~ l ~ r n e ~ t e ~

ASA-GS FC col f abo ra ted -S device specific data

To be presented by Melanie Berg at Radialton and 11s Effeds on Components and Systems WDECS) 2008. Athens Greece, September 27-29,U)OB Page I


RCELL (Sequential): - Triple Mode Redundant

(TMR) Mitigation - Inputs are shared

(single points of failure) - contains more logic (not

shown) 2 MUXs one for logic and one for clocking) Adds more sources of failure 0

CCELL (Combinatorial): - Logic Block is generally

a MUX structure - Addition of block should

increase error cross section as tkequency increases

To be presented by Melanie 8-w a1 Radiation and Its Effeds m C c i n p n t s and syslems (RADECS) 2006. Athens Greece. September 27-29,2006 Page 25

In general . . . ~ o ~ ~ ~ ~ a t Q ~ i a l . . . .. RCELL contains some CCELL should make a considerable contribution due to frequ dep

To be presented by Melanie Berg at Radiabm and lh Effects on Cwnpanents and Systems (RADECS) MOB, Athens G m w , September 27-29.2005 Page 26


Another effort b undertaken Cfock Rates were s~pp~ied to the DUT from A5 ISOMWz DUT Input Data: - Alternating data was supplied at half the clock rate - Static “ 0 - Static “1”

Several Designs were j ~ ~ l e ~ e n t ~ d to analyze the potential increased ~usceptib~li~ to transients when

en Actel and NASA-GSFC was

ng C-CELLS hronous Design Approach was i ~ ~ l e ~ e n t ~ d in the and in the tester.

To be presenied by Melananle Seplember27-29,2006 Page 27

al Radiatron and Its Effeds on Components and Systems (RADECS) 2006, Athens Greece.

SEE Data on Actel RTAX-S Shift Register Strings 10-6

10-7 h (1. 0 = 10“ .- b 5 E 10-9

10-10

IO-”

s b

0 10 20 30 40 50 60 70 LET (MeV*cm2/mg)

Strings with Additional

Corn binatorial Logic

t Frequency

To be presented by Melmanle Bers at Radiatmn and Ih E#& on Cmponents and Systems (RnDEcs) 2006, Athens Greece. Seplember27-29.2006 Page 28


ed Sneers ysicists.

Engineers: Physicists: Told Frequency dependency does not exist Was not aware of transients and their effects in ~ i r ~ u ~ t ~

ed on the new MHz, the original

assumption that the data is scalable holds true - (2Mhz to 150Mhz testing should result in abaut 2 orders of magnitude between data sets

To be presented by Melanie Berg at Radiation and 115 Effeds on Components and Systems (RADECS) 2006, Athens Greece, September 27-29,2006 Page 29

To be presented by Melanie Berg at Radiation and Its Effeds on Components and Systems (RADECS) 2006. Athens Greece, September 27-29,2006 Page 30


I TO be presented by Melanie Berg at Radiation and its E R ~ ~ S on Components and systems (RADECS) 2006, Athens Greece, Sepiember27-29.2WB

omparision of FPGA Radiation Test Data ~~ynamic Shift Register Tests Only)

Aebl TPIIR: embedded in device Configuration Memory)

Can not test without

Frequency 150 MHz 120 MHz

Frequency Dependent Yes I I Data Dependant Yes

No

Yes

7

7

No Yes - Too much No to high LET

To be presented by Melanie Berg at September27-29.2WB Page 32

d Its Effects on Components and systems (RADECS) 2006, Athens Greece.


ults ~ i t ~ j ~ circuit

rect questions must

To be presented by Melanie Berg at Radiakon and Its Effeds on Components and s w e m s (RADECS) 2006. Athens Greece. September 27-29,2006. Page 33

s FPGAs have proven to be cost effective solutions to large, complex systems ~ o n ~ g ~ ~ a t ~ o n and logic structures vary among ~ a n ~ f a ~ ~ r ~ r s When considering potential SEUs and deciding which device is best suited for a project, special attention must be taken concerning - Configuration Hardness - Logic Level Hardness - Ease of system level implementation - Function necessities (speed, data manipulation, . ..) - Mitigation schemes (if necessary

To be presented by Melanie Bem at Padiahon and Its EReUs on Cornponenls and systems (RADECS) 2006, Athens Greece, September 27-29,2008 Page I


adiation Testing is necessary to c ~ a r a c t e ~ e device eve1 SEU data. Care must be taken to implement a~pro~riate tests in order to push the DUT to its limits - Speed - Reliable data supply and capture - Realistic DUT design implementation - Simplistic structures - avoid fault masking

While analyzing data the proper questions should be asked to ensure the data efficiently charactwiies the device.

To be presented by Melanie Berg at Radiation and Its Effects on Components and Systems (RADECS) 2006, Athens Greece, September 27-29.2008 Page 35


EU and Test Co~sidera~ons for PGA Devices

Melanie Berg fvluniz Technologies Incorporated NASNGSFC Radiation Effects an

Analysis Group

Outline

Field Programmable Gate Array (FPGA) Background - Definition - Implementr&ons in space missions - Available Technologies

Single Event Upsets (SEUs) and Single Event Transients (SETS) - Definition - How they Effect FPGAs

Testing - Goals - Considerations - Data Analysis

Summary i o l . a - ~ q l * ( . R o - . ~ ~ ~ " ~ * r n - ~ ~ ~ " ~ - * - - ~ - ~ ~ ~ -

What's the Issue?

I Faulty Chips Delay launch of Japanese Imaging Satellite

Field P~grammable Gats? Arrays (FPGA)

Role of FPGNASIC Devices within Space Missions


Connectivity

Single Event Upsets (SEUs) and Single Event Transients (SETs)

I 1 Single Event Upsets (SEU) and Single

Event Transients (SET) CMOS transistors have become more susceptible to incurring faults. Why? ble - reduction in cure voltage tor - decrease in transistor

geometry - increase in switching

A Fault Occurs when a transistor that is turned oft - Collects Charge at the drain - turns on with enough charge

to change the state of the

speeds.

Transistor

Add something about set capture in dff

3.10


Example 1: Summa ry.... How Do SET's/SEU"s Effect Xilinx FPGAs? Configuration Memory hit: - Largest area of concern for the Devica - The entire FPGA can become uneonfigured LogidConnector Hit - Frequency dependency SETS can be caught by Flip-Flops - Frequency mndepedent SEU can occur in FlipFlop

Single Event Functional Interrupt (SEFI): Hits to - Power On Reset - Configuration Control logic

What considerations must be taken to test for these conditions?

Testing Complex FPGA Implementations Targeted for Critical Missions

Choo Cost ~ffective for a ritical Require

m Define realistic Requirements D: Trade-offs - Reliability

- Perfwmanoe - Schedule - TataCost

w Define a mathodology for trade-off analysis

w Radiation T a n g is key and can be broken into 2 major categones - CharaderiretCon

- QuaBficabon

m Genealdawceshldy e SunpdeTes(sI~&ures

li Prol.xtweEmEs D T e s t ~ m y b e m w s o m n p l s x

We'll Focus on Device Characterization

Goals for Device Characterization

How radiation-tolerant (in general) IS the Device Under Test (DUT)? Test for: - Clock Tree Susceptibility - Rest Tree Susceptibility - Sequential logic Hardness - Combinatonal Error Cross-Section Contribution

- Single Event Functional Interrupts (SEFI)

- Configuration Memory Susceptibility (SWM -Based

- UO SuSCEpttbility

Only)

DUT Radiation Test Strategies

Push the limits of the DUT - Timing vanahons (very slow to fastest clock rates) - Types of logic cells (check device technology library) - Fill Device with logic - Safe UO strategies Designs should be simple so that faults are not masked and undecipherable. Designs should represent realistic implementations - Proper reset s t ~ c t ~ r e ~ - Synchronous design techniques - Various levels of combinatorel logic between DFF structures - Fanout variation


I Shift Register Strings (sequential logic) Combinatorial Clouds of logic between (sequential cells) Large quantities of I10 to accommodate data variation, system clock rate variation, design interfacing, and I/O susceptibility testing

Testing Sequential and Combinatorial logic

Tester Radiation Test Strategies

Attention to Timing Characteristics of the DUT Application of comer case input variations (stress the part) Deterministic DUT Data Capture Tester to DUT Interface Limitations - NumberofllO - Simultaneously Swtching Outputs (SSO) - Interface connector speed

I

Analyzing Test Data -Asking the Right Questions

Does the device stay configured? Is the DUT schematic supplied? Is the DUT implementation a reliable design? - Synchronous design techniques - "Single Integnly" solution applied

How reliable is the supplied inputs and data capture scheme of the testef? What are the maximum and minimum frequencies supplied to the OUT during test and how do they relate to the timing specifications of the devlce?

wi What are the data rates? (May be difficult to determine for complex designs) Are there SEFls Is there speed degradetron?

Pap25 T o ~ ~ Q ~ u l . B a r p . ~ ~ . l " . ~ ~ - a C ~ ~ ~ ~ - ( R ~ 2 m B . ~ G I . t c l -278m

Data Analysis Example

Actel Corporation and NASA-GSFC collaborated in supplying SEU RTAX-S device specific data Data was supplied at 2MHz testing frequency Simple shift register test structures were implemented

Question: Was the supplied data an Efficient characterization of the devices?

W e 24 T o ~ W Q W u E B o l D l ~ n ~ * - m ~ W d ~ @ N X W m -5- m27sm


cte

k! RCELL (Sequenbal) - Tnple Made Redundant (TMR) Miiigaiion

- Inputs are shared (single points of failure)

- contains mare logic (not shown)

5 2 YUXs one for logc and one for clocking)

-a Adds more sowces of failure

BB CCELL (Combmatonal) - Logic Block is generally

a MUX siruciure - Addiiion of block should

increase error cross section as frequency increases

T o ~ a p l - 4 U l - B o ~ ~ ~ - ~ " ~ ~ - m n C o n B M n ~ M h r t n s B 1 D E C f - Ma,*- yP*mk,llzam

Actel Expectations: SET Frequency Response

In general ... Combinatorial.. . .. RCELL contains some CCELL should make a considerable contribution due to frequ dep

Data Analysis Example (Continued)

Another effort between Actel and NASA-GSFC was undertaken Clock Rates were supplied to the DUT from 15Miiz to 150MHz DUT Input Data - Alternating data was supplied at half the clock rate - Stalic"0" - SIak"1"

Several Designs were implemented to analyze the potential increased susceptibility to transients when utilizing C-CELLS S nchronous Desi n Approach was implemented in the DbT and in the tes?er.

t

Logic

Increase

Frequency 1 Test

Survey -Why Was the Original 2MHz Data Acceptable?

Asked Engineers and Physicists. Here's the Best of:

Engineers: Told Frequency dependency does not exist

B Was not aware of transients and their effects in circuitr/

150MHz, the original assumption that the data is scalable holds true - (2Mhz to 15OMhz testing should result in about 2 orders of magnitude between data sets

me 29 T o ~ ~ ~ L T M I . n a s a O * ~ ~ ~ l a ~ n d ~ ~ ~ - ~ ~ . M h r t n s m ~ M m M a s o - s w s a m

2 Orders of Magnitude is True in this Case


Comparision of FPGA Radiation Test Data (Dynamic Shift Register Tests Only)

Actel Aeroflex Xilinx TMR embedded m DICE embedded n Scrubbing (0vSMnbng

de- CoMw-abon Memory) d w h MlagatlC."

cannotteatvvldlout

FreqY@"Fy i50MHz lMMHz Jo MHZ

Frequeocyoependent Y e s NO

Data Dependant Yes YW 9

Lowwt cross SBCtlrn

stay canflgured Yes YeS NO

SEFl NO No Ye0

SpsedDegradadon No Yea - Too much NO eqmwe to high LET

w e 32 T o l . ~ a r w ~ o s s n . ~ ~ s , r B b a r ~ n ~ . n ~ O U O K S I 2 m B Mm'e- m z m na

Data Analysis Conclusion

We are aware of possible faults within circuitry When analyzing data, the proper precautions must be taken and the correct questions must be asked?

FPGAs have proven to be cost effective solutions to large, complex systems Configuration and logic structures vary among manufacturers When considering potential SEUs and deciding which device is best suited for a project, special attention must be taken concerning - Configuration Hardness - Logic Level Hardness - Ease of system level implementation - Funchon necessities (speed, data manipulation, - Mibgetion schemes (d necessary

)

Summary (Continued ...)

Radiation Testing is necessary to characterize device level SEU data. Care must be taken to implement appropriate tests in order to push the DUT to its limits - Speed - Reliable data supply and capture - Realishc DUT design implementation - Simplistic structures - avoid fault masking

While analyzing data the proper questions should be asked to ensure the data efficiently characterizes the device.

PWS 35 T ~ ~ ~ q h * l . r r B s ~ ~ ~ ~ " * ~ , ~ - ~ ~ ~ ~ ~ ~ ~ - - Mauu- sapmDa27'x)na


melanie berg m iz tech dog ies ncwpo rated nasngsfc ... · r melanie berg m un iz tech n dog ies i...

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