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* Property of STI of 22

8088-8086 Architecture

Computer Organization and Assembly Language

History of Intel Microprocessor

Ø The 4-bit Microprocessorsv Intel released the world’s first µp in 1971.

The 4004 is a 4-bit µp with maximum memory of only up to 4,096 4-bit memory locations (2,048 bytes).

Ø The 8-bit Microprocessorsv In 1972, Intel released the 8008 which is an

8-bit µp capable of addressing 16,384 bytes and has 48 instructions.

v In 1973, Intel released the 8080.

v In 1977, the 8085 was released.




The 16-bit Microprocessors

Ø In 1978, Intel released the 8086 µp and a year later the 8088. Both are 16-bit µp’s and can execute instructions in as little as 400 ns.

Ø These 16-bit microprocessors have multiplication and division instructions.




Basic 8088/8086 Architecture

RegisterArray

SegmentRegister and

IP

BusController

PrefetchQueue

ALU & CU

IR

EU BIU




8088/8086 Bus Structure

8086System

Address Bus

Data Bus

Control Bus

A0 to A19

D0 to D15

RD, WR, M/IO

ToMemoryand I/O

8088System

Address Bus

Data Bus

Control Bus

A0 to A19

D0 to D7

RD, WR, IO/M

ToMemoryand I/O




Logical Memory

1 MBytes

FFFFDH

00001H

00002H

00000H

FFFFEH

FFFFFH

8086/8088Logical

Memory Map




Physical Memory

512 KBytes

FFFFBH

00003H

00005H

00001H

FFFFDH

FFFFFH

512 KBytes

FFFFAH

00002H00004H

00000H

FFFFCHFFFFEH

Odd Bank Even Bank

16 bits




Dedicated and General Use of Memory

Ø 00000H to 00013H - dedicated

Ø 00014H to 0007FH - reserved

Ø FFFF0H to FFFFBH - dedicated for functions

Ø FFFFCH to FFFFFH - reserved for use




Register Structure of the 8086/8088

Computer Systems Organization

AH ALBH BL

CH CLDH DL

AX AccumulatorBX Base

CX CountDX Data

SP Stack PointerBP Base PointerSI Source Index

DI Destination IndexIP Instruction Pointer

CS Code SegmentDS Data SegmentSS Stack SegmentES Extra Segment

Flags

8 Bits 8 Bits

16 Bits

GeneralPurposeRegister

Pointer andIndexRegisters

SegmentRegisters




General Purpose Registers

Ø General Purpose Registers. These are used in any manner that the programmer wishes. Each is addressable as a:

16-bit register (AX, BX, CX, DX) or

Ø Two 8-bit registers (AH, AL, BH, BL, CH, CL, DH, and DL).




Pointer and Index Registers

Ø Pointer and Index Registers. Although the pointer and index registers are also general purpose in nature, they are more often used to index or point to the memory location holding the operand data for many instructions.

v SP (Stack Pointer)v BP (Base Pointer )v SI (Source Index )v DI (Destination Index)




Status Register or Processor Status Word

Ø Status Register or Processor Status Word. This contains 16 bits, but 7 of them are not used. Each bit in the PSW is a flag.

Ø These flags are divided into the conditional flags and the control flags.





Ø Conditional Flags

v Sign Flag (SF) - b7v Zero Flag (ZF) - b6v Parity Flag (PF) - b2v Carry Flag (CF) - b0v Overflow Flag (OF) - b11v Auxiliary Carry Flag (AF) - b4




Example 1

Perform the indicated operation and determine the state of the conditional flags.

1.)0010 0011 0100 0101

+ 0011 0010 0001 10010101 0101 0101 1110

2.)0101 0100 0011 1001

+ 0100 0101 0110 10101001 1001 1010 0011




Example 2

Perform the indicated operation and determine the state of the conditional flags.

1.)0101 0100 0011 1001

- 0100 0101 0110 10101001 1001 1010 0011

2.)0001 0010 0011 0100

- 0100 1010 1110 00001100 0111 0101 0100




Example 3

Perform the following arithmetic operation and determine the state of the conditional flags.

1.) 70A3H – E757H2.) FE58H + 01A8H




Exercises

Perform the following arithmetic operation and determine the state of the conditional flags.

1.) AA45H – 4678H2.) 234FH + 34CDH 3.)

0110 0010 1010 0000+ 1001 1101 0110 0000

0000 0000 0000 0000





The control flags are:

v Direction Flag (DF) - b10v Interrupt Enable Flag (IF) - b9v Trap Flag (TF) - b8




Segment Registers and Memory Segmentation

Ø The MM can be partitioned into 64 K (65,536) byte segments where each segment represents an independently addressable unit of memory consisting of 64 K consecutive byte-wide storage locations.

64 KBSegment

Base Address




Generating a Memory Address

Ø A logical address in the 8086/8088 is identified by a segment (its base address) and an offset.

.

.

.

Data

Base Address

.

.

.

64 KBSegment

Offset




Example 1

Segment Base Address = 1234H Offset Address = 0022H

Computing for the physical address:

Physical Segment Base Address = 2340H+ Offset Address = 0022H

Physical Address = 12362H




Example 2

Segment Base Address = 123AHOffset Address = 341BH

Computing for the physical address:Physical Segment Base Address = 123A0H

+ Offset Address = 341BHPhysical Address = 157BBH




Exercise

Determine the physical address of the following addresses:

1. Segment Base Address = 4321H Offset Address = 1266H

2. Segment Base Address = ABCDH Offset Address = 3623H

3. Segment Base Address = AE6DH Offset Address = 43A1H

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