memctrlrunit aim: capture and simulate memctrlrunit element ise project : memctrlr.ise provides...

memCtrlrUnit

Aim: Capture and simulate memCtrlrUnit element

ISE Project : memCtrlr.ise provides access to all of the constituent files

This document contains:• EE427 submission / demonstration instructions• appliedVHDL project overview

• Function description and block diagram• Assignment Instructions• Process description• Functional Partition• Incremental Data Dictionary• Finite State Macine flowchart• Synthesised RTL schematics • memCtrlrUnit&RAMBFM Simulation Model and testbench structure• SRAM r/w timings

EE427 Phase 3b Assignment : Contents

memCtrlrUnitDFD 1.3.1 (memCtrlrUnit) Function Description & Block

diagram

symbol

Function description:

Manages SRAM control signals to perform SRAM rd or wr SRAM address tri-state controlRegisters data on SRAM read

Use RAM Bus Functional Model (BFM) to simulate memCtrlrUnit

Block Diagram:

SRAM SpecramBFM

memCtrlr State

Machine

4

D

QregDatFromRam

dat2Ram(31:0)

ramAddSrc(17:0)ramAdd(17:0)

add(17:0)

dat(31:0)

ramRdReg

memCtrlrFSM

en

memCtrlrUnit

CE1L, CE0L, WEL, OEL

UB0L, LB0L,UB1L, LB1L

1.3.1

1.3.1.1

1.3.1.2

1.3.1.3

ramWr,ramRd

enRamWrTri

triStBuff bidir data bus, ramIO(31:0)

datFromRam(31:0)

SRAM (256kx32)Bank 0 and 1

Quadrant 0 addr range “00”&(0->FFFF)

Quadrant 1 addrrange “01”&(0->FFFF)



memCtrlrUnitAndRAMBFM

memCtrlrUnitPhase 3b Assignment instructions

1. memCtrlrUnit level– Capture memCtrlrUnit.vhd VHDL model.

The lab file contains commented VHDL template files – Check VHDL code syntax, synthesise and view RTL schematic.

Confirm correctness.

2. RAMBFM– Review/verify/complete RAMBFM.vhd.

The template file includes the RAM rdMem VHDL process. Complete the rdMem VHDL process. Synthesis is not necessary.

3. memCtrlrUnitAndRamBFM level– memCtrlrUnitAndRamBFM.vhd VHDL model is provided. – Review VHDL code syntax. Do not synthesise. – Review memCtrlrUnitAndRamBFM_TB.vhd VHDL code and memRead.txt – Review memCtrlrUnitAndRamBFM_TB.udo modelsim macro file. – Simulate memCtrlrUnitAndRamBFM_TB.vhd. – Review the timing waveform and verify correct memCtrlrUnit and RAMBFM VHDL model

operation.

memCtrlrUnit

DFD 1.3 (memCtrlr) Process Description

• memCtrlrUnit FSM performs RAM r/w control. Refer to CMOS Static RAM IS61LV25616AL specification (www.issi.com/pdf/61LV25616AL.pdf)

• Only 32-bit RAM access is supported. Therefore, LB1L, UB1L, LB0L, UB0L are always asserted

• Bidirectional RAM data bus with tristate data output

• Registers data read from RAM

memCtrlrUnitDFD 1.3.1 Functional Partition

memCtrlrUnit

DFD 1.3.1 : Incremental Data Dictionary

• enRamWrTri: enable tristate buffer as o/p for RAM write

• regDatFromRam : assertion enables register to store data read from RAM

memCtrlrUnit

idle

read

ramWr

ramRd

write

Flowchart Key :

i/ps : clk, rst, ramWr, ramRd

o/psSignal default valuece1L ‘1’ce0L ‘1’weL ‘1’oeL ‘1’ramDone ‘0’enRamWrTri ‘0’regDatFromRam ‘0’

N

YN

Y

ce1L ‘0’ce0L ‘0’oeL ‘0’ramDone ‘1’regDatFromRam ‘1’

ce1L ‘0’ce0L ‘0’weL ‘0’ramDone ‘1’enRamWrTri ‘1’

memCtrlrFSM Flowchart

DFD 1.3.1 : FSM Flowchart

memCtrlrUnit

Tristate buffer

FSM

RAM data read register

RTL schematic

memCtrlrUnit

memCtrlrUnit (DFD 1.3.1.1) FSM RTL schematic

memCtrlrUnitmemCtrlrUnit&RAMBFM Simulation Model

• memCtrlrUnit can be verified using a VHDL model of the SRAM device SRAM specification: www.issi.com/pdf/61LV25616AL.pdf • VHDL simulation model is call a Bus Functional Model (BFM)• VHDL RAM BFM mimics the behaviour of the SRAM device. • RAM BFM used to provide RAM behavioural VHDL model enabling simulation of practical interactions between the VHDL memCtrlr model & a real RAM device• BFM Incorporates SRAM device timing

Supports byte control (lower and/or upper byte access), though unused in appliedVHDL project

Models RAM device tristate behaviour• BFM model is not synthesised for implementation, though can avail of full VHDL language to define its behaviour• ramCtrlrUnit testbench block diagram (illustrated on next slide)• ramCtrlrUnit testbench template code is provided Functional description included in ramBFM VHDL file header (ramBFM.vhd)• Testbench uses fileIO (memWrite.txt) to apply ram write data.

uses fileIO (memRead.txt) to output data read from ram

memCtrlrUnit

DFD 1.3 memCtrlrUnitAndRAMBFM Testbench Structure

memCtrlrUnit

• During write cycle both CEL & WEL asserted (low) & valid address is presented on SRAM address bus • Write cycle timings (refer to full SRAM spec)• A VHDL RAM Bus Functional Model (BFM) models the device operation Include Thzwe in the ramBFM SRAM write model

DFD 1.3.1.1 memCtrlrFSM : SRAM Write Cycle Timing

memCtrlrUnitmemCtrlrUnitAndRamBFM_TB w’form extract (WRITE)

memCtrlrUnitRAM write cycle timing diagram

memCtrlrUnit

• Both CEL & OEL asserted (low) & valid address is presented on SRAM addr bus Read cycle timings (refer to full SRAM spec). A VHDL RAM Bus Functional Model (BFM) models the device operation Include Taa in the ramBFM SRAM write model

DFD 1.3.1.1 memCtrlrFSM : SRAM Read Cycle Timing

memCtrlrUnitRAM read cycle timing diagram

memCtrlrUnitmemCtrlrUnitAndRamBFM_TB : RAM read cycle timing diagram

memCtrlrUnitmemCtrlrUnitAndRamBFM_TB Simulation sequence waveform

memctrlrunit aim: capture and simulate memctrlrunit element ise project : memctrlr.ise provides...

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