memories - faculty-web.msoe.edu€¦ · 15.05.2020 · synchronous ram using inferred memories 1)...
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Memories
Last updated 5/15/20
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Counters
These slides review the design for several types of memories
Upon completion: You should be able to design ROMs and RAMS of various sizes and register
configurations
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Memories
• ROM – mux based with memory values stored as constants
![Page 4: Memories - faculty-web.msoe.edu€¦ · 15.05.2020 · synchronous RAM using inferred memories 1) downto Inputs: outputs: clk, addr, we _ b, data_out data—i n 4096 library ieee](https://reader036.vdocuments.net/reader036/viewer/2022062607/605ab55acaba3e4bb1066d97/html5/thumbnails/4.jpg)
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Memories
• ROM – mux based
![Page 5: Memories - faculty-web.msoe.edu€¦ · 15.05.2020 · synchronous RAM using inferred memories 1) downto Inputs: outputs: clk, addr, we _ b, data_out data—i n 4096 library ieee](https://reader036.vdocuments.net/reader036/viewer/2022062607/605ab55acaba3e4bb1066d97/html5/thumbnails/5.jpg)
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Memories
• ROM – mux based
![Page 6: Memories - faculty-web.msoe.edu€¦ · 15.05.2020 · synchronous RAM using inferred memories 1) downto Inputs: outputs: clk, addr, we _ b, data_out data—i n 4096 library ieee](https://reader036.vdocuments.net/reader036/viewer/2022062607/605ab55acaba3e4bb1066d97/html5/thumbnails/6.jpg)
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Memories
• ROM – inferred with memory values stored in a xx.mif file
![Page 7: Memories - faculty-web.msoe.edu€¦ · 15.05.2020 · synchronous RAM using inferred memories 1) downto Inputs: outputs: clk, addr, we _ b, data_out data—i n 4096 library ieee](https://reader036.vdocuments.net/reader036/viewer/2022062607/605ab55acaba3e4bb1066d97/html5/thumbnails/7.jpg)
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Memories
• ROM – inferred w/ mif file
rom_init.mif
![Page 8: Memories - faculty-web.msoe.edu€¦ · 15.05.2020 · synchronous RAM using inferred memories 1) downto Inputs: outputs: clk, addr, we _ b, data_out data—i n 4096 library ieee](https://reader036.vdocuments.net/reader036/viewer/2022062607/605ab55acaba3e4bb1066d97/html5/thumbnails/8.jpg)
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Memories
• ROM – inferred w/ mif file
• Cannot be simulated
![Page 9: Memories - faculty-web.msoe.edu€¦ · 15.05.2020 · synchronous RAM using inferred memories 1) downto Inputs: outputs: clk, addr, we _ b, data_out data—i n 4096 library ieee](https://reader036.vdocuments.net/reader036/viewer/2022062607/605ab55acaba3e4bb1066d97/html5/thumbnails/9.jpg)
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Memories
• SRAM – synchronous write – generic• No inferred memory
![Page 10: Memories - faculty-web.msoe.edu€¦ · 15.05.2020 · synchronous RAM using inferred memories 1) downto Inputs: outputs: clk, addr, we _ b, data_out data—i n 4096 library ieee](https://reader036.vdocuments.net/reader036/viewer/2022062607/605ab55acaba3e4bb1066d97/html5/thumbnails/10.jpg)
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Memories
• SRAM – register based
32 bits x 64 words4 bytes x 64 words8x4x64 bits (registers) = 2048
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• SRAM – register based
Memories
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Memories
• SRAM – register based
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Memories
• SRAM – synchronous read/write – generic• Inferred memory
![Page 14: Memories - faculty-web.msoe.edu€¦ · 15.05.2020 · synchronous RAM using inferred memories 1) downto Inputs: outputs: clk, addr, we _ b, data_out data—i n 4096 library ieee](https://reader036.vdocuments.net/reader036/viewer/2022062607/605ab55acaba3e4bb1066d97/html5/thumbnails/14.jpg)
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Memories
• SRAM – inferred memory
8 bits x 4096 words = 32,768 bits
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Memories
• SRAM – inferred memory
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Memories
• SRAM – inferred memory