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Memory Design I

Professor Chris H. Kim

University of MinnesotaUniversity of MinnesotaDept. of ECE

chriskim@ece.umn.edu

Array-Structured Memory Architecture

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Semiconductor Memory Classification

R d W i MNon-Volatile

R d O l MRead-Write Memory Read-WriteMemory

Read-Only Memory

EPROM

E2PROM

FLASH

RandomAccess

Non-RandomAccess

SRAM

Mask-Programmed

Programmable (PROM)

FIFO

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DRAMShift Register

CAM

LIFO

Read-Write Memories (RWM)• Basic storage elements of semiconductor

memoryRAM

SRAM DRAM

SRAM ll h i 6T FAST LOW POWER l i

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SRAM: cell has gain, 6T, FAST, LOW POWER, logic compatible, differential

DRAM: cell has no gain, 1T, refresh, slow, DRAM process, single ended, DENSE

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Memory Scaling Trend

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• High density is the primary design goal for memories• Low voltage operation is essential for low power

Itoh, IBM R&D, 2003

Memory Scaling Trend

• Long retention time low Ioff

– High Vt is required• Fast access time

high Ion– High Vgs-Vt is

required

• Vdd cannot be

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Vdd cannot be scaled down aggressively for low power consumption

Itoh, IBM R&D, 2003

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Why SRAMs are Important0.18μmCore

Logic

Cache

0.13μm

0.09μm

Cache

Core Logic

Core

Cache

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Core Logic

• Memories have better power efficiency compared to logic• ~9.9B out of 10B transistors will be used for SRAMs• Company with better SRAM design will dominate

Why SRAMs are Important

111.2

1.4

ed I O

N

NMOSPMOS

WLAreatV11

=∝σ

Taur, Ning0.4

0.6

0.8

1.0

0.01 0.1 1 10 100Normalized IOFF

Nor

mal

ize

100X

2X

150nm, 110°C

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• Area is the number one concern minimum sized devices• Smaller devices have larger variation• Delay variation, stability, leakage is a problem• Central limit theorem doesn’t hold (σ/μ)

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Positive Feedback: Bi-StabilityVi1 Vo2Vo1 = Vi 2

1V VVo2 = Vi 1Vo

1

Vi25Vo1

1

Vi1

A

Vo2

Vo1 Vi2

V = V

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Vi25Vo1

C

B

Vi1 = Vo2

Vi2 = Vo1

Meta-Stability

A

Vo1

A

Vo1

C

B

Vi2=

C

B

Vi2

=

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Gain should be larger than 1 in the transition regionδ Vi1 = Vo2 δ Vi1 = Vo2

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SRAM Memory Cell

0

WL

• NMOS access transistors• Read and write uses the same port: need sufficient

‘1’0

BL BLB

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Read and write uses the same port: need sufficient margins

• One wordline to access cell• Two bit lines (BL, BLB) to carry the data• Almost minimum size transistors for small cell area

SRAM Read Operation

‘1’0

WL‘1’

• Both bit lines are precharged to Vdd• Wordline is fired for one of the cells on bit line

‘1’

BL BLB‘1’‘1’

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o d e s ed o o e o t e ce s o b t e• Cell pulls down either BL or BLB• Sense amp regenerates the differential signal• Data should not flip after read access• Driver TR must be stronger than access TR

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SRAM Read Operation

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• For high density, large number of cells share bitline and wordline– Subarray organization for 32Kb: 128 WL’s, 256BL’s

Murmann class notes

SRAM Read Operation

bitlinebitline VCd lbitli Δ

WL

BL 50 V

cell

bitlinebitline

Idelaybitline =

• Cbitline is large due to large number of cells attachedI is small d e to high densit cells

BLB

SA out

50mV

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• Icell is small due to high density cells• ∆Vbitline has to be minimized for high speed

– < 100mV bitline voltage difference generated by SRAM cell– Let the sense amplifier finish the job– Increased noise sensitivity, circuit complexity

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SRAM Read Operation: Precharge

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SRAM Read Operation: Precharge• Option (a)

– Similar to dynamic logic precharge– Balance transistor to equalize bitline voltages

S– Short wordline pulse required to limit bitline swing• Option (b)

– Pseudo-NMOS type circuit– Bitline voltage clamped during read

• Option (c)– NMOS pullup instead of PMOS– Precharge levels are limited to Vdd-Vt

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Precharge levels are limited to Vdd Vt– Can’t operate at low Vdd

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VddVdd

Vdd

SRAM Cell Read Margin

Vdd 0 Vx

• When cell is not accessed (WL=0)– Data is safely kept inside the cell

Hi h i i

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– High noise margin• When cell is accessed (WL=Vdd)

– Access transistor acts as a noise source– Data ‘0’ is pulled up to Vx– Cell data can flip if Vx rises above Vtn

VDDVDD

VDD

Static Noise Margin

0.2

0.4

0.6

0.8

1

V(Q

B)

VQVQB

E. Seevinck, 1987, JSSC

0.6

0.8

1

(QB

)

Good SNM0

0 0.2 0.4 0.6 0.8 1V(Q)

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Destructive read problemThe size of the largest square enclosed in the butterfly curves = read static noise margin

0

0.2

0.4

0 0.2 0.4 0.6 0.8 1V(Q)

V(

Bad SNM

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CMOS SRAM Analysis (Read)WL

BL

VDDM 4BL

M 5M 6

M1 VDDVDD VDD

Q = 1Q = 0

Cbit Cbit

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Techniques to Improve Read Margin

Cell beta ratio =

• Increasing the size of the driver NMOS improves read

(W/L)drv / (W/L)access

J. Rabaey

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Increasing the size of the driver NMOS improves read margin

• But remember, area is the number one constraint in memory design

• Increasing cell size a not a good trade off

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Techniques to Improve Read Margin• High Vt transistors

– Internal node on low side needs to rise to Vtside needs to rise to Vtor more

– Virtually never happens when Vt is larger than half Vdd

– Cell is extremely stable at ultra-low power design pointBeta ratio constraint is

SNM low Vt

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– Beta ratio constraint is relaxed smaller driver and larger access TR can be used for faster read and write

SNM high Vt

Techniques to Improve Read Margin• Boosted cell supply

– Supply voltage of SRAM ll i hi h Vdd

Vdd+∆

SRAM cell is higher than outside

– Makes driver stronger than access, suppressing the rise in the low side

– Effectively improves

VddVdd

dd

Vdd 0

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Effectively improves the beta ratio

– Driver NMOS can be downsized, decreasing cell size

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SRAM Write Operation

0

WL‘1’

‘1’0

BL BLB‘0’‘1’

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• Launch the write data on BL and BLB• Word line signal is fired• Low bit line value flips cell data• Access TR must be stronger than PMOS load

CMOS SRAM Analysis (Write)

M4

VDD

WL

( )( )

4//LWLW

PR=

BL = 1 BL = 0

Q = 0Q = 1

M1

M5

M6

VDD

( )6/LW

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SRAM Cell Write Margin

0Vdd

VddJ. Rabaey

Vdd 00 Vdd

= (W/L)pmos / (W/L)access

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• Access transistor must be stronger than PMOS to pull the below the trip point (typical pull-up ratio ~ 1.5)

• To avoid cell size increase, correct pull-up ratio achieved by controlling Vtn and Vtp

Techniques to Improve Write Margin• Sizing: access TR vs. PMOS in latch• Higher WL voltage for access TR• Virtual VDD

Higher voltage

Sizing

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6T-SRAM Layout Until 90nm

VDD

BL BLB

GND

WL

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WL

Compact cellBitlines: M2Wordline: strapped in M3

6T-SRAM Layout From 65nm

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6T versus 4T SRAM

6T SRAM CellSupply current is limited t th l k t fto the leakage current of transistors in the stable state

4T SRAM CellHi h d f

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High degree of compactnessHigh power consumption

RAM Variations• Many variations to the basic 6T SRAM cell• More functionality, smaller cells

Dual read or single write cell– Dual read or single write cell– True multi-ported cell– Content addressable memory (CAM)– 4T memory cell– 3T memory cell– 2T memory cell

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– 1T DRAM cell

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Dual Read or Single Write CellWL0WL1

• Two wordlines, one for each access transistorS ll i i ll i

BL BLB

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• Small increase in cell size• Can either

– read two different cells in one cycle– or write to one cell

Multi Ported CellWL0

E h t h t ddBL0 BLB0

WL1BL1 BLB1

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• Each port has separate address• Memory access bandwidth is twice (ideally)• “Write through”: data written can be read by

another port in the very same cycle

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Content Addressable Memory (CAM)

• Some application need to find out if anything in the memory matches a certain key value (e.g. tag)

• Special memory with XOR gate that compares cell value

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• Special memory with XOR gate that compares cell value with the data on the bilines

• Precharged match line shared across word will stay high only when the entire word matches

• Needs a encoder that will output the matching address

Smaller RAM Cells

• Internal nodes don’t go to Vdd

• Cell won’t work at low Vdd• High value stored is

• Need 2 wordlines, read WL and write WL

• Can have 1 or 2 bitlines (Read/Write)

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• High value stored is degraded

• Effective strength of NMOS driver is reduced

• Refresh needed

(Read/Write)• Not very small, since it has

more wires

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1-T DRAM Cell

M

WL

BL

WLWrite 1 Read 1

M1

CS

CBL

VDD 2 VTX

sensing

BL

GND

VDD

VDD /2 VDD /2

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Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

ΔV BL VPRE– VBIT VPRE–CS

CS CBL+------------= =V

DRAM Cell Observations1T DRAM requires a sense amplifier for each bit line,

due to charge redistribution read-out.DRAM memory cells are single ended in contrast toDRAM memory cells are single ended in contrast to

SRAM cells.The read-out of the 1T DRAM cell is destructive; read

and refresh operations are necessary for correct operation.

When writing a “1” into a DRAM cell, a threshold voltage is lost This charge loss can be circumvented by

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voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD

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Sense Amp Operation

V(1)VBL

DV(1)

V(0)

VPRE

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V(0)tSense amp activated

Word line activated

1-T DRAM Cell

M1 word

Capacitor

1line

Diffusedbit line

Polysilicongate

Polysiliconplate

Metal word line

Poly

SiO2

Field Oxiden+ n+

Inversion layerinduced byplate bias

Poly

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Uses Polysilicon-Diffusion CapacitanceExpensive in Area

Cross-section Layout

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Advanced 1-T DRAM CellsCapacitor dielectric layerCell plate

Word lineInsulating Layer

Cell Plate Si

Capacitor Insulator

Storage Node Poly

2nd Field Oxide

Refilling Poly

Si Substrate

IsolationTransfer gateStorage electrode

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2nd Field Oxide

Trench Cell Stacked-capacitor Cell

Good References on RAM• K. Itoh, VLSI Memory Chip Design, Springer-Verlag

New York, LLC • Y Nakagome M Horiguchi T Kawahara and K Itoh• Y. Nakagome, M. Horiguchi, T. Kawahara, and K. Itoh,

Review and future prospects of low-voltage RAM circuits, Vol. 47, No. 5/6, 2003, IBM J R&D

• R. W. Mann, W. W. Abadeer, M. J. Breitwisch, O. Bula, et al, Ultralow-power SRAM technology, Vol. 47, No. 5/6, 2003, IBM J R&D

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