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Metrology of Defect Annealing in Advanced USJ Formation Processes

P. J. Timans1, Y. Z. Hu1, Y. Lee1, J. Gelpey1, S. McCoy1,W. Lerch1, S. Paul1, D. Bolze2 and H. Kheyrandish3

1 Mattson Technology2 IHP, Frankfurt (Oder), Germany3 CSMA Ltd., U. K.

Metrology of Defect Annealing in Advanced USJ Formation Processes

P. J. Timans1, Y. Z. Hu1, Y. Lee1, J. Gelpey1, S. McCoy1,W. Lerch1, S. Paul1, D. Bolze2 and H. Kheyrandish3

1 Mattson Technology2 IHP, Frankfurt (Oder), Germany3 CSMA Ltd., U. K.


Outline

Introduction— Trade-offs in annealing — Metrology challenges

Diffusion & Electrical ActivationDamage annealing— Reflectance Spectra— Junction Leakage (RsL)— Photoluminescence— Thermal Wave

Paths forward for advanced junction engineeringConclusions


Advanced USJ Requirements

C.-H. Jan et al., IEDM 2005, p.65Minimize Dopant Diffusion Maximize electrical activation“Enough” defect annealing— Junction leakage:

Becoming significant for low power CMOS

— High channel/halo doping greatly increases leakage

Need to optimize all 3 “dimensions”Damage metrology:— Traditional - TEM, devices— Non-Contact:

ReflectanceRsL – RS & Junction LeakagePhotoluminescenceThermal Wave

Rapid Process Optimization


Trends in Millisecond Annealing

Currently, millisecond anneal is being combined with spike annealing— Polysilicon gate activation— Gate overlap— Implant damage recovery

As technology progresses, the desire is to lower the thermal budget further— Reduce dopant diffusion— Metal gate / high-K integration— Strain engineering integration

Reduce peak T of spike anneal or migrate to millisecond anneal only?— Residual defect concerns

Damage engineering - implant & anneal


Experiment

PAI: 1015 Ge/cm2 @ 30 keV

Halo: 4x1013 As/cm2 @ 40 keV

B: 1015 B/cm2 @ 500 eV

Anneal

PAIPAI

Anneal

B Implant

PAI

Halo

10-15 Ωcm n-type (100), 200 mm Si

Pre-anneal: 1050°C, 10 s, 10% O2

Anneals:•SPE: 650°C, 5 s•Spike: 1050°C•fRTP: Various conditions


Millisecond Annealing with Flash-Assisted RTPTM

Flash-Assisted RTPTM

(fRTPTM ):—150 K/s ramp to Ti

—Pulsed surface heating

—MilliosTM tool provides real-time T measurement on front & back of wafer

600700800900

10001100120013001400

4.5 5.0 5.5 6.0

Temperature (°C)

Time (s)

600700

800900

1000

11001200

1300

4.835 4.840 4.845 4.850 4.855

Top TempBot Temp

Time (s)


Outline

IntroductionDiffusion & Electrical ActivationDamage annealingPaths forward for advanced junction engineeringConclusions


Diffusion Behaviour in c-Si Wafers

Minimal diffusion with fRTP, except for highest teff

Concentration-enhanced diffusion ⇒ More abrupt junctions

1018

1019

1020

1021

0 5 10 15 20 25 30 35

As ImplantedfRTP: 700°C/1250°CfRTP: 700°C/1300°CfRTP: 750°C/1300°CfRTP: 2x 750°C/1300°CfRTP: 750°C/1350°CSpike: 1050°C

Con

cent

ratio

n (c

m-3

)

Depth (nm)


Halo Doping and Pre-Annealing Effects (c-Si Case)

Halo suppresses B ion channelling, but introduces TEDPre-annealing halo ⇒ Behaviour similar to c-Si caseExpect high junction leakage with halo

— Junctions at ~15-30 nm depth, doping > 6x1018/cm3

— High doping concentration: ⇒ Narrow depletion region (~ 15 nm)— Residual damage from PAI and halo implants

1018

1019

1020

1021

0 10 20 30 40 50 60

H: As-Implanted (B)AH: As-Implanted (B)H: Spike (B)AH: Spike (B)H: fRTP 700/1300°C (B)AH: fRTP 700/1300°C (B)Halo-SRIM (As)Halo with Diffusion (As)

Con

cent

ratio

n (c

m-3

)

Depth (nm)

a-Si/c-Si PAI


fRTP: Improved Activation & Reduced Diffusion

fRTP gives a major improvement over spike anneal in RS/XJtrade-off for both c-Si & PAINo benefit evident for use of PAI over c-Si

200

250

300

350

400

450

500

550

600

10 15 20 25 30 35 40

c-Si, fRTPc-Si, SpikePAI, fRTPPAI, SpikePAI, SPE

4PP

-Hg

Prob

e R

S (Ω

/sq.

)

XJ (7x1018 cm-3) (nm)


Outline

IntroductionDiffusion & Electrical ActivationDamage annealing— Reflectance Spectra— Junction Leakage (RsL)— Photoluminescence— Thermal Wave

Paths forward for advanced junction engineeringConclusions


Reflection Spectra Reveal Implant Damage

Peaks at 3.4 and 4.6 eV reflect “long range” crystalline order— Disrupted by implant damage

Oscillations < 3 eV ⇒ amorphous layer— ~ 50 nm thick for PAI; ~ 30 nm for halo (heavy damage layer)

0.3

0.4

0.5

0.6

0.7

1.5 2 2.5 3 3.5 4 4.5 5 5.5

c-Sic-Si + BPAI + BHalo + Bc-Si + B(Spike Anneal)

Ref

lect

ance

Energy (eV)


Evolution of Reflectance Peaks with Annealing

Behaviour at peaks is sensitive to annealing, especially 3.4 eV peakAt 3.4 eV light penetrates ~10 nm⇒ Probes heavily B-doped region

More sophisticated analysis should be possible

0.45

0.50

0.55

0.60

0.65

0.70

0.75

3.0 3.5 4.0 4.5 5.0

c-SiAs ImplantedSpike750°C/1300°C

Ref

lect

ance

Energy (eV)

c-Si + B Implant

0.45

0.50

0.55

0.60

0.65

0.70

0.75

3.0 3.5 4.0 4.5 5.0

c-SiAs ImplantedSpike750°C/1300°CSPE

Ref

lect

ance

Energy (eV)

PAI + B Implant

0.45

0.50

0.55

0.60

0.65

0.70

0.75

3.0 3.5 4.0 4.5 5.0

c-SiAs ImplantedSpike750°C/1300°C

Ref

lect

ance

Energy (eV)

c-Si + Halo + B Implant


Junction

Depletion

Substrate

Spreading

Modulated LED Beam

Vin Vout

Recombination

Junction

Depletion

Substrate

Spreading

Modulated LED Beam

Vin Vout

Recombination

RsLTM: Non-Contact Sheet Resistance & Leakage

1. Modulated light source creates free carriers in junction & substrate.

2. Carrier drift & leakage monitored by dual-probe measurement of junction photo-voltage (JPV).

3. Carrier spreading analysis gives sheet resistance, RS.

4. Frequency dependence of JPV gives recombination leakage current, JL.

RsL probe(Frontier Semiconductor)


Junction Leakage Reveals Dominant Role of Halo

Halo doping greatly increases leakage (narrow depletion region)— Pre-annealing halo damage reduces JL, esp. in c-Si

For PAI, 1300°C fRTP significantly reduces JL from SPE level

0.1

1

10

100

1000

10000

c-S

i

c-S

i,H

c-S

i,AH

PAI

PA

I,H

PA

I,AH

Wafer Type

J L (u

A/c

m2 ) SPE

SpikefRTP, 700°C/1250°CfRTP, 750°C/1300°C


Photoluminescence for Damage Characterization

Room temperature photoluminescence measurements were performed using a system from Accent (Now Nanometrics)The PL signal is very sensitive to defects that alter electron-hole recombination behaviour

A. Buczkowski, ECS Trans. 11(3) p.109 (2007)


Photoluminescence Shows Damage Annealing Trends

For c-Si, halo damage effect and annealing trend are evidentWith PAI, halo condition makes little difference1300°C fRTP ⇒ Damage levels ≅ spike annealing result

1

10

100

1000

10000

c-S

i

c-S

i,H

c-S

i,AH

PA

I

PA

I,H

PA

I,AH

Wafer Type

Def

ect L

evel

(Arb

. Uni

ts)

As implantedSPESpikefRTP, 700°C/1250°CfRTP, 750°C/1300°C


Thermal Wave Characterization

Thermal wave measurements were performed using a TP630XP system from KLA-TencorThe TW signal can be affected by both defects and by doping distributions

S. Cherekdjian et al., ECS PV 2002-11, (2002) p.339


Thermal Wave Results Reveal Doping & Damage Phenomena

TW Signals initially reduce with annealingHalo implant has large effect on final signal values— But, pre-annealing has relatively little effect

Results suggest that doping plays a key part in the TW signal

101

102

103

c-Si

c-Si,H

c-Si,AH

TW S

igna

l (Ar

b. U

nits

)

fRTP

SPE:

650

°C

Spik

e: 1

050°

C

700/

1250

°C

700/

1300

°C

750/

1300

°C

2x 7

50/1

300°

C

750/

1350

°C

Non

e 101

102

103

PAI

PAI,H

PAI,AH

TW S

igna

l (Ar

b. U

nits

)fRTP

SPE:

650

°C

Spi

ke: 1

050°

C

700/

1250

°C

700/

1300

°C

750/

1300

°C

2x 7

50/1

300°

C

750/

1350

°C

Non

e


Outline

IntroductionDiffusion & Electrical ActivationDamage annealingPaths forward for advanced junction engineeringConclusions


Minimizing Halo Doping is Essential for Leakage Control

Millisecond Annealing enables shallower junctions and hence improved short-channel effect control— Halo dose can be

reducedReduced BTBTReduced damage from halo

T. Hoffmann et al., IIT 2008 Conference, Monterey, 2008


Damage/Activation/Diffusion Engineering Requires Innovation in BOTH Implantation and Annealing

Selection of implant approach has major effect on residual damage:— PAI & dopants: Mass, dose, energy, dose rate, temperature— Co-implants: Diffusion & activation control— Novel implant schemes: Molecular implants, plasma doping, GCIB

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

B B+PAI BF2 BF2 + PAI B18 B18 + PAI

RsL

Lea

kage

Cur

rent

(A/c

m2)

Spike 1000Spike 1080Flash 1300Laser 1300SPE 650 B18H22 implant

shows greatly reduced RsLleakage current(SemEquip data)


Boron Doping Profile: Carborane Implant and MSA

1 E + 1 5

1 E + 1 6

1 E + 1 7

1 E + 1 8

1 E + 1 9

1 E + 2 0

1 E + 2 1

1 E + 2 2

0 1 0 2 0 3 0 4 0 5 0D e p t h ( n m )

B C

ON

CE

NT

RA

TIO

N (

at

A s -Im p l a n t e d X j: 8 . 9 n m

A b r u p t n e s s : 0 .9 3 n m /d e c a d e

R s : 9 5 8 .7 o h m s / s qX j : 1 0 . 5 n m @ 5 E 1 8

SIMS profile of flash annealed carboraneimplant. Note superior Xj/Rsand junction abruptness

J. Gelpey et al., Ultra-Shallow Junction Formation using Flash Annealing and Advanced Doping Techniques, IWJT-2008.


Damage and Activation Improvements with High Temperature Preheat in Millisecond Anneal

Improved activation and greatly reduced junction leakage demonstrated by using flash-lamp annealing with higher pre-heat temperature & B18H22 implant

K. Yako et al.(NEC)

16th IEEE International Conference on Advanced Thermal Processing of Semiconductors -RTP2008


Novel metrology techniques ⇒ very rapid assessment of defect phenomena & optimization of implant & annealing choices

Conclusions

The halo implant is dominant in determining junction leakage:Dose and halo implant damage are criticalPre-annealing halo damage reduced leakage

Annealing approaches offer trade-offs :Spike anneals remove defects, but introduce excessive diffusionSPE gave good activation with very little diffusion, but junctions show severe leakageMillisecond annealing with fRTP showed improved activation with minimal diffusion, as well as improved defect annealing

The next steps in USJ technology require advances in both implantation and annealing— Novel implantation methods can help overcome the damage

annealing challenge


Acknowledgements

H. Phan, G. Stuart & D. Camm - Mattson Technology

M. Current, T. Nguyen, J. Halim and V. Faifer - Frontier Semiconductor

A. Buczkowski, Z. Li and T. Walker - Accent (now Nanometrics)

J. Chen, T. Dimitrova, W. Liu, N. Jaeger and D. Dimitrov - Four Dimensions

S. Prussin & J. Reyes - UCLA

M. Bakshi, D. Shaughnessy and A. Salnik - KLA-Tencor

L. Romano and K. Jones - University of Florida

A. Kontos, L. Godet, C. Hatem, G. Papasouliotis, J. Scheuer - Varian Semiconductor Equipment Associates

K. Sekar, W. Krull, T. Horsky, D. Jacobson - SemEquip

metrology of defect annealing in advanced usj formation ... · for pai, 1300°c frtp significantly...

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