MICRO-35 Program at a Glance (all sessions are in the Ball Room)

Wednesday 20th Thursday 21st Friday 22nd

8:00. Conference Opening 8:00. Energy Efficient Memory Systems

8:00. Keynote II : Justin R. Rattner, Director, Microprocessor Research, Intel Labs, “Right Hand Turn for Power Efficient Computing” 8:15. Keynote I : Tilak Agerwala, Vice

President, Systems, IBM Research, "Systems Trends and Their Impact on Future Microprocessor Design" 10:00. Break 9:00. Break

9:15. Break

9:45. Superscalar Design

10:30. Compilation and Run-time Systems

9:30. Simulation and Architecture Evaluation Morning

11:45. Lunch 12:00. Break

11:30. Lunch 11:55 – 12:20. Invited NSF Speaker : Prof. A. Yavuz Oruc, U. Maryland, and Director, Computer Systems Architecture Program, 2000-2002, NSF, “The Role of NSF in Computer Architecture Research” (Room: Golden Dome)

1:00. Multithreading I 1:00. Energy Aware Design

3:00. Break 3:00. Break

3:30. Compiler Scheduling 3:30. Superscalar Microarchitecture

5:30. Break 5:00. Break

6:00. Register File and Memory System Design

5:30. Multithreading II

Afternoon

7:30. Break

12:25-6:30. Excursion in Istanbul: Visits to the Hippodrome, Blue Mosque, and Hagia Sophia, followed by a boat tour on the Bosphorus.

Evening 8:00-11:00. Banquet at Feriye Restaurant 9:00-11:00. Business Meeting 7:00-7:30. Closing and Awards

The Bosphorus and the Rumeli Fortress

Keynote Addresses “Systems Trends and their Impact on Future Microprocessor Design”. Tilak Agerwala, Vice President, Systems, IBM Research. (Wednesday, November 20, 2002) Important application domains like simulation, games, and content distribution are placing new demands on microprocessor functionality and performance. Furthermore, future microprocessors will be designed for a very broad range of systems: highly parallel supercomputers, backend servers, desk top systems, and a variety of embedded systems . With hundreds of millions of transistors available to the microprocessor designer today, it is important to identify the functions that will eventually migrate into the processor chip. A high level of integration leads to a host of issues, including balancing on-chip power consumption with high frequency design, overcoming design complexity, achieving system reliability, and breaking the memory performance barrier. The talk will describe emerging applications and industry trends for different categories of systems, discuss some of the exciting research and development challenges these systems will impose on future microprocessor design, and give examples of advanced work at IBM in these areas.

Hagia Sophia -detail

“Right Hand Turn for Power Efficient Computing”. Justin R. Rattner, Intel Fellow, Enterprise Platforms Group, Director, Microprocessor Research, Intel Labs. (Friday, November 22, 2002) Following Moore's Law for microprocessors in the future will be limited by power delivery and dissipation, not by manufacturing or cost. Therefore, performance at any cost will not be an option, and delivering the highest performance in a given power envelope will be the challenge. We will examine power efficiency of microarchitectures and circuits employed, the process technologies used to fabricate these microprocessors, and then point out the inevitable right hand turn that one must make, to improve power efficiency in all these disciplines, to deliver the highest performance when constrained by power. “The Role of NSF in Computer Architecture Research”. Prof. A. Yavuz Oruc, University of Maryland, Director, Computer Systems Architecture Program, 2000-2002, National Science Foundation. (Friday, November 22, 2002) Computer architecture research has been a melting pot of theoretical concepts for devising concrete techniques by which next generation computer systems are designed and put together. From the design of early vacuum tube computers to shaping today's impressive single-chip processors, housing tens of millions of transistors, computer architecture researchers have been at the forefront of an amazing journey of discoveries that have helped usher in the new age of personal computing and global web of information sharing and exchange. In this talk, I will attempt to describe the critical role that the National Science Foundation has played and continues to play in stimulating computer architecture research. The talk will draw from my recent experience as the Director of Computer Systems Architecture Program at NSF. It will explain the delicate dynamics of balancing mainstream computer architecture research projects with new ideas and technology-driven problems such as molecular and nano architectures. The talk will also include a survey of research projects currently funded by the Program and explain the various stages that proposals go through after they are submitted for funding.

Workshops

2nd Workshop on EPIC Architectures and Compiler Technology (EPIC-2). David August (Princeton), Dan Connors (University of Colorado), Carole Dulong (Intel), Rick Hank (Hewlett-Packard). Room: Mercury A&B, Monday 11/18. 8:50AM-3:30PM 4th Workshop on Media and Stream Processors (MSP-4). Vipin Chaudhary (Wayne State University, Cradle Technologies), Jason Fritts (Washington University), Alex Dean (North Carolina State University). Room: Saturn, Monday 11/18 8:30AM-5:30PM

6th Workshop on Multi-threaded Execution, Architecture and Compilation (MTEAC-6). Antonio Gonzalez (UPC Barcelona and Intel), Walid Najjar (University of California, Riverside), Dean Tullsen (University of California, San Diego). Room: Mercury A&B, Tuesday 11/19, 9:00AM-5:00PM 1st Workshop on Application Specific Processors (WASP-1). Alex Orailoglu (University of California, San Diego. Room: Saturn, Tuesday 11/19, 8:00AM-6:00PM

Tutorials

Asynchronous Microprocessor Design. Alain J. Martin, Mika Nystroem (Caltech). Room: Neptune, Monday 11/18. 8:30AM-12:30PM Tutorial on Partially Asynchronous Microprocessors (PAMs). Diana Marculescu (CMU), David Albonesi, Alper Buyuktosunoglu (U. Rochester) Room: Neptune, Monday 11/18 2:00PM-6:00PM From Molecules to Computers. Seth Copen Goldstein (CMU). Room: Mercury C, Monday 11/18, 2:00PM-6:00PM Thermal Management Issues for Microprocessors. Kevin Skadron , Mircia Stan (U. Virginia), David Brooks (Harvard). Room: Neptune, Tuesday 11/19, 8:30AM-12:30PM

An Introduction to Network Processor Research and Design. Patrick Crowley (U. Washington). Room: Mercury C, Tuesday 11/19, 2:00PM-6:00PM. Open Research Compiler (ORC) 2.0 and Tuning Performance on Itanium. Roy Ju, Sun Chan (Intel MRL), Chengyong Wu (ICT CAS), Tin-Fook Ngai (Intel MRL). Room: Mercury C, Tuesday 11/19, 8:30AM-12:30PM. Simics Microarchitect's Toolset. Peter Magnusson (Virtutech). Room: Neptune, Tuesday 11/19, 2:00PM-6:00PM. Lunch will be served at 12:30PM on both 11/18 and 11/19.

Snack room in the Harem, Topkapi Palace Museum

Technical Sessions

Superscalar Design (Wednesday, 9:45-11:45) – Ronny Ronen (Intel), chair

"Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors”. Jose F. Martinez (Cornell University), Jose Renau (University of Illinois), Michael Huang (University of Rochester), Milos Prvulovic, and Josep Torrellas (University of Illinois).

“Characterizing and Predicting Value Degree of Use”. J. Adam Butts and Gurindar S. Sohi (University of Wisconsin).

“Hierarchical Scheduling Windows”. Edward Brekelbaum, Jeff Rupley, Chris Wilkerson, and Bryan Black (Intel Corporation).

“Three Extensions to Register Integration”. Vlad Petric, Anne Bracy, and Amir Roth (University of Pennsylvania).

Multithreading I (Wednesday, 1:00-3:00) – Yale Patt (U. of Texas), chair

“Instruction Fetch Deferral using Static Slack”. Gregory A. Muthler, David Crowe, Sanjay J. Patel, and Steven S. Lumetta (University of Illinois).

“Pointer Cache Assisted Prefetching”. Jamison Collins, Suleyman Sair, Brad Calder, and Dean M. Tullsen (University of California, San Diego).

Microarchitectural Support for Precomputation Microthreads”. Robert S. Chappell (University of Michigan), Francis Tseng (University of Texas, Austin), Adi Yoaz (Intel Corporation), and Yale N. Patt (University of Texas, Austin).

“Master/Slave Speculative Parallelization”. Craig Zilles (University of Illinois) and Guri Sohi (University of Wisconsin)

Compiler Scheduling (Wednesday, 3:30-5:30) – Brad Calder (UC San Diego), chair

“Reduced Code Size Modulo Scheduling in the Absence of Hardware Support”. Josep Llosa (UPC Barcelona) and Stefan Freudenberger (Hewlett-Packard).

“Convergent Scheduling”. Walter Lee, Diego Puppin, Shane Swenson and Saman Amarasinghe(MIT).

“Effective Instruction Scheduling Techniques for an Interleaved Cache Clustered VLIW Processors”. Enric Gibert (UPC Barcelona), Jesús Sánchez, and Antonio González (UPC Barcelona and Intel Corporation).

“Compiler Managed Micro-cache Bypassing for High Performance EPIC Processors”. Youfeng Wu, Ryan Rakvic, Li-Ling Chen, Chyi-Chang Miao, George Chrysos, Jesse Fang (Intel Corporation).

Register File and Memory System Design (Wednesday, 6:00-7:30) – Roy Ju (Intel), chair

“Three-dimensional Memory Vectorization for High Bandwidth Media Memory Systems”. Jesús Corbal, Roger Espasa, and Mateo Valero (UPC Barcelona).

“Dynamic Addressing Memory Arrays with Physical Locality”. Steven K. Hsu (Oregon State University and Intel Corporation), Shih-Lien Lu (Intel Corporation), Shih-Chang Lai (Oregon State University), Ram Krishnamurthy, and Konrad Lai (Intel Corporation).

“Reducing Register Ports for Higher Speed and Lower Energy”. Il Park, Michael D. Powell, and T. N. Vijaykumar (Purdue University).

Energy Efficient Memory Systems (Thursday, 8:00-10:00) – Bill Mangione-Smith (UC Los Angeles), chair

“Generating Physical Addresses Directly for Saving Instruction TLB Energy”. Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul Kandiraju, and Guangyu Chen (Pennsylvania State University).

“Energy Efficient Frequent Value Cache Design”. Jun Yang (University of California, Riverside) and Rajiv Gupta (University of Arizona).

“Compiler-Directed Instruction Cache Leakage Optimization”. Wei Zhang, Ji e Hu, Vijay Degalahal, Mahmut Kandemir, N. Vijaykrishnan, and Mary J. Irwin (Pennsylvania State University).

“Drowsy Instruction Caches - Leakage Power Reduction using Dynamic Voltage Scaling”. Nam Sung Kim (University of Michigan), Krisztián Flautner (ARM), David Blaauw, and Trevor Mudge (University of Michigan).

Compilation and Run-time Systems (Thursday, 10:30-12:00) – Jim Dehnert (Transmeta), chair

“Vacuum Packing: Extracting Hardware-Detected Program Phases for Post-Link Optimization”. Ronald D. Barnes, Erik M. Nystrom, Matthew C. Merten, and Wen-mei W. Hwu (University of Illinois).

“A Faster Optimal Register Allocator”. Changqing Fu and Kent Wilken (University of California, Davis).

“DELI: A New Run-time Control Point”. Giuseppe Desoli (STMicroelectronics), Nikolay Mateev (Hewlett-Packard), Evelyn Duesterwald (IBM), Paolo Faraboschi, and Joseph A. Fisher (Hewlett-Packard).

Simulation and Architecture Evaluation (Friday, 9:30-11:30) – Antonio Gonzalez (UPC Barcelona and Intel), chair

“Microarchitectural Exploration with Liberty”. Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, and David I. August (Princeton University).

“Vector Vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks”. Christoforos Kozyrakis (Stanford University) and David Patterson (University of California, Berkeley).

“Orion: A Power-Performance Simulator for Interconnection Networks”. Hang-Sheng Wang, Xinping Zhu, Li-Shiuan Peh, and Sharad Malik (Princeton University).

“A Framework and Analysis of Modern Graphics Architectures for General-Purpose Computing”. Christopher J. Thompson, Sahngyun Hahn, and Mark Oskin (University of Washington). Energy Aware Design (Friday, 1:00-3:00) – Evelyn Duesterwald (IBM), chair

“Managing Static Leakage Energy in Microprocessor Functional Units”. Steven Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman (University of Rochester).

“Optimizing Pipelines for Power and Performance”. Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip N Strenski, and Philip G Emma (IBM).

“Power Protocol: Reducing Power Dissipation on Off-Chip Data Buses”. Kohinoor Basu, Alok Choudhary, Jay Pisharath (Northwestern University), and Mahmut Kandemir (Pennsylvania State University).

“Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture”. Greg Semeraro, David H. Albonesi, Steven G. Dropsho, Grigorios Magklis, Sandhya Dwarkadas, and Michael L. Scott (University of Rochester).

Superscalar Microarchitecture (Friday, 3:30-5:00) – Sanjay Patel (U. of Illinois), chair

“Fetching Instruction Streams”. Alex Ramirez, Oliverio J. Santana, Josep L. Larriba-Pey and Mateo Valero (UPC Barcelona).

“Register Write Specialization Register Read Specialization: A Path to Complexity-Effective Wide-Issue Superscalar Processors”. André Seznec (IRISA/INRIA), Eric Toullec (IRISA, Université de Rennes I), and Olivier Rochecouste (IRISA/INRIA).

“Exploiting Data-Width Locality to Increase Superscalar Execution Bandwidth”. Gabriel H. Loh (Yale University). Multithreading II (Friday, 5:30-7:00) – Matt Farrens (UC Davis), chair

“Microarchitectural Denial of Service: Insuring Microarchitectural Fairness”. Dirk Grunwald and Soraya Ghiasi (University of Colorado).

“Compiling for Instruction Cache Performance on a Multithreaded Architecture”. Rakesh Kumar and Dean M. Tullsen (University of California, San Diego).

“A Quantitative Framework for Automated Pre-Execution Thread Selection”. Amir Roth (University of Pennsylvania) and Gurindar S. Sohi (University of Wisconsin). Social Events The conference will also offer two social events to the delegates: The conference banquet on November 20th (at 8:00 PM at Feriye Restaurant, Ciragan Cad. No: 124, Ortakoy, Istanbul, (0212) 227 22 16. Busses leave at 7:45PM) and an excursion on November 21st (Visits to the Hippodrome, Blue Mosque and Hagia Sophia, followed by a boat tour of the Bosphorus. Busses leave at 12:25PM. Box lunches will be provided.)

Yerebatan Cistern

Leander’s Tower

Organizing Committee General Chair

Kemal Ebcioglu, IBM T.J. Watson Research Center

Program Co-Chairs Scott Mahlke University of Michigan

B. Ramakrishna Rau, HP Labs

Workshops Chair Erik Altman, IBM Tutorials Chair

Evelyn Duesterwald, IBM Finance Chair Irma Esmer, Intel Local Arrangements Chair Sadun Anik, Garanti Publicity Chair

Dan Connors, University of Colorado

Publications Chair Sanjay Patel, University of Illinois Registration Chair

Emre Ozer, Trinity College, Dublin

Student Advocate Haldun Hadimioglu, Polytechnic University

Faculty Liasons in Turkey Bulent Orencik, Istanbul Technical University Ahmet Akkas, Koc University Steering Committee Richard Belgard, Consultant, Chairman Tom Conte, NC State Kemal Ebcioglu, IBM Matt Farrens, UC-Davis Josh Fisher, HP Labs Wen-mei Hwu, University of Illinois Yale Patt, The University of Texas at Austin Ronny Ronen, Intel Mike Schlansker, HP Labs Andy Wolfe, SONICblue Program Committee Santosh Abraham, Sun Saman Amarasinghe, MIT David August, Princeton Todd Austin, Michigan Pradip Bose, IBM

Program Committee (cont.) Brad Calder, UCSD Doug Carmean, Intel Tom Conte, NCSU Jim Dehnert, Transmeta Srinivas Devadas, MIT Matt Farrens, UC-Davis Guang Gao, Delaware Antonio González, UPC Rajiv Gupta, Arizona Wei Hsu, Minnesota Wen-mei Hwu, Illinois Richard Johnson, Transmeta Roy Ju, Intel Josep Llosa, UPC Bill Mangione-Smith, UCLA Margaret Martonosi, Princeton Sanjay Patel, Illinois Yale Patt, Texas Ronny Ronen, Intel Eric Rotenberg, NCSU Mike Schlansker, HP Jim Smith, Wisconsin Carol Thompson, HP Kees Vissers, Trimedia

MICRO-35 Program at a Glance (all sessions are in the Ball Room) Wednesday 20th Thursday 21st Friday 22nd

8:00. Conference Opening 8:00. Energy Efficient Memory Systems

8:00. Keynote II : Justin R. Rattner, Director, Microprocessor Research, Intel Labs, “Right Hand Turn for Power Efficient Computing” 8:15. Keynote I : Tilak Agerwala, Vice

President, Systems, IBM Research, "Systems Trends and Their Impact on Future Microprocessor Design" 10:00. Break 9:00. Break

9:15. Break

9:45. Superscalar Design

10:30. Compilation and Run-time Systems

9:30. Simulation and Architecture Evaluation Morning

11:45. Lunch 12:00. Break

11:30. Lunch 11:55 – 12:20. Invited NSF Speaker : Prof. A. Yavuz Oruc, U. Maryland, and Director, Computer Systems Architecture Program, 2000-2002, NSF, “The Role of NSF in Computer Architecture Research” (Room: Golden Dome)

1:00. Multithreading I 1:00. Energy Aware Design

3:00. Break 3:00. Break

3:30. Compiler Scheduling 3:30. Superscalar Microarchitecture

5:30. Break 5:00. Break

6:00. Register File and Memory System Design

5:30. Multithreading II

Afternoon

7:30. Break

12:25-6:30. Excursion in Istanbul: Visits to the Hippodrome, Blue Mosque, and Hagia Sophia, followed by a boat tour on the Bosphorus.

Evening 8:00-11:00. Banquet at Feriye Restaurant 9:00-11:00. Business Meeting 7:00-7:30. Closing and Awards

MICRO-35 is sponsored by:

IEEE TC-uARCH

ACM SIGMICRO

and

HP Turkey

National Science

Foundation

and

IBM Türk

and

Intel Turkey

IEEE Turkey Section

and IEEE Region 8

All photos courtesy of the Turkish Tourist Office, New York.