microcontroller & risc architecture (2 marks - question bank)

8/7/2019 Microcontroller & RISC Architecture (2 Marks - Question Bank)

1/61

080290040

MICROCONTROLLER & RISC ARCHITECTURE

PART- AShort Questions & Answers

Compiled by

PROF. N.SHANMUGASUNDARAM,Professor & Head, ECE Department,

Vidyaa Vikas College of Engineering & TechnologyTiruchengode 637214, Namakkal Dt., T.N.


2/61

MICROCONTROLLER AND RISC ARCHITECTURE

(2 MARKS Q & A)

Unit I

INTRODUCTION TO INTEL 8051 ARCHITECTURE

1. What is microcontroller?

Microcontroller is a single IC which contains the CPU with integratedperipherals like memory, serial ports, parallel ports, timer/counter, interruptcontroller, data acquisition interfaces like ADC, DAC.

CPUOn-chip

ROMOn-chip

RAM

Timers I/O Ports Serial Port

Internal blocks of Microcontroller

2. Compare Microprocessor and Microcontroller.

S.No Microprocessor Microcontroller

1 The functional blocks of amicroprocessor are CPU whichcontains ALU, few registers,timing and control unit.

The functional blocks ofmicrocontroller includes a CPU,Timers, Parallel I/O ports, SerialI/O port, and internal RAM andROM memory.

Some microcontrollers have even

ADC and/or DAC on-chip.

2 P operates on byte/word data.Hence, it has LESSBit manipulation instructions.

C operates on bit/byte data.Hence, it has MOREBit manipulation instructions.

3 A P based system requires largeno. of peripherals and hence, itsPCB will be LARGE.

A C based system can be formedwithout using additional peripheralICs. Hence, its PCB will be SMALL.

4 A P based system is used forGeneral purpose computing andData processing applications.

A C based system is used forapplication specific dedicatedsystems.

Eg. Washing machines, Mobilephones, Microwave oven,Elevators, etc.

5 It involves movement of code &data between P and externalmemory.

Hence MORE instructions aremade available for data transferwith external memory.

It involves movement of code &data between internal memory &CPU inside C.

Hence FEWER instructions areavailable for data transfer withexternal memory.


3/61

3. List the features of 8051.

Features of 8051 are:

Data size is 8-bit Address lines is 16-bit (Memory capacity = 216 = 64 KB) Memory capacity of On-chip RAM is 128 Bytes Memory capacity of On-chip ROM is 4 KB Total program memory space is 64KB Total data memory space is 64KB On-chip Timers - 2 x 16-bit each 4 x 8-bit I/O Ports One full duplex Serial port (TxD & RxD) Six Interrupt sources (inclusive of two H/w interrupts INT0, INT1)

4. Draw the Pin diagram of 8051.

5. List the alternate functions of Port3 in 8051.


4/61

6. Draw the program memory organization in 8051.

7. Draw the data memory organization in 8051.

8. Draw the Internal RAM memory organization in 8051.


5/61

9. What is meant by bit addressable memory?

Out of the 128 bytes of internal RAM in 8051, only 16 bytes of it are bit-addressable. The bit addressable RAM locations are 20H to 2FH. These 16bytes of RAM provide 128 bits (16 bytes x 8 bits) bit-addressability with theaddress from 00H to 7FH.

10. What is Program Status Word?PSW is another name for Flag register. It holds various flags, which areuseful for the programmer to test the condition of the result and makedecisions. The format of PSW of 8051 microcontroller is shown in fig below.

Program Status Word (Flag Register)

The PSW consists of four math flags and two register bank select bits. The

math flags are Carry, Auxiliary Carry, and Overflow and Parity flags.

The register bank select bits RS1 and RS0 are used to select any one of the

four register banks of the internal RAM. At any instant, the microcontrollercan work with (or access) only one register bank, which is selected by thesebits.

11. State the function of RS1 and RS0 bits in the flag register of 8051.

12. List the various registers used in 8051.

The registers used in 8051 are Accumulator (A), B-Register,Stack Pointer (SP), Program counter (PC), Flag Register (PSW),Data Pointer (DPTR), Timer Registers (TH0, TL0, TH1, TL1) and other SFRs


6/61

13. Define Stack Pointer.

The stack pointer is 8 bit register which points the stack top. It isincremented before data is stored during PUSH and CALL instructions. Afterreset of the processor, the SP is 07H.

14. Define Program Counter.

Program counter is a 16 bit register which holds the 16-bit address of theprogram instruction currently executed by the processor. PC is automaticallyincremented after every fetch of instruction byte from the memory for its

execution.

15. What is the significance of DPTR?

DPTR is a 16-bit register which is used as Data Pointer for external datamemory. It holds the 16-bit address of the data stored in the external datamemory.

This can also be used as two numbers of 8-bit data pointers namely DPH andDPL. The 8-bit data pointers are used for accessing internal RAM and SFR.

The contents of data pointer are programmable using instructions.

16. What is the significance of pin in 8051?

is an output pin and stands for Program Store Enable. Whenexternal ROM holds the code, this pin is connected to OE pin of the ROM.

17. What is the significance of pin?

EA stands for External Access. By applying LOW to this pin, makes 8051 toomit internal 4KB on-chip ROM and use only external memory for programstorage. By applying HIGH to this pin, makes 8051 to use internal 4KB on-chip ROM along with external memory for program storage.


7/61


8/61

20. Why all pins of a port is loaded with value FF before using it?

All ports of 8051 are configured by default as Output port.Hence, to make it configured as Input Port, all pins of a port are loaded withvalue FF i.e., 1111 1111.

20. Justify why the crystal oscillator frequency in 8051 is chosen as

11.0592Mhz.

When an 8051 microcontroller based system is connected to an external

serial communication device, the speed of the data transfer should be instandard baud rates such as 4800, 9600, etc.

Only XTAL (Crystal Oscillator) of 11.0592 MHz can provide such standardbaud rates, after down scaling down by 12, 32 at UART and by a factor set intimer register TH1.

21. Draw the format of TMOD register of 8051.

22. List the modes of Timer in 8051.

The modes of timer in 8051 are chosen with the help of two bits,viz., M0 & M1 in TMOD register. The different modes of timer are as follows.

M1 M0 Mode Description of Timer mode

0 0 0 13 bit timer

0 1 1 16-bit timer

1 0 2 8-bit timer with auto reload

1 1 3 Split timer

23. What is the significance of C/T bit in TMOD register of 8051?

The C/T bit in the TMOD register is a selector bit for the type of operation wewant to perform in the timer register. HIGH in that bit indicates Counteroperation and LOW in that bit indicates Timer operation.

0 Timer operation

1 Counter operation


9/61

24. What is the significance of TRx bit in TCON register of 8051?

TRx bit in the TCON register is used to Start / Stop the timer register forboth timer and counter operation, by setting that bit with value 1 or 0.

25. Draw the format of TCON register of 8051.

26. Explain the Timer operation of 8051.

In this mode, the timer register is used to generate the time delay using theclock signal applied to the processor.

An initial count is loaded in the timer register. When the timer is started, thetimer register content gets incremented after every machine cycle. When thetimer register crosses (i.e., overflows) the count FFFFH and goes to 0000H,the timer overflow flag in TCON register becomes set.

Hence, by loading appropriate value in the timer register, a specific timedelay can be generated using timer. One machine cycle consists of 12 clocksignal periods and the delay is equal to count value loaded * time period ofone machine cycle.


10/61

27. Explain the Counter operation of 8051.

In this mode, the timer register is used to count the external events with thehelp of external pulses received through the counter input (t0 & T1).

An initial count is loaded in the timer register. When the timer is started, thetimer register content gets incremented after every external pulse. When thetimer register crosses (i.e., overflows) the count FFFFH and goes to 0000H,the timer overflow flag in TCON register becomes set. Hence, by loadingappropriate value in the timer register, counting of external event can beperformed using timer.

28. List the Interrupt sources in 8051.

The Six Interrupt sources in 8051 are

RESET INT0, INT1 TF0, TF1 SPI (TI/RI)

29. What is the default priority of the interrupts in 8051?


11/61

30. Draw the format of IE register.

31. Draw the format of IP register.

32. What are the types of serial communication?

The serial communication can be,

Synchronous (continuous) Iso-Synchronous (with regular time intervals) Asynchronous (with irregular time intervals)

33. Draw the Frame format of Asynchronous serial communication.

The asynchronous data frame starts with a Start bit (0), followed by databyte (LSB first and MSB last) and a Stop bit (1).


12/61

34. Define Baud rate.

Baud Rate: It is the speed of serial data transfer, expressed in bits/sec.

The standard baud rates used for serial communication are

110, 150, 300, 600, 1200, 2400, 4800, 9600, 19200

35. Explain the Serial Communication in 8051.

SERIAL COMMUNICATION IN 8051

The serial communication in 8051 is carried out using two SFR registers,

1. SCON2. SBUF

SCON register is used to control and set the mode of serial communication.

SBUF register is used to dump the data before serial transmission and holddata after serial reception.

36. Draw the format of SCON register of 8051.


13/61

37. What are the modes of asynchronous serial communication in 8051?

The mode of serial communication is decided by two bits SM0 & SM1 inSCON register. The details of the various modes are described in the tablegiven below.

SM0, SM1 Mode Serial Mode Description Baud rate

00 0 8-bit Shift register FOsc / 12

01 1 8-bit UART Variable10 2 9-bit UART FOsc / 32 or 64

11 3 9-bit UART Variable

Note: Out of all modes, Mode-1 is commonly used mode for serial data transfer in 8051.

38. Explain how baud rate is calculated for serial data transfer in mode 1?

General Expression for setting baud rates using TH1 register is given below.

39. Explain how baud rate is set in 8051 for serial data transfer usingtimer register?

Based on the baud rate needed for serial communication, the timer registerTH1 is loaded with values as per the following calculation.

External XTAL oscillator frequency is chosen as 11.0592 MHz is to make theUART output as 28800 Hz, so that the various baud rates are obtained bydividing this frequency 28800 Hz with different values set in TH1 register.

Example

For baud rate of 9600; Divisor needed is 03H (because 28800 / 03 = 9600)Value loaded in TH1 register = 00H 03H = FDH

The sample values loaded in TH1 register for different baud rates.

Baud rate Frequency DivisorHex value loaded in

TH1 register

9600 03 FD

4800 06 FA

2400 12 EE

1200 24 DC


14/61

40. Draw the format of PCON register in 8051.

41. Compare the features of 8051, 8052 and 8031.


15/61

Unit II

THE 8051 INSTRUCTION SET AND PROGRAMMING

1. List the addressing modes of 8051.

The 8051 has the following types of addressing.

Immediate Addressing Direct Addressing Register Addressing Register Indirect Addressing Implied Addressing Relative Addressing

2. List the various Instructions available in 8051 microcontroller.

Data Transfer Instructions Arithmetic Instructions Logical Instructions Boolean variable Manipulation Instructions Program and Machine Control Instructions

3. List the steps to create the executable code from assembly program.


16/61

4. List the widely used assembler directives of 8051.

S.No.AssemblerDirective

Definition and usage

1. ORG The ORG directive is used to indicate the origin ofthe address of the assembly program

2. DBThe DB directive is the most widely used data

directive in the assembler to define data. Thenumbers can be in decimal, hex, or ASCII formats.Regardless of which format is used, the assemblerconverts the numbers into hex.

3. EQU EQU stands for Equate. This directive is used todefine a constant without occupying a memorylocation.

4. END The END directive is specified in the last line of the8051 assembly program to indicate the assemblerthe end of the source (.asm) file.

5. Draw and list the flags in PSW of 8051.

6. When is the overflow flag set?

In 8-bit signed number operations; OV is set to 1 if either of the followingtwo conditions occurs.

i) There is a carry from D6 to D7; but NO carry out of D7 (CY=0)ii) There is a carry out from D7 (CY=1); but NO carry from D6 to D7.


17/61

7. List the instructions that affect the flag bits.

8. List the Conditional jump instructions in 8051.

9. What are Read-Modify-Write instructions?

Some instructions read the I/O port and others read the latch. Since theseinstructions that read a latch normally reads a value, possibly changing itand rewrites it to the latch, these instructions are called Read-Modify-Writeinstructions.

The instructions that read the latch are ANL, ORL, XRL, JBC, CPL, INC, DEC,DJNZ, CLR PX.Y, SETB PX.Y, etc.


18/61

10. What is the limitation of Indirect addressing mode?

The indirect addressing mode is implemented using R0 & R1 registers whichare 8-bit wide. Hence, this mode supports accessing of internal Ram only.

11. Explain the operation of SWAP A instruction.

The SWAP instruction of 8051 interchanges the contents of lower nibble andupper nibble of the Accumulator.

Eg. If the content of Acc is 56H before SWAP instruction; the content in

Acc becomes 65H after execution of SWAP instruction.

12. Explain the operation of DIV AB instruction.

DIV AB performs division operation (divide A by B) on two 8-bit data.The Dividend is stored in Acc and Divisor is stored in B register beforedivision operation is performed. After division operation; the results i.e.,

quotient is stored in Acc and the remainder is stored in B register

Eg. MOV A, #95 ; Load 95 into AccMOV B, #10 ; Load 10 into B-registerDIV AB ; Now, Acc=09 (Quotient) & B=05 (Remainder)

13. Explain the operation of MUL AB instruction.

MUL AB performs multiplication operation on two 8-bit data. One operandis stored in Acc and the other operand is stored in B register before

multiplication operation is performed. After multiplication operation; theresults i.e., quotient is stored in Acc and the remainder is stored in B register

Eg. MOV A, #65 ; Load 65 into AccMOV B, #25 ; Load 25 into B-registerMUL AB ; Now, 65 x 25 = E99

Where B=0E & A=99

14. Explain the operation of DJNZ instruction.

DJNZ stands for Decrement and Jump, if Not Zero.

This instruction decrements an 8-bit number stored in a register / memorylocation, and the program control branches to a specific location if theresultant number after decrement is not zero. The branching is done byrelative addressing.

The different formats of DJNZ instruction are


19/61

15. Explain the operation of CJNE instruction.

CJNE stands for Compare and Jump, if Not Equal.

This instruction compares two 8-bit numbers and the program control

branches to a specific location if the numbers are not equal. The branching isdone by relative addressing.

The different formats of CJNE instruction are

16. Explain the operation of Rotate instructions in 8051.


20/61

17. Explain why SJMP instruction is used in the place of HLT in 8051?

As microcontroller is used for a dedicated and repetitive application, therewill not be a situation in which the microcontroller is switched ON and no

program is running in it. Hence, there is no necessity to have HLTinstruction in the instruction set of microcontroller.

At the same time, when we want to terminate the execution of a program in8051, we use SJMP to make the program execution remain in the sameinstruction.


21/61

18. Specify the single instruction, which clears the most significant bit of

B register of 8051, without affecting the remaining bits.

Single instruction, which clears the most significant bit of B register of 8051,

without affecting the remaining bits, is CLR B.7

19. Show how 8051 would represent -5.

The steps for representation of -5 in 8051 are as follows.

Represent 5 in 8-bit binary - 0000 0101 Invert each bit - 1111 1010 Add 1 to inverted bits - 1111 1011 = FBH

The answer is FBH

20. What are the registers that are used for Timer operations?

The two 16-bit timer registers are TIMER0 & TIMER1.

The two registers that control the operation of timers are TMOD and TCON

registers.

21. What is Auto-reload feature in 8-bit mode of timer operation?

The timers in 8051 (Timer0 and Timer1) can be operated in 4 differentmodes and mode-2 of it is called 8-bit Timer mode with Auto-reloadoperation. When the count in timer register (TL) reaches the maximum value

(FF), the 8-bit initial count value is reloaded from TH to TL registerautomatically.

This mode is used for setting up baud rate for serial communication in 8051.

22. What is role of GATE bit in TCON register?

Timer operation can be controlled either through software or hardware andGATE bit in TCON register decides the selection of control (H/w or S/w) forthe timers.

23. List the steps in programming the Timers.

Choose the Timer (Timer0 or Timer1) Decide the mode of control for timer (through GATE bit of TMOD) Decide the operation (Counter or Time Delay through C/T bit of TMOD) Select the mode of operation (through M0 & M1 bits of TMOD) Accordingly to above, set the Hex value in TMOD register Load the initial count value in Timer register (TH & TL) Start the Timer (by setting 1 I TR bit of TCON) Check whether TF bit of TCON has become 1 When TF becomes 1; Stop the timer (by clearing the TR bit of TCON)


22/61

24. List the sources of Interrupt in 8051.

25. What is the importance of EA bit in IE register of 8051?

EA stands for Enable All and it is D7 bit of IE register. Hence, beforeexecuting a program, EA bit has to be set to 1 to enable all interrupts of8051.

26. What is interrupt polling?

The interrupts can be serviced by two methods.

I Method: Until receipt of an interrupt; the processor can execute the

instructions and the interrupt sub routines (ISR) can be invokedupon receipt of interrupt at hardware interrupt pins.

II Method: Interrupt Polling is the second method in which the processorperiodically checks the status of the external devices for interruptand services them.

Interrupt polling method consumes the processor time and

hence, this scheme is not used in most of the applications.

27. List the default priority of the interrupts in 8051?

The default priority of interrupts in 8051 is listed below from highest tolowest priority.

Interrupts Priority

IE0 Ext. Interrupt 0

TF0 Timer0 FlagIE1 Ext. Interrupt 1

TF1 Timer1 Flag

RI / TI Serial Comm. Interrupt

TF2 Timer2 Flag (in 8052 only)


23/61


24/61

33. What is RS232 standard?

RS232 is a serial communication standard adopted by electronics industrywith -3V to -25V for level 1 and +3V to +25V for level 0. But, themicrocontroller and most of the peripheral ICs support only TTL / CMOS logic

which needs MAX232 IC for level conversion to make it compatible withRS232 logic.

34. What is UART?

UART stands for Universal Asynchronous Receiver Transmitter.

8051 supports Asynchronous mode for serial communication (mode-1) andSM0 & SM1 bits of the SCON register decides the mode of operation forserial communication.

35. Explain the operation of IC MAX232.

MAX232 is a voltage level converter IC from Maxim Corporation. It operateson +5V power source as 8051 and it converts the TTL voltage level atMicrocontroller to RS232 voltage level at the Computer or any external serialcommunication devices.

36. List the steps in programming for Serial communication in 8051.

FOR TRANSMISSION:

Set the baud rate for serial communication by choosing appropriateHex value in TMOD and Timer register (TH).

Load the data in SBUF register Start the Timer (by making TR bit = 1) Check the status of TI flag in SCON register When TI flag becomes 1; Stop the timer (by making TR bit = 0) After reloading the next data, repeat the above process from step 2.


25/61

FOR RECEPTION:

Set the baud rate for serial communication by choosing appropriateHex value in TMOD and Timer register (TH).

Start the Timer (by making TR bit = 1) Check the status of RI flag in SCON register When RI flag becomes 1; Stop the timer (by making TR bit = 0) Copy the received data at SBUF register and repeat the above process

from step 2.


26/61

PROGRAMMING EXAMPLES


27/61


28/61


29/61


30/61

Unit III

THE 8051-REAL WORLD INTERFACING

1. Draw the interface diagram for connecting LCD with 8051.

2. List and describe the function of pins of LCD.

3. List the status of RS, R/W and E pins for data & command operationsin LCD.

Pin / Operation Command Data

RS (Register Select) 0 1

R/W (Read/Write)0 Write1 Read

0 Write1 Read

E (Enable) H-to-L Pulse H-to-L Pulse


31/61

4. List and describe the LCD command codes.

5. List the two methods for sending data / command to LCD.

I Method: Send the data / command to LCD after apredefined time delay.

II Method: Send the data / command to LCD after checking the busy flag

(D7 bit of Status register) in LCD.

6. Draw the structure of stator windings & Rotor of Stepper motor.


32/61

7. List the normal steps sequence for stepper motor.

8. List the other steps sequence for stepper motor.

The other step sequences for stepper motor are

9. What is a Step angle?

Step angle is the minimum angle of rotation made by the rotor of thestepper motor. Based on the step angle, the no. of steps to make onecomplete revolution varies accordingly.


33/61

9. How the speed of stepper motor can be controlled?

The speed of stepper motor can be controlled by introducing a time delay inbetween the steps sequence.

10. Draw the connection of stepper motor with 8051.

11. What is the role of ULN2003IC in stepper motor interface with 8051?

As 8051 has limited capacity; ULN2003 driver IC is used to deliver therequired current to the coil windings and drive the stepper motor.

12. Draw the signal flow diagram of 8255 and describe its operation.

The 8255 is a Programmable PeripheralInterface (PPI) IC, which supports paralleldata transfer between microcontroller andexternal devices.

It has three ports (Port A, Port B and Port C).These three ports can be programmed to

operate either in I/O or BSR mode.In I/O mode, it can be programmed to

operate in Mode_0 (simple I/O), Mode_1(Hand shake I/O) and Mode_2 (Bi-directionalI/O) modes.

Address lines A0 & A1 are used to select theports (A, B or C) and Control register for read/ write operations.


34/61

13. Draw the control word format for I/O mode operation in 8255.

13. Draw the control word format for BSR mode operation in 8255.

14. Draw the 8255 interface diagram with ADC and 8051.


35/61

15. Programming example for 8255.


36/61

16. Draw the pin diagram of SRAM and DRAM.The pin diagram of SRAM and DRAM is shown below.

17. Draw the two methods of address decoding logic used for external

memory.

I Method: Logic gates as Address Decoder

II Method: 3x8 Decoder as Address Decoder


37/61

18. What is meant by demultiplexing of address and data lines in 8051?

Due to shortage of pins in 8051, the address lines (A0-A7) and data lines(D0-D7) are combined as (AD0-AD7). The process of separating the addressand data lines with the help of ALE signal and Latch (74LS373) is calledDemultiplexing.

19. Draw the interface diagram for external program memory with 8051.

Fig. Interfacing External Program Memory


38/61

20. Draw the interface diagram for external data memory with 8051.

Fig. Interfacing External Data Memory

21. Draw the interface diagram for external data & program memorywith 8051.


39/61

22. Find the address range of the given memory design?

The address lines used in memory is A0-A13 (14 lines) and the memorycapacity is 16KB (214 = 16KB).

As per the given address decoding logic, the address lines A14=1 andA15=0. Therefore, the address range is as follows.

A15 A14 A13 ~ A0 Hex Addr

0 1 00 0000 0000 0000 4000

0 1 11 1111 1111 1111 7FFF

23. What is checksum byte?

In order to detect errors, the last byte in a block of data is calculatedthrough a procedure to detect errors and it is called as Checksum Byte.

Each data byte in a block of data is sequentially added and the carry isignored in each addition. The final value obtained in such addition is calledChecksum byte.

24. What is memory refreshing in DRAM and why is it needed?

The information (one-bit) stored in DRAM is in the form of electric charge injunction capacitance of a MOS transistor. This charge slowly decays over aperiod of time and it has to be restored back before it gets completely

decayed. Thus, the process of restoring the stored information in the MOStransistor is called memory refreshing.

25. Compare MOVC and MOVX instructions.MOVC: MOVC is a data transfer instruction which is used for transfer of

program code between external program memory and the

internal registers of 8051 microcontroller.Eg. MOVC A, @A+PC

MOVX: MOVC is a data transfer instruction which is used for transfer ofdata byte between external data memory and the internalregisters of 8051 microcontroller.Eg. MOVX A, @A+DPTR


40/61

26. What is Signal conditioning?

The process of removing the unwanted signal, amplifying and converting theoutput of sensor into voltage form is called Signal Conditioning.

27. Explain linear and non-linear sensors with an example.

If the relationship between the output and input of a sensor is linear; the sensor

would be called as Linear sensor and otherwise it is called as Non-linear Sensor.

Eg. Linear Sensor - LM34, LM35 (Temperature sensors)

Non-linear Sensor - LDC (Light Dependent Resistor)

28. With Vref/2=0.64V in ADC804,

Find the Vin for the output D0-7=11111111?

Since Vref / 2 = 0.64 V; the full scale reference voltage Vref is 1.28 V.Therefore, the output for Vin = 1111 1111 is 1.28 V (i.e., Vref value).

29. In ADC804, what is the VRef/2 value for step size of 20mV?

The resolution of ADC804 is 8-bits and hence it can have 28 = 256 inputcombinations.

If the step size is 20mV; then the full scale value for 256 combinations is256 x 20mV = 5.12 V

Therefore; the Vref / 2 = Full scale value / 2 = 5.12 V / 2 = 2.56 V (ans).

30. Which pin of ADC804 indicates the end-of-conversion?

INTR pin of ADC804 indicates the end-of-conversion to the microcontroller.

31. What is the conversion time of an ADC?

It is the time taken to completely convert the analog signal into a digitalsignal in the A/D converter and the minimum conversion time in ADC804 is110S.


41/61

32. What is the use of LM336 IC in DAC0808 interface?

The DAC requires a constant and regulated reference signal. LM336 is a ICwhich provides the regulated signal for reference with the help of Zenerdiode in it.

33. What is the use of LM336 IC in DAC0808 interface?

The DAC requires a constant and regulated reference signal. LM336 is a ICwhich provides the regulated signal for reference with the help of Zenerdiode in it.

35. Draw the interface diagram of DAC0808 with 8051.

36. Write a program for saw-tooth wave generation using DAC0808.


42/61

ARM PROCESSOR

Unit IV:

1. Define Pipelining.Starting the execution of next instruction before the current instructionexecution is finished with the available hardware resources is called

pipelining. This is achieved by splitting the execution of each instruction formore than one stage and allocating appropriate hardware for each stage. Toimprove the utilization of hardware resources, and also the processorthroughput, pipelining organization is implemented.

2. What are the sequences of steps in pipelining?A typical pipelining sequence may be as follows: Fetch fetch instruction from memory. Decode generating control signals for that instruction. Register accessing any operands from register. ALU combine the operands to produce results or memory address. Memory access memory for a data operand. Result write the result back to the register bank.

3. What are the hazards occur in pipelining?Read-after-write pipeline hazard occurs when an instruction waits for an

operand which is the result of the previous instruction.

Branching hazards since branch instructions modify the flow of program,

it flush and refill the pipeline.

4. List the features of RISC architecture. Fixed 32-bit instruction size with predefined formats. Load - store architecture. Large register bank of 32bit registers.

5. List the features of RISC processor. Hardwired decode logic. Pipelined execution. Single cycle execution.

6. Mention the advantages and drawbacks of RISC.Advantages: Smaller die size. Shorter development time. Higher performance. Higher clock rate with single cycle execution.Drawbacks: RISCs generally have poor code density. RISCs dont execute x86 code.


43/61

7. How higher clock rates are achieved in RISC?

Higher clock rates is achieved by, Single cycle execution. High memory access rate.

8. What are the factors to be considered for low power circuit design?Minimize the power supply voltage, Vdd.Minimize the circuit activity, A.Minimize the number of gates.Minimize the clock frequency.

9. Mention the features of RISC which are used and rejected in ARMprocessors.

Features used: 1. Load store architecture

2. Fixed-length 32-bit instructions3. 3-address instruction formats.

Features rejected: 1. Register windows

2. Delayed branches3. Single cycle execution of all instructions.

10. Explain the ARM CPSR format.CPSRCurrent Program Status Register is used to store the status bits.

31 28 27 8 7 6 5 4 0N Z C V unused I F T mode

Mode [4:0] (lower 5 bits) represents the processor operating mode. T 5th bit: represents currently ARM or Thumb instruction is executed. I, F 6th, 7th bits: interrupt flag and fast interrupt flag. N, Z, C, V Negative, Zero, Carry, overflow flags.

11. How data items are arranged in memory system?Memory may be viewed as a linear array of bytes numbered from zero up to2^32-l. Data items may be 8-bit bytes, 16-bit half-words or 32-bit words. Aword-sized data item must occupy a group of four byte locations starting ata byte address which is a multiple of four. Half-words occupy two bytelocations starting at an even byte address.


44/61

12. Define Load-store architecture.This means that the instruction set will only process (add, subtract, and so

on) values which are in registers (or specified directly within the instructionitself), and will always place the results of such processing into a register.

The only operations which apply to memory state are ones which copymemory values into registers (Load instructions) or copy register values intomemory (store instructions).

13. List the types of ARM instructions.All ARM instructions fall into one of the following three categories:1. Data processing instructions.

2. Data transfer instructions3. Control flow instructions

14. Define supervisor mode.The ARM processor supports a protected supervisor mode. The protectionmechanism ensures that user code cannot gain supervisor privileges withoutappropriate checks being carried out to ensure that the code is notattempting illegal operations. These functions generally include any accessesto hardware peripheral registers, and to widely used operations such ascharacter input and output.

15. List the features of ARM instruction set.The most notable features of the ARM instruction set are:

The load-store architecture; 3-address data processing Conditional execution of every instruction; load and store multiple register instructions; Single instruction that executes in a single clock cycle; Open instruction set extension through the coprocessor instruction set Highly dense 16-bit compressed representation of the instruction set

in the Thumb architecture.

16. How I/O systems are handled in ARM?The ARM handles I/O (input/output) peripherals (such as disk controllers,network interfaces, and so on) as memory-mapped devices with interrupt

support.

The internal registers in these devices appear as addressable locations withinthe ARM's memory map and may be read and written using the same (load-store) instructions as any other memory locations.


45/61

17. Mention the development tools available for ARM. ARM C compiler. ARM assembler. The linker. ARM symbolic debugger. ARMulator.

.

18. Define ARMulator. Give its various levels of accuracy.The ARMulator (ARM emulator) is a suite of programs that models thebehavior of various ARM processor cores in software on a host system. It canoperate at various levels of accuracy:

Instruction-accurate modeling gives the exact behavior of the system statewithout regard to the precise timing characteristics of the processor.

Cycle-accurate modeling gives the exact behavior of the processor on a cycleby- cycle basis, allowing the exact number of clock cycles that a programrequires to be established.

Timing-accurate modeling presents signals at the correct time within a cycle,

allowing logic delays to be accounted for.

19. Give the steps in exception handling.The current state is saved by copying the PC into rl4_exc and the CPSR intoSPSR_exc (where exc stands for the exception type). The processoroperating mode is changed to the appropriate exception mode. The PC isforced to a value between 0016 and 1C16, the particular value depending onthe type of exception.

20. Define Jump-start tools.The Jumpstart tools from VLSI Technology, Inc., include the same basic setof development tools but present a full X-windows interface on a suitableworkstation rather than the command-line interface of the standard ARMtoolkit. There are many other suppliers of tools that support ARMdevelopment.

21. What are the principal components in 3-stage pipelining?The principal components in 3-stage pipelining are:

The register bank The barrel shifter The ALU The address register and incrementer The data registers The instruction decoder and associated control logic.


46/61

22. What are the factors considered to view breaks in ARM pipeline.

The simplest way to view breaks in the ARM pipeline is to observe that:

All instructions occupy the data-path for one or more adjacent cycles.

For each cycle that an instruction occupies the data-path, it occupies thedecode logic in the immediately preceding cycle.

During the first data-path cycle each instruction issues a fetch for thenext instruction but one.

Branch instructions flush and refill the instruction pipeline.

23. How performance of a processor can be increased?There are only two ways to increase performance:

Increase the clock rate, fclk. - This requires the logic in each pipelinestage to be simplified and, therefore, the number of pipeline stages to be

increased.

Reduce the average number of clock cycles per instruction, CPI .- Thisrequires either that instructions which occupy more than one pipeline slotin a 3-stage pipeline ARM are re-implemented to occupy fewer slots, or

that pipeline stalls caused by dependencies between instructions arereduced, or a combination of both.

24. What is meant by Von-Neumann bottleneck? Any stored-program computer with a single instruction and data memory

will have its performance limited by the available memory bandwidth.

The fundamental problem with reducing the CPI relative to a 3-stage coreis related to the von Neumann bottleneck.

To get a significantly better CPI the memory system must deliver morethan one value in each clock cycle.

25. What is Data forwarding?The only way to resolve data dependencies without stalling the pipeline is tointroduce forwarding paths.

Forwarding paths allow results to be passed between stages as soon as theyare available, and the 5-stage ARM pipeline requires each of the three source

operands to be forwarded from any of three intermediate result registers.

26. How clocking scheme is implemented in ARM?The design is based around 2-phase non-overlapping clocks, which aregenerated internally from a single input clock signal. This scheme allows the

use of level-sensitive transparent latches. Data movement is controlled bypassing the data alternately through latches which are open during phase 1and latches which are open during phase 2. The non-overlapping property ofthe phase 1 and phase 2 clocks ensures that there are no race conditions inthe circuit.


47/61

27. Mention the delays to be considered for minimum data path cycle time.

The minimum data-path cycle time depends on: The register read time; The shifter delay;

The ALU delay; The register write set-up time;

The phase 2 to phase 1 non-overlap time.

28. Explain the types of multiplier used in ARM processors.Two styles of multiplier have been used:

Older ARM cores include low-cost multiplication hardware that supportsonly the 32-bit result multiply and multiply-accumulate instructions.

Recent ARM cores have high-performance multiplication hardware andsupport the 64-bit result multiply and multiply-accumulate instructions.

29. Mention the structural components of ARM control logic.The control logic on the simpler ARM cores has three structural components:

1. An instruction decoder PLA (programmable logic array).2. Distributed secondary control - to select other instruction bits and/or

processor state information to control the datapath.

3. Decentralized control units for specific instructions that take a variablenumber of cycles to complete (load and store multiple, multiply and

coprocessor operations).

30. Define the mechanisms used to implement processor core.There are two principal mechanisms used to implement an ARM processorcore (or any other core, for than matter) on a particular process:

A hard macrocell is delivered as physical layout ready to be incorporated

into the final design;

A soft macrocell is delivered as a synthesizable design expressed in a

hardware description language such as VHDL.

31. List the features of co-processor architecture.The coprocessors most important features are:

Support for up to 16 logical coprocessors.

Each coprocessor can have up to 16 private registers of any reasonablesize; they are not limited to 32 bits.

Coprocessors use load-store architecture, with instructions to performinternal operations on registers, instructions to load and save registersfrom and to memory, and instructions to move data to or from an ARM

register.


48/61

32. What is a co-processor?

The ARM architecture supports a general mechanism for extending theinstruction set through the addition of coprocessors. The most commonuse of a coprocessor is the system coprocessor used to control on-chip

functions such as the cache and memory management unit on theARM720.

A floating-point ARM coprocessor has also been developed, andapplication-specific coprocessors are a possibility.

Coprocessor data operations are completely internal to the coprocessorand cause a state change in the coprocessor registers.

ARM coprocessors have their own private register sets and their state iscontrolled by instructions that mirror the instructions that control ARMregisters.

33. Define the handshaking signals used for coprocessor interfacing.The handshake uses three signals:

1. cpi (from ARM to all coprocessors).

This signal, which stands for 'Coprocessor Instruction', indicates that theARM has identified a coprocessor instruction and wishes to execute it.

2. cpa (from the coprocessors to ARM).

This is the 'Coprocessor Absent' signal which tells the ARM that there is nocoprocessor present that is able to execute the current instruction.

3. cpb (from the coprocessors to ARM).

This is the 'Coprocessor Busy' signal which tells the ARM that the

coprocessor cannot begin executing the instruction yet.

34. What are the signals used in ARM bus transactions?The memory bus interface signals include the following:

A 32-bit address bus, A [31:0], which gives the byte address of the datato be accessed.

A 32-bit bidirectional data bus, D [31:0], along which the data istransferred.

Signals that specify whether the memory is needed (mreq) and whetherthe address is sequential (seq); these are issued in the previous cycle sothat the memory control logic can prepare appropriately.

Signals that specify the direction (r/w) and size (b/w on earlierprocessors; mas[1:0] on later processors) of the transfer.

Bus timing and control signals (abe, ale, ape, dbe, lock, bl[3:0]).


49/61

35. List the functions of control logic in memory interfacing.The control logic performs the following functions:

It decides when to activate the RAM and when to activate the ROM.

It controls the byte write enables during a write operation. It ensures that the data is ready before the processor continues.

36. Define the buses specified in AMBA.Three buses are denned within the AMBA specification:

The Advanced High-performance Bus (AHB) is used to connect high-performance system modules. It supports burst mode data transfers and

split transactions, and all timing is reference to a single clock edge.

The Advanced System Bus (ASB) is used to connect high-performancesystem modules. It supports burst mode data transfers.

The Advanced Peripheral Bus (APB) offers a simpler interface for low-performance peripherals.

37. Define AMBA. ARM processor cores have bus interfaces that are optimized for high-

speed cache interfacing and required to allow the ARM to communicatewith other on-chip macrocells.

ARM Limited specified the Advanced Microcontroller Bus Architecture,AMBA, to standardize the on-chip connection of different macrocells.

38. What are the signals used by bus master?The bus master which holds the grant; then proceeds with the bustransaction using the following signals:

Bus transaction, BTRAN [1:0], indicates whether the next bus cycle will beaddress-only, sequential or non-sequential.

The address bus, BA[31:O]

Bus transfer direction, BWRITE.

Bus protection signals, BPROT[1:0], which indicate instruction or data

fetches and supervisor or user access.

The transfer size, BSIZE[1:0], specifies a byte, half-word or word

transfer.

Bus lock, BLOK, allows a master to retain the bus to complete an atomicread-modify-write transaction.

The data bus, BD[31:0], used to transmit write data and to receive readdata.


50/61

39. What are the signals used by bus slave unit?

A slave unit may process the requested transaction immediately, acceptingwrite data or issuing read data on BD [31:0], or signals one of the followingresponses:

Bus wait, BWAIT, allows a slave module to insert wait states when it

cannot complete the transaction in the current cycle.

Bus last, BLAST, allows a slave to terminate a sequential burst to forcethe bus master to issue a new bus transaction request to continue.

Bus error, BERROR, indicates a transaction that cannot be completed.If the master is a processor it should abort the transfer.

40. Why bus reset signal is required? It takes some time for a clock oscillator to stabilize after power-up, so

there may be no reliable clock available to sequence all the modules into

a known state. In any case, if two or more modules power-up trying to drive bus lines in

opposite directions, the output drive clashes may cause power supply

crow-bar problems which may prevent the chip from powering upproperly at all.

Correct ASB power-up is ensured by imposing an asynchronous resetmode that forces all drivers off the bus independently of the clock.

41. Define APB? The ASB offers a relatively high-performance on-chip interconnects which

suits processor, memory and peripheral macrocells with some built-ininterface sophistication.

For very simple, low-performance peripherals, the overhead of theinterface is too high. The Advanced Peripheral Bus is a simple, staticbus which operates as a stub on an ASB to offer a minimalist interface tovery simple peripheral macrocells.

42. Why AHB is replaced for ASB in high performance systems?The following features differentiate the AHB from the ASB:

It supports split transactions, where a slave with long response latencycan free up the bus for other transfers while it prepares its data fortransmission.

It uses a single clock edge to control all of its operations, aiding synthesisand design verification (through the use of static timing analysis andsimilar tools).

It uses a centrally multiplexed bus scheme rather than a bidirectional buswith tri-state drivers.

It supports wider data bus configurations of 64 or 128 bits.


51/61

43. Mention the protocol followed to initiate a bus transfer.

The ASB specifies the protocol which must be followed:

The master, x, issues a request (AREQx) to the central arbiter. When the bus is available, the arbiter issues a grant (AGNTx) to master.

44. List the components of ARMulator.It is made up of four components:

The processor core model, which can emulate any current ARM core

A memory interface which allows the characteristics of the targetmemory system to be modelled.

A coprocessor interface that supports custom coprocessor models.

An operating system interface that allows individual system calls to behandled by the host or emulated on the ARM model.

45. Mention the test signals used by JTAG.The interface works with five dedicated signals which must be provided on

each chip that supports the test standard:

TRST is a test reset input which initializes the test interface.

TCK is the test clock which controls the timing of the test interfaceindependently from any system clocks.

TMS is the test mode select which controls the operation of the test

interface state machine.

TDI is the test data input line which supplies the data to the boundaryscan or instruction registers.

TDO is the test data output line which carries the sampled values fromthe boundary scan chain and propagates data to the next chip in theserial test circuit.

46. Define TAP controller. The operation of the test interface is controlled by the Test Access Port

(TAP) controller. This is a state machine whose state transitions arecontrolled by TMS.

All the states have two exits so the transitions can be controlled by onesignal, TMS.

The two main paths in the state transition diagram control the operationof a data register (DR) and the instruction register (IR).


52/61

47. What are the public instructions supported by compliant devices?

The minimum set of public instructions that all compliant devices mustsupport is:

BYPASS: here the device connects TD Ito TDO though a single clock delay.

EXTEST: here the boundary scan register is connected between TDI andTOO and the pin states are captured and controlled by the register.

IDCODE: here the ID register is connected between TDI and TDO. In theCapture DR state the device ID is copied into the register which is thenshifted out in the Shift DR state.

INTEST: here the boundary scan register is connected between TDI andTDO and the core logic input and output states are captured and

controlled by the register.

48. What is an Embedded-ICE? The Embedded-lCE module consists of two watch-point registers and

control and status registers. The watch-point registers can halt the ARM

core when the address, data and control signals match the valueprogrammed into the watch-point register.

Since the comparison is performed under a mask, either watch-pointregister can be configured to operate as a breakpoint register capable ofhalting the processor when an instruction in either ROM or RAM isexecuted.

The breakpoint and watch-point registers which are accessed asadditional data registers using special JTAG instructions and a tracebuffer which is similarly accessed.

In addition to the breakpoint and watch-point events, it may also bedesirable to halt the processor when a system-level event occurs. Thedebug architecture includes external inputs for this purpose.

The on-chip cell containing these facilities is called the Embedded-lCEmodule.

49. List the types of debugging.There are two basic approaches to debugging are Desktop debugging - watching a system from the outside, using the test

equipment such as logic analyzer.

Embedded debugging - on viewing a system from the inside with toolsthat support single stepping, he setting of breakpoints, and so on.

50. What are the types of ARM7TDMI cycle/memory access?Cycle Use

N Non-sequential memory accessS Sequential memory accessI Internal cycle - bus and memory inactiveC Coprocessor registers transfer memory inactive


53/61

51. Specify the features of ARM7 TDMI.

The ARM7, is a 3-volt compatible rework of the ARM6 32-bit integer core,with:

The Thumb 16-bit compressed instruction set;

On-chip Debug support, enabling the processor to halt in response to adebug request;

An enhanced Multiplier, with higher performance than its predecessorsand yielding a full 64-bit result.

Embedded-lCE hardware to give on-chip breakpoint and watch-point support.

52. How ARM7TDMI is modified for synthesis?The ARM7TDMI-S is a synthesizable version of the ARM7TDMI, delivered as ahigh-level language module which can be synthesized using any suitable celllibrary in the target technology. It is therefore easier to port to a new

process technology than is the hard macro-cell.

The synthesis process supports a number of optional variations on theprocessor core functionality. These include:

omitting the Embedded-lCE cell;

replacing the full 64-bit result multiplier with a smaller and simplermultiplier that supports only the ARM multiply instructions that produce a32-bit result.

53. How Double memory bandwidth is achieved in ARM8? It assumes that the memory connected to processor can deliver one word

in a clock cycle and deliver the next sequential word half a cycle laterconcurrently with starting the next access.

A 64-bit wide memory has the required characteristics, but delaying thearrival of the second word by half a clock cycle allows a 32-bit bus to beused and can save area since routing a 32-bit bus requires less area thanrouting a 64-bit bus.

54. Compare thumb decoding in ARM7& ARM9. The ARM7TDMI implements the Thumb instruction set by 'decompressing'

Thumb instructions into ARM instructions using slack time in the ARM7pipeline.

The ARM9TDMI pipeline is much tighter and does not have sufficient slacktime to allow Thumb instructions to be first translated into ARM

instructions and then decoded; instead it has hardware to decode bothARM and Thumb instructions directly.


54/61

55. Specify the features of on chip debug of ARM9.

The Embedded-lCE functionality in the ARM9TDMI core gives the samesystem-level debug features as that on the ARM7TDMI core with thefollowing additional features:

Hardware single-stepping is supported.

Breakpoints can be set on exceptions in addition to the

address/data/control conditions supported by ARM7TDMI.

56. Define ARM9E-S. The ARM9E-S is a synthesizable version of the ARM9TDMI core. It

implements an extended version of the ARM instruction set comparedwith the 'hard' core.

In addition to the ARM architecture v4T instructions supported by theARM9TDMI, the ARM9E-S supports the full ARM architecture version v5TEincluding the signal processing instruction set extensions.


55/61

UNIT- V

ARM INSTRUCTION SET

1. Define Thumb instruction set.The Thumb instruction set addresses the issue of code density. It may be

viewed as a compressed form of a subset of the ARM instruction set. Thumb

instructions map onto ARM instructions, and the Thumb programmer's modelmaps onto the ARM programmer's model.

Implementations of Thumb use dynamic decompression in an ARMinstruction pipeline and then instructions execute as standard ARMinstructions within the processor.

2. How thumb entry and exits are made?Thumb entry

The normal way they switch to execute Thumb instructions is byexecuting a Branch and Exchange instruction. This instruction sets the Tbit if the bottom bit of the specified register was set, and switches theprogram counter to the address given in the remainder of the register.

Other instructions which change from ARM to Thumb code includeexception returns, either using a special form of data processinginstruction or a special form of load multiple register instruction

Thumb exit

An explicit switch back to an ARM instruction stream can be caused byexecuting a Thumb BX instruction.

An implicit return to an ARM instruction stream takes place whenever anexception is taken, since exception entry is always handled in ARM code.

3. How ARM registers are modified for thumb instructions. R13 is used as a stack pointer. R14 is used as the link register. R15 is the program counter (PC).

4. Mention the uses of thumb branch instructions.Typical uses of branch instructions include:

1. Short conditional branches to control loop exit;2. Medium-range unconditional branches to 'go to' sections of code;3. Long-range subroutine calls.


56/61

5. State the similarities & differences between Thumb & ARM instructions.

Similarities

The load-store architecture with data processing, data transfer andcontrol flow instructions.

Support for 8-bit byte, 16-bit half-word and 32-bit word data types wherehalf-words are aligned on 2-byte boundaries and words are aligned on 4-

byte boundaries.

A 32-bit un-segmented memory.

Differences

Most Thumb instructions are executed unconditionally.All ARM instructions are executed conditionally.

Many Thumb data processing instructions use a 2-address format - thedestination register is the same as one of the source registers. ARM dataprocessing instructions, with the exception of the 64-bit multiplies, use a3-address format.)

Thumb instruction formats are less regular than ARM instruction formats,as a result of the dense encoding.

6. How SWI instruction is encoded in Thumb?This instruction causes the following actions:

The address of the next Thumb instruction is saved in r14_svc.

The CPSR is saved in SPSR_svc.

The processor disables IRQ, clears the Thumb bit and enters supervisormode by modifying the relevant bits in the CPSR.

The PC is forced to address 0x08.

7. Explain about Thumb break point instruction.This instruction causes the processor to take a prefetch abort when thedebug hardware unit is configured appropriately. Breakpoint instructions areused for software debugging purposes; they cause the processor to breakfrom normal instruction execution and enter appropriate debugging

procedures.

8. State the thumb properties. The Thumb code requires 70% of the space of the ARM code. The Thumb code uses 40% more instructions than the ARM code. With 32-bit memory, the ARM code is 40% faster than the Thumb code. With 16-bit memory, the Thumb code is 45% faster than the ARM code.

Thumb code uses 30% less external memory power than ARM code.


57/61

9. Write about Thumb systems. A high-end 32-bit ARM system may use Thumb code for certain non-

critical routines to save power or memory requirements.

A low-end 16-bit system may have a small amount of on-chip 32-bit RAMfor critical routines running ARM code, but use off-chip Thumb code for allnon-critical routines.

10. Mention the data types supported by ARM processors.ARM processors support six data types:

8-bit signed and unsigned bytes.

16-bit signed and unsigned half-words; these are aligned on 2-byteboundaries.

32-bit signed and unsigned words; these are aligned on 4-byte boundaries.

11. Explain the types of memory organization in ARM. little-endian big-endianMost ARM chips remain strictly neutral in the dispute and can be configuredto work with either memory arrangement, though they default to little-endian.

12. List the operating modes of ARM processor.i)

Normal user mode.ii) Software interrupt mode.

iii) Fast interrupt mode.iv) Abort mode.v) System mode.vi) Standard interrupt mode.vii) Undefined trap mode.

13. Define SPSR.Each privileged mode (except system mode) has associated with it a

Saved Program Status Register, or SPSR.This register is used to save thestate of the CPSR (Current Program Status Register) when the privilegedmode is entered in order that the user state can be fully restored when theuser process is resumed.

Often the SPSR may be untouched from the time the privileged mode isentered to the time it is used to restore the CPSR, but if the privileged

software is to be re-entrant (for example, if supervisor code makessupervisor calls to itself) then the SPSR must be copied into a general

register and saved.


58/61

14. What are the types of ARM exceptions?ARM exceptions may be considered in three groups:

Exceptions generated as the direct effect of executing an instruction.- Software interrupts undefined instructions and pre-fetch aborts.

Exceptions generated as a side-effect of an instruction. - Data aborts(a memory fault during a load or store data access) are in this class.

Exceptions generated externally, unrelated to the instruction flow.- Reset, IRQ and FIQ fall into this category.

15. List the exception vector addresses.

16. Write the steps followed in exception entry and exit.Steps followed in exception entry:

It changes to the operating mode corresponding to the particularexception.

It saves the address of the instruction following the exception entryinstruction in r14 of the new mode.

It saves the old value of the CPSR in the SPSR of the new mode.

It disables IRQs by setting bit 7 of the CPSR and, if the exception is a fastinterrupt, disables further fast interrupts by setting bit 6 of the CPSR.

It forces the PC to begin executing at the relevant vector address given

Steps followed in exception exits:

Any modified user registers must be restored from the handler's stack.

The CPSR must be restored from the appropriate SPSR.

The PC must be changed back to the relevant instruction address in the

user instruction stream.


59/61

17. Mention the priority followed in exception handling.

Since multiple exceptions can arise at the same time it is necessary to definea priority order to determine the order in which the exceptions are handled.

On ARM this is:

1. Reset (highest priority);

2. Data abort;

3. FIQ;4. IRQ;5. Pre-fetch abort;6. SWI, undefined instruction (including absent coprocessor).

These are mutually exclusive instruction encodings and therefore cannotoccur simultaneously

18. State the sequence of steps done during a software interrupt arises.In detail, the processor actions are:

1. Save the address of the instruction after the SWI in r14_svc.

2. Save the CPSR in SPSR_svc.

3. Enter supervisor mode and disable IRQs (but not FIQs) by settingCPSR[4:0] to 100112andCPSR[7]tol.

4. Set the PC to (08)H and begin executing the instructions there.

19. Mention the flags used in ARM. The N flag is set if the result is negative, otherwise it is cleared (that is, N

equals bit 31 of the result).

The Z flag is set if the result is zero, otherwise it is cleared. The C flag is set to the carry-out from the ALU when the operation is

arithmetic (ADD, ADC, SUB, SBC, RSB, RSC, CMP, and CMN) or to thecarry-out from the shifter otherwise. If no shift is required, C ispreserved.

The V flag is preserved in non-arithmetic operations. It is set in anarithmetic operation if there is an overflow from bit 30 to bit 31 andcleared if no overflow occurs.

20. State the use of r15 in programming. The PC value is stored in r15 and is updated for each clock cycle. The r15 may be used as a source operand. The value supplied is the

address of the instruction plus eight bytes.

The r15 may also be specified as the destination for the result, in whichcase the instruction is a form of branch. This is exploited as a standardway to return from a subroutine.


60/61

21. Define SWP instruction.Swap instructions combine a load and a store of a word or an unsigned bytein a single instruction. Normally the two transfers are combined into anatomic memory operation that cannot be split by an external memory access(for instance from a DMA controller), and therefore the instruction can be

used as the basis of a semaphore mechanism to give mutually exclusiveaccess to data structures that are shared between multiple processes,

processors, or a processor and a DMA controller. These instructions are little

used outside their role in the construction of semaphores.

22. State the types of ARM architecture variants/versions.The ARM architecture has undergone a number of revisions in the course ofits development. The various architecture versions are described below.

Version 1 These are the first ARM chips supported only26-bitaddressing and had no multiply or coprocessor support.

Version 2 - It was still a 26-bit address machine, but included the 32-bitresult multiply instructions and coprocessor support.

Version 2a - but added the atomic load and store (SWP) instruction andintroduced the use of coprocessor

Version 3 The ARM6 introduced ARM architecture version 3, which had32-bit addressing, separate CPSR and SPSRs, and added the undefinedand abort modes to allow coprocessor emulation and virtual memorysupport in supervisor mode.

Version 3G - ARM architecture version 3G is version 3 withoutbackwards compatibility to version2a.

Version 3M - ARM architecture version 3M introduces the signed andunsigned multiply and multiply-accumulate instructions that generate thefull 64-bit result.

Version 4 - adds the signed and unsigned half-word and signed byteload and store instructions and reserves some of the SWI space for

architecturally defined operations. The system is introduced, and severalunused corners of the instruction space are trapped as undefined

instructions.

Version 4T - The 16-bit Thumb compressed form of the instruction set isintroduced in version4T of the architecture.

Version5T - the ARM architecture has been introduced recently, and atthe time of writing is supported only by ARM10 processors (and these willsoon support v5TE). It is a superset of architecture version 4T, addingthe BLX, CLZ and BRK instructions.

Version 5TE - adds the signal processing instruction set extensions.


61/61

23. What is the state of ARM after a data abort?The state of the ARM after a data abort depends on the particular processorand, with some processors, on the early/late abort configuration:

In all cases the PC is preserved (so on data abort exception entryr14_abt contains the address of the faulting instruction plus eight bytes).

The base register will either be unmodified, or will contain a valuemodified by auto-indexing (it will not be overwritten by a loaded value).

Other load destination registers may have been overwritten, but thecorrect value will be loaded when the instruction is retried.

microcontroller & risc architecture (2 marks - question bank)

Documents