microelectronic manufacturing
DESCRIPTION
WSU ME 310TRANSCRIPT
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ME310
Manufacturing Processes
Rahul Panat
School of Mechanical and Materials Engineering
Washington State University
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HW-1 REVIEW OF SELECT QUESTIONS
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HW-1 REVIEW OF SELECT QUESTIONS
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Manufacturing of Microelectronics
and MEMS Devices
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Ack: Prof. McCloy for some material
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Why study this topic?• Electronic devices have revolutionized our world!
BACKGROUND
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Google Contact Lens Apple Watch Intel-FossilBracelet
Conceptual
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Core Material
(woven glass
composite)
Cu Layers
(Patterned)
Dielectric Film
Solder Resist
PTH
Filling material
Highly Complicated Layered Structure
Patterned Cu Dielectric
Thick Core
Bump(lead free)
Vias connecting Cu layers
Vias
Plated through holes in core Solder resist and bumping
LENGTH SCALES IN ELECTRONIC
DEVICES
Length scales drive specialized manufacturing methods
Flexible Boards with components* (100um~10mm)
*Source: Teardown.com
Google Glass
Processor**
(10s nm ~ 100um)
**Intel public information
Intel’s 32nm Si **
(10s nm ~ 10um)PCB (10um ~ 100um)
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LENGTH SCALE DRIVEN MANUFACTURING
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Intel lithography now at 14um in HVMAnd 11 nm and below in research
Needs cleanrooms!
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• Transistor discovered in Bell labs enabling modern
computing revolution
• Vacuum tubes used in computers – limiting the number of
circuits in the computer; highly bulky
• Solution: Jack Kilby patented first IC design and showed
first prototype; Bob Noyce (Intel founder) patented Al
metallization connect the ICs
• Microelectronic manufacturing as a separate area emerged
from the miniaturization started by Kilby/Noyce
BRIEF HISTORY
Jack Kilby, Texas Instruments, “Miniaturized electronic circuits”, U.S. Patent US3138743 A Robert Noyce, Intel Corporation, “Semiconductor device”, U.S. Patent 2,981,877
Bob Noyce
Jack Kilby
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• Miniaturization of circuits continues per the prediction by Intel’s Moore
(Moore’s Law) – “With unit cost falling as the number of components per
circuit rises, by 1975 economics may dictate squeezing as many as 65 000
components on a single silicon chip.”…………………….well….a chip with
3.1 billion components* was released in 2012 by Intel……..
IC MINIATURIZATION
Major area of manufacturing research in electronics due to the massive (exponential)
pace of miniaturization!
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SILICON
• Why Si
– Cheap
– SiO2, used for isolation and passivation and can be reliably and easily formed to
form the basis for metal oxide semiconductor (MOS) devices
• Doping required for to make Si a semiconductor
– N-type dopant – Phosphorous (group IV)
– P-type dopant – Boron (group III)
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SILICON WAFER
Video Link
SiO2 + C95-98% pure polycrystalline Si
Trichlorisilane ECG
• Making electronic grade silicon
• Crystal growth by Czochralski (CZ) method
High TH2 atm
Heat
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WAFER PROCESSING
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CLEANING
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CLEANING
Wafers in a Chemical Bath
Total Time: >1 hour
Cross-contamination due to close spacing between wafers
● >1 hour process: long chemical
exposure causes undesired loss
of silicon and oxide
● Long cycle time and high work-
in-process
● Large footprint
● 30 year old technology
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PHOTOLITHOGRAPHY
● Masking● Projection
system● Photoresist
● Considerations● Feature size● Wavelength
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TYPICAL RESIST PROCESSES
HMDS: hexamethyldisilzane
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OXIDATION
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OXIDATION
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DIFFUSION AND ION IMPLANTATION
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DIFFUSION AND ION IMPLANTATION
Other types of PVD used in research• Molecular beam epitaxy (MBE)• Pulsed laser deposition (PLD)• Atomic layer deposition (ALD)
Types of CVD• Atmospheric pressure CVD (APCVD)• Low pressure CVD (LPCVD)• Plasma enhanced CVD (PECVD)• Hybrid physical-chemical VD (HPCVD)
DIFFERENCE BETWEEN PVD AND CVD METHODS: chemical decomposition of precursor gas (CVD) versus vaporization of solid source (PVD)
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CVD
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PVD
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PVD: Sputtering
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DEPOSITION
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ETCHING
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ETCHING PROCESSES
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ETCHING PROCESSES
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WET vs PLASMA ETCHING
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CHEMICAL vs PHYSICAL ETCHING
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ETCHING ISSUES
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BACKEND: DIELECTRICS AND
INTERCONNECTS
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PACKAGE TYPES
LeadframeStacked Chip Scale Package
FC-CSPFlip Chip
www.emeraldinsight.com computing-dictionary.thefreedictionary.com
CSP: Chip Scale Package
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FLIP CHIP PACKAGE: MICROPROCESSOR
First Level InterconnectPassives
Substrate (fiber reinforced polymer with metal traces connecting die to second level interconnect)
die
Motherboard (containing chipsets, power supply, Signal I/O connectivity and other peripherals)
die
substrate
substrate
PCB board
solder
solder
Underfill (polymer)
Second Level
Interconnect
Die Bump
Si: ~3ppm/K
Package: ~17ppm/K
Schematic Ack Dr. Hill
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LAYERED COMPOSITE
Core Material
(woven glass
composite)
Cu Layers(Patterned)
Dielectric Film
Solder Resist
PTH Filling material
Highly Complicated Layered Structure Patterned Cu Dielectric Thick Core
Bump(lead free)
Vias connecting Cu layers
Vias Plated through holes in core Solder resist and bumping
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STACKED CSP* PACKAGE: MEMORY
5 die stacked memory package(Molding compound removed – isometric view)
Multiple dies stacked one above the other Chip scale package (Intel makes NAND memory) Thinning of the wafer is required
Stacked Dies
Molding Compound
Gold Wires(~20um Ø)
Substrate
*CSP: Chip Scale Package
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FLIP CHIP ASSEMBLY
Substrate
C4 bumps LSCs
Application of flux
Substrate
Die
Die Placement
Substrate
FLI joint
formation
Capacitors
(land side)
Die
Flux evaporation, reflow
and joint formation
Application of solder paste
Capacitor
Soldered
joint
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STACKED CSP ASSEMBLY
Backgrinding/cutting wafer into individual dies
EPOXY DISPENSE
(or FILM)
EPOXY (or FILM)
DIE BONDING
SUBSTRATE
DIE
GOLD
WIRE
+
Overmolding
Repeat the process for multiple
dies if necessary
Ball attach and reflow
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DFM: Cu-MIGRATION
Per JEDEC standards, all packages must meet certain accelerated test requirements such as high temperature and moisture under biased condition, temperature cycling
After several hours at high Temp and moisture
Polymeric matrix of the substrateor dielectric of the silicon
Copper line
Dendrite
Example of dendrite formation: Cu in acidic solution at 0.6V (Gabrielli et al, J Electrochem
Soc, 154, H393 (2007)
H2O H+ + OH-
Anode: Cu Cu+ + e-
2Cu++ 2OH---> Cu2O + H2O
Movement of Cu+ ion to cathode under electric fieldCathode: Cu+ + e-
Cu2H+ + 2e-
H2
+ -
Cu Migration Video
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SUMMARY
W-CMPCopper Deposition
PVD + ECP
Dielectric
DepositionDielectric
Etch
Copper
CMP
Metal
Deposition
PVD + WCVD
Dielectric
EtchDielectric
Deposition
• 6 Dielectric
Deposition Steps
• 12 Dielectric
Etch Steps
• 6 Ta/Cu PVD Steps
• 6 Cu Plating Steps
• 6 Cu CMP Steps
• 12 Wet Clean Steps
Interconnect
Shallow Trench
Isolation Etch
Shallow Trench
Isolation CMP
Gate Oxide
Growth
Poly Silicon
DepositionPoly Silicon
Gate EtchShallow Trench
Isolation Dielectric
Deposition
Intel’s Microprocessor
Courtesy of Intel Silicon Wafer
Ion Implantation
• 16 Thermal Steps
• 11 Implant Steps
• 5 Etch Steps
• 2 CMP Steps
• 38 Wet Clean Steps
Transistor
Both interconnect and transistor are important