microprocesor 8086

8/10/2019 Microprocesor 8086

1/201

Microprocessor- 8086

MANOJKUMAR S.B Page 1

MICROPROCESSOR

Subject Code : 06EC62 IA Marks : 25No. of Lecture Hrs/Week : 04 Exam Hours : 03

Total no. of Lecture Hrs. : 52 Exam Marks : 100PART - A

UNIT - 1

8086 PROCESSORS: Historical background, The microprocessor-based personal computer system, 8086 CPUArchitecture, Machine language instructions, Instruction execution timing, The 8088 7 Hours

UNIT - 2

INSTRUCTION SET OF 8086: Assembler instruction format, data transfer and arithmetic, branch type, loop,NOP & HALT, flag manipulation, logical and shift and rotate instructions. Illustration of these instructions withexample programs, Directives and operators 7 Hours

UNIT - 3

BYTE AND STRING MANIPULATION: String instructions, REP Prefix, Table translation, Number format

conversions, Procedures, Macros, Programming using keyboard and video display 6 Hours

UNIT - 4

8086 INTERRUPTS: 8086 Interrupts and interrupt responses, Hardware interrupt applications, Software interruptapplications, Interrupt examples 6 Hours

PART - B

UNIT - 5

8086 INTERFACING: Interfacing microprocessor to keyboard (keyboard types, keyboard circuit connections andinterfacing, software keyboard interfacing, keyboard interfacing with hardware), Interfacing to alphanumericdisplays (interfacing LED displays to microcomputer), Interfacing a microcomputer to a stepper motor 6 Hours

UNIT - 6

8086 BASED MULTIPROCESSING SYSTEMS: Coprocessor configurations, The 8087 numeric data processor:

data types, processor architecture, instruction set and examples 6 Hours

UNIT - 7

SYSTEM BUS STRUCTURE: Basic 8086 configurations: minimum mode, maximum mode, Bus Interface:peripheral component interconnect (PCI) bus, the parallel printer interface (LPT), the universal serial bus (USB)

7 Hours

UNIT - 8

80386, 80486 AND PENTIUM PROCESSORS: Introduction to the 80386 microprocessor, Special 80386registers, Introduction to the 80486 microprocessor, Introduction to the Pentium microprocessor. 7 Hours

TEXT BOOKS:

1. Microcomputer systems-The 8086 / 8088 Family Y.C. Liu and G. A. Gibson, 2E PHI -20032. The Intel Microprocessor, Architecture, Programming and Interfacing-Barry B. Brey, 6e, Pearson Education

/ PHI, 2003

REFERENCE BOOKS:

1. Microprocessor and Interfacing- Programming & Hardware, Douglas hall, 2e TMH, 19912. Advanced Microprocessors and Peripherals - A.K. Ray and K.M. Bhurchandi, TMH, 20013. 8088 and 8086 Microprocessors - Programming, Interfacing, Software, Hardware & Applications - Triebeland Avtar Singh,4e, Pearson Education, 2003.


2/201



Unit - I

8086- PROCESSORS

In December 1970, Gilbert Hyatt filed a patent application entitled Single Chip Integrated

Circuit Computer Architecture, the first basic patent on the microprocessor.

The microprocessor was invented in the year 1971 in the Intel labs. The first processor was a 4

bit processor and was called 4004.The following table gives chronologically the microprocessor

revolution.

Microprocess

ors

Year of

Introduct

ion

Word

Length

Memory

Addressi

ng

Pins Clock Remarks

4004 1971 4 bits 1KB 16 750KHz Intels 1stP

8008 1972 8 bits 16KB 18 800KHz Mark-8 usedthis;1st computer for

the home.

8080 1973 8 bits 64KB 40 2 MHz 6000trs, Altair-1st PC

8085 1976 8 bits 64KB 40 3-6 MHz Popular

8086 1978 16 bits 1 MB 40 5-10 MHz IBM PC, Intelbecame one offortune 500companies.

8088 1980 8/16 bits 1MB 40 5-8MHz PC/XT

80186 1982 16 bits 1 MB 68 5-8MHz More a

Microcontroller80286 1982 16 bits 16 MB

real,

4GBv

68 60-

12.5MHz

PC/AT, 15million PCssold in 6 years

80386DX 1985 32 bits 4GB real,

64TBv

132

PGA

20-33MHz 2,75,000transistors

80386SX 1988 16/32 16MB 100 20MHz 32b int16b ext


3/201



bits real,

64TBv

80486DX 1989 32 bits 4 GB real,

64TBv

168

PGA

25-66MHz Flaot pt cop,Command lineto point andclick

Pentium 1993 64 bits 4 GB, 16

KB cache

237

PGA

60-200

MHz

2 intr. At a time,Process realworld data likesound, handwritten andphoto images.

Pentium Pro 1995 64 bits 64Gb,256K/512K L2Cache

387PGA 150MHz Speedy CAD

Pentium II 1997 64 bits 64Gb 242 400MHz Capture, edit &share digitalphotos viaInternet

Pentium IIXeon

1998 64 bits 512k/1M/2M L2cache

528pinsLGA

400MHz Workstationsthriving onbusiness

applicationsPentium IIIXeon

1999 64 bits 16 k L1data + 16k L1 instr;512 kB/1MB/2 MBL2

370PGA

1GHz e-commerceapplications

Pentium 4 2000 64 bits 514,864KB

423PGA

1.3 - 2GHz 1.5 GHz,Professionalquality movies,rendering 3D

graphics.Xeon 2001 64 bits 8 MB iL3cache

3.33 GHz Choice of operating system

Itanium 2001 64 bits 2MB/4MB L3cache

418pinsFCPGA

800 MHz Enabling e-commercesecuritytransactions

Itanium 2 2002 64 bits 1.5 9MB L3cache

611pinsFCPGA

200 MHz Businessapplications


4/201



Centrinomobile

2003 64 bits Mobile specific,increased batterylife.

Pentium 4processorextreme

2003 64 bits 2 MB L2cache

423pinsPGA

3.80 GHz Hyper threadingtechnology,games

Centrino M(mobile)

2004 64 bits 90nm,2MB L2cache400MHzpower-systemoptimizedsystem bus

Apart from Intel, Motorola, Zylog Corporation, Fairchild and National (Hitachi, Japan) are some

of the other microprocessor manufacturers.

Microprocessors are used in all modern appliances, which are Intelligent, meaning that they are

capable of different modes of working. For example an automatic washing machine has different

wash options, one for woolen and the other for nylon etc., Also in a printing Industry right from

type setting to page lay out to color photo scanning and printing and cutting and folding are also

taken care of by microprocessors.

The applications of microprocessors can be sub divided into three categories. The first and most

important one is the computer applications. The second one is the control application (micro

controllers, embedded controllers etc.) and the third is in Communication (DSP processors, Cell

phones etc.).

The basis of working of all the microprocessors is binary arithmetic and Boolean logic. The

number system used is Hexadecimal (base 16) and the character code used is ASCII. Many

assemblers are available to interface the machine code savvy processor to English language like

programs of the users.(CP/M, MASM, TASM etc.).

For Games we have joysticks, electronic guns and touch screens. Nowadays laptop and palmtop

computers are proliferating and in future nano computing, bio computing, molecular and optical

computing also are contemplated.


5/201



Microprocessor Based Personal Computer System

Different Components of Computers Microprocessor 8086, 8088, 80186, 80188, 80286, 80386, 80486, Pentium, Pentium

Pro, Pentium II, Pentium III, Pentium IV

Memory System DRAM, SRAM, Cache, ROM, Flash Memory, EEPROM, SDRAM,

RAMBUS

I/O System Printer, Serial communications, Floppy Disk Drive, Hard Disk Drive,

Mouse, CD-ROM drive, Plotter, Keyboard, Monitor, Scanner, DVD, Pen Drive

Summary of Simple Microcomputer Bus Operation

1. A microcomputer fetches each program instruction in sequence, decodes the instruction,

and executes it.

2. The CPU in a microcomputer fetches instructions or reads data from memory by sending

out an address on the address bus and a Memory Read signal on the control bus. The

memory outputs the addressed instruction or data word to the CPU on the data bus.

3. The CPU writes a data word to memory by sending out an address on the address bus,

sending out the data word on the data bus, and sending a Memory write signal to memory

on the control bus.

4. To read data from a port, the CPU sends out the port address on the address bus and

sends an I/O Read signal to the port device on the control bus. Data from the port comes

into the CPU on the data bus.

5. To write data to a port, the CPU sends out the port address on the address bus, sends out

the data to be written to the port on the data bus, and sends an I/O Write signal to the port

device on the control bus.

ADDRESS BUS

CONTROLBUS

CONTROLBUS

INPUTDEVICE

OUTPUTDEVICE

I/O PORTS

CENTRALPROCESSING

MEMORY(RAM AND

DATA BUS


6/201



8086 Internal Block diagram (Intel Corp.)

The block diagram of 8086 is as shown. This can be subdivided into two parts, namely the Bus

Interface Unit and Execution Unit. The Bus Interface Unit consists of segment registers, adder to

generate 20 bit address and instruction prefetch queue.

Once this address is sent out of BIU, the instruction and data bytes are fetched from memory and

they fill a First In First Out 6 byte queue.

Execution Unit:

The execution unit consists of scratch pad registers such as 16-bit AX, BX, CX and DX and

pointers like SP (Stack Pointer), BP (Base Pointer) and finally index registers such as source

index and destination index registers. The 16-bit scratch pad registers can be split into two 8-bit

registers. For example, AX can be split into AH and AL registers. The segment registers and

their default offsets are given below.

Segment Register Default Offset

CS IP (Instruction Pointer)

DS SI, DI

SS SP, BP

ES DI


7/201



The Arithmetic and Logic Unit adjacent to these registers perform all the operations. The results

of these operations can affect the condition flags.

Different registers and their operations are listed below:

Register Operations

AX Word multiply, Word divide, word I/O

AL Byte Multiply, Byte Divide, Byte I/O, translate, Decimal Arithmetic

AH Byte Multiply, Byte Divide

BX Translate

CX String Operations, Loops

CL Variable Shift and Rotate

DX Word Multiply, word Divide, Indirect I/O

IP

SR

DI

SI

BP

SP

DX

CX

AX

BX

ES

SS

DS

CS

Instruction Pointer

Code Segment Register

Data Segment Register

Stack Segment Register

Extra Segment Register

AH

Stack Pointer Register

AL

BE BL

CE CL

DH DL

Break Pointer Register

Source Index Register

Destination Index Register

Status Register

Code Segment (64Kb)

Data Segment (64Kb)

Stack Segment (64Kb)

Extra Segment (64Kb)

FFFFF16

00000016

8086/8088 MPU MEMORY


8/201



Generation of 20-bit Physical Address:

8086 flag register format

(a) : CARRY FLAG SET BY CARRY OUT OF MSB(b) : PARITY FLAG SET IF RESULT HAS EVEN PARITY(c) : AUXILIARY CARRY FLAG FOR BCD(d) : ZERO FLAG SET IF RESULT = 0(e) : SIGN FLAG = MSB OF RESULT(f) : SINGLE STEP TRAP FLAG(g) : INTERRUPT ENABLE FLAG(h) : STRING DIRECTION FLAG

(i)

(h)

(g)

(e)

d

(a)

U U U U 0F DF IF TF SF ZF U AF U PF U CF

=

LOGICAL ADDRESS

SEGMENT REGISTER 0000

ADDER

20 BIT PHYSICAL MEMORY ADDRESS


9/201



There are three internal buses, namely A bus, B bus and C bus, which interconnect the various

blocks inside 8086.The execution of instruction in 8086 is as follows:

The microprocessor unit (MPU) sends out a 20-bit physical address to the memory and fetches

the first instruction of a program from the memory. Subsequent addresses are sent out and the

queue is filled upto 6 bytes. The instructions are decoded and further data (if necessary) are

fetched from memory. After the execution of the instruction, the results may go back to memory

or to the output peripheral devices as the case may be.

Real mode memory addressing

The segment registers have contents of 16-bits. Hence, 216 = 64Kb of memory can be addressed

by segment registers. Normally, the segment base register contains three zeroes, so that each

segment can start from say E0000 to EFFFF. The segments namely code segment, data segment,

stack segment and extra segment for a particular program can be contiguous, separate or in case

of small programs overlapping even. i.e., for example, code segment is supposed to have 64Kb

and in case of small programs data segment may be within the code segment.

Fig: One way four 64-Kbyte segment might be positioned within the 1-Mbyte address space

of an 8086

5FFFFH

70000H

7FFFFH

FFFFFH

PHYSICALADDRESS

MEMORY

EXTRA SEGMENT BASEES=7000H

HIGHEST ADDRESS

TOP OF EXTRA SEGMENT

STACK SEGMENT BASE

SS = 5000H

TOP OF CODE SEGMENT

TOP OF STACK SEGMENT

CODE SEGMENT BASE

CS=348AH

TOP OF DATA SEGMENT

BOTTOM OF DATA SEGMENT

64K

64K

64K

64K

50000H

4489FH

348A0H

2FFFFH

20000H


10/201



Fig: Addition of IP to CS to produce the physical address of the code byte

(a) Diagram

3 4 8 A 0

4 2 1 43 8 A B 4

(b) Computation

Segment Over Ride Prefix

SOP is used when a particular offset register is not used with its default base segment register,

but with a different base register. This is a byte put before the OPCODE byte.

0 0 1 S R 1 1 0

SR Segment Register

00 ES

01 CS

10 SS

11 DS

348A0H

38AB4H

4489FH

PHYSICALADDRESS MEMORY

CODE BYTE

TOP OF CODE SEGMENT

START OF CODE SEGMENTCS=348AH

IP=4214H

CS

IP +PHYSICAL ADDRESS

HARDWIRED ZERO


11/201



Here SR is the new base register. To use DS as the new register 3EH should be prefix.

Operand Register Default With over ride prefix

IP (Code address) CS Never

SP(Stack address) SS Never

BP(Stack Address) SS BP+DS or ES or CS

SI or DI(not including Strings) DS ES, SS or CS

SI (Implicit source Address for

strings)

DS

DI (Implicit Destination

Address for strings)

ES Never

Examples: MOV AX, DS: [BP], LODS ES: DATA1

S4 S3 Indications

0 0 Alternate data

0 1 Stack

1 0 Code or none

1 1 Data

Bus High Enable / Status

BHE A0 Indications

0 0 Whole word

0 1 Upper byte from or to odd address

1 0 Lower byte from or to even address

1 1 None

Segmentation:

The 8086 microprocessor has 20 bit address pins. These are capable of addressing 220 = 1Mega

Byte memory.

To generate this 20 bit physical address from 2 sixteen bit registers, the following procedure is

adopted.


12/201



The 20 bit address is generated from two 16-bit registers. The first 16-bit register is called the

segment base register. These are code segment registers to hold programs, data segment register

to keep data, stack segment register for stack operations and extra segment register to keep

strings of data. The contents of the segment registers are shifted left four times with zeroes (0s)

filling on the right hand side. This is similar to multiplying four hex numbers by the base 16.

This multiplication process takes place in the adder and thus a 20 bit number is generated. This is

called the base address. To this a 16-bit offset is added to generate the 20-bit physical address.

Segmentation helps in the following way. The program is stored in code segment area. The data

is stored in data segment area. In many cases the program is optimized and kept unaltered for the

specific application. Normally the data is variable. So in order to test the program with a

different set of data, one need not change the program but only have to alter the data. Same is the

case with stack and extra segments also, which are only different type of data storage facilities.

Generally, the program does not know the exact physical address of an instruction. The

assembler, a software which converts the Assembly Language Program (MOV, ADD etc.) into

machine code (3EH, 4CH etc) takes care of address generation and location.

Sr. No 8088 80086

1. Its has only eight data lines.Therefore, it has AD0 AD7and A8A15 signals.

It has sixteen data lines. Therefore it has AD0AD15 signals.

2. As data bus is 8-bit wide, itdoes not have BHE signal.

It has BHE signal to access higher byte.

3. It has 4 byte instruction queue.Due to 8-bit data businstruction fetching is slowand 4 bytes are sufficient for

queue.

It has 6 byte instrucyion queue.

4. Its pin number 34 is SSO. Itacts as S0 in the minimummode. In maximum mode,SSO pin is always high.

Its pin number 34 is BHE/S7. During T1(firstclock cycle) BHE should be used to enable dataon to the most significant byte of the data bus.During T2, T3 and T4 status of this pin is logic 0.In maximum mode, 8087 monitors this pin toidentify the CPU as a 8088 or a 8086, andaccordingly sets its own queue length to 4 or 6bytes.

5. In minimum mode its pin 28 isassigned to signal IO/M

In minimum mode its pin 28 is assigned to signalM/IO


13/201



Addressing Modes

Addressing modes of 8086

When 8086 executes an instruction, it performs the specified function on data. These data arecalled its operands and may be part of the instruction, reside in one of the internal registers of themicroprocessor, stored at an address in memory or held at an I/O port, to access these differenttypes of operands, the 8086 is provided with various addressing modes (Data AddressingModes).

Data Addressing Modes of 8086

The 8086 has 12 addressing modes. The various 8086 addressing modes can be classified intofive groups.

A. Addressing modes for accessing immediate and register data (register and immediatemodes).

B. Addressing modes for accessing data in memory (memory modes)C. Addressing modes for accessing I/O ports (I/O modes)D. Relative addressing modeE. Implied addressing mode

8086 ADDRESSING MODES

A. Immediate addressing mode:In this mode, 8 or 16 bit data can be specified as part of the instruction.

OP Code Immediate Operand

Example 1 : MOV CL, 03 HMoves the 8 bit data 03 H into CL

Example 2 : MOV DX, 0525 HMoves the 16 bit data 0525 H into DX

In the above two examples, the source operand is in immediate mode and the destination operandis in register mode.

A constant such as VALUE can be defined by the assembler EQUATE directive such asVALUE EQU 35HExample : MOV BH, VALUE

Used to load 35 H into BH

B. Register addressing mode :The operand to be accessed is specified as residing in an internal register of 8086. Fig. belowshows internal registers, any one can be used as a source or destination operand, however onlythe data registers can be accessed as either a byte or word.


14/201



RegisterOperand sizes

Byte (Reg 8) Word (Reg 16)

Accumulator AL, AH AxBase BL, BH Bx

Count CL, CH Cx

Data DL, DH Dx

Stack pointer - SP

Base pointer - BP

Source index - SI

Destination index - DI

Code Segment - CS

Data Segment - DS

Stack Segment - SS

Extra Segment - ES

Example 1 : MOV DX (Destination Register) , CX (Source Register)Which moves 16 bit content of CS into DX.

Example 2 : MOV CL, DLMoves 8 bit contents of DL into CL

MOV BX, CH is an illegal instruction.* The register sizes must be the same.

C. Direct addressing mode :The instruction Opcode is followed by an affective address, this effective address is directly usedas the 16 bit offset of the storage location of the operand from the location specified by thecurrent value in the selected segment register.

The default segment is always DS.

The 20 bit physical address of the operand in memory is normally obtained asPA = DS : EABut by using a segment override prefix (SOP) in the instruction, any of the four segmentregisters can be referenced,

PA = CSDS : Direct AddressSSES

The Execution Unit (EU) has direct access to all registers and data for register and immediateoperands. However the EU cannot directly access the memory operands. It must use the BIU, inorder to access memory operands.

In the direct addressing mode, the 16 bit effective address (EA) is taken directly from thedisplacement field of the instruction.


15/201



Example 1 : MOV CX, STARTIf the 16 bit value assigned to the offset START by the programmer using an assembler pseudoinstruction such as DW is 0040 and [DS] = 3050.

Then BIU generates the 20 bit physical address 30540 H.The content of 30540 is moved to CLThe content of 30541 is moved to CH

Example 2 : MOV CH, STARTIf [DS] = 3050 and START = 00408 bit content of memory location 30540 is moved to CH.Example 3 : MOV START, BX

With [DS] = 3050, the value of START is 0040.Physical address : 30540

MOV instruction moves (BL) and (BH) to locations 30540 and 30541 respectively.

Register indirect addressing mode :

The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20 bitphysical address is computed using DS and EA.Example : MOV [DI], BX

register indirectIf [DS] = 5004, [DI] = 0020, [Bx] = 2456 PA=50060.The content of BX(2456) is moved to memory locations 50060 H and 50061 H.

CSPA = DS BX

SS = SIES DIBased addressing mode:

CSPA = DS BX

SS : or + displacementES BP

when memory is accessed PA is computed from BX and DS when the stack is accessed PA iscomputed from BP and SS.

Example : MOV AL, START [BX]orMOV AL, [START + BX]

based modeEA : [START] + [BX]PA : [DS] + [EA]

The 8 bit content of this memory location is moved to AL.


16/201



Indexed addressing mode:CS

PA = DS SISS : or + 8 or 16bit displacementES DI

Example : MOV BH, START [SI]PA : [SART] + [SI] + [DS]

The content of this memory is moved into BH.

Based Indexed addressing mode:

CSPA = DS BX SI

SS : or + or + 8 or 16bit displacementES BP DI

Example : MOV ALPHA [SI] [BX], CLIf [BX] = 0200, ALPHA 08, [SI] = 1000 H and [DS] = 3000

Physical address (PA) = 312088 bit content of CL is moved to 31208 memory address.

String addressing mode:

The string instructions automatically assume SI to point to the first byte or word of the sourceoperand and DI to point to the first byte or word of the destination operand. The contents of SIand DI are automatically incremented (by clearing DF to 0 by CLD instruction) to point to thenext byte or word.Example : MOV S BYTE

If [DF] = 0, [DS] = 2000 H, [SI] = 0500,[ES] = 4000, [DI] = 0300

Source address : 20500, assume it contains 38PA : [DS] + [SI]

Destination address : [ES] + [DI] = 40300, assume it contains 45After executing MOV S BYTE,

[40300] = 38[SI] = 0501 incremented

[DI] = 0301

C. I/O mode (direct) :

Port number is an 8 bit immediate operand.Example : OUT 05 H, AL

Outputs [AL] to 8 bit port 05 H

I/O mode (indirect):

The port number is taken from DX.


17/201



OR

OR

OR

Example 1 : INAL, DXIf [DX] = 5040

8 bit content by port 5040 is moved into AL.Example 2 : IN AX, DXInputs 8 bit content of ports 5040 and 5041 into AL and AH respectively.

D. Relative addressing mode:Example : JNC STARTIf CY=O, then PC is loaded with current PC contents plus 8 bit signed value of START,otherwise the next instruction is executed.

E. Implied addressing mode:

Instruction using this mode have no operands.Example : CLC which clears carry flag to zero.

SINGLE INDEX DOUBLE INDEX

Fig.3.1 : Summary of 8086 Addressing Modes

Encodedin the

instruction

BX

OR

BP

SI

OR

DI

+

+ +

+ +

CS 0000

PHYSICAL ADDRESS

DS 0000

SS 0000

ES 0000

DISPLACEMENTExplicit in the

instruction

Assumed

unlessover

ridden

by prefix

EU

BIU

BX

OR

BP

OR

SI

OR

DI


18/201


MANOJKUMAR S.B Page 18Byte 3 Byte 4

Special functions of general-purpose registers:

AX & DX registers:

In 8 bit multiplication, one of the operands must be in AL. The other operand can be a byte inmemory location or in another 8 bit register. The resulting 16 bit product is stored in AX, withAH storing the MS byte.

In 16 bit multiplication, one of the operands must be in AX. The other operand can be a word inmemory location or in another 16 bit register. The resulting 32 bit product is stored in DX andAX, with DX storing the MS word and AX storing the LS word.

BX register : In instructions where we need to specify in a general purpose register the 16 biteffective address of a memory location, the register BX is used (register indirect).

CX register : In Loop Instructions, CX register will be always used as the implied counter.

In I/O instructions, the 8086 receives into or sends out data from AX or AL depending as a wordor byte operation. In these instructions the port address, if greater than FFH has to be given asthe contents of DX register.

Ex : IN AL, DXDX register will have 16 bit address of the I/P device

Physical Address (PA) generation :

Generally Physical Address (20 Bit) = Segment Base Address (SBA)+ Effective Address (EA)

Code Segment :Physical Address (PA) = CS Base Address

+ Instruction Pointer (IP)Data Segment (DS)PA = DS Base Address + EA can be in BX or SI or DIStack Segment (SS)PA + SS Base Address + EA can be SP or BPExtra Segment (ES)PA = ES Base Address + EA in DI

Instruction Format :The 8086 instruction sizes vary from one to six bytes. The OP code occupies six bytes and itdefines the operation to be carried out by the instruction.Register Direct bit (D) occupies one bit. It defines whether the register operand in byte 2 is thesource or destination operand.D=1 Specifies that the register operand is the destination operand.D=0 indicates that the register is a source operand.Data size bit (W) defines whether the operation to be performed is an 8 bit or 16 bit data

W=0 indicates 8 bit operationW=1 indicates 16 bit operation


19/201



7 2 1 0 7 6 5 4 3 2 1 0

Opcode D W MOD REG R/MLow Disp/

DATAHigh Disp/

DATA

The second byte of the instruction usually identifies whether one of the operands is in memory orwhether both are registers.

This byte contains 3 fields. These are the mode (MOD) field, the register (REG) field and theRegister/Memory (R/M) field.

MOD (2 bits) Interpretation00 Memory mode with no displacement follows except for 16 bit

displacement when R/M=110

01 Memory mode with 8 bit displacement

10 Memory mode with 16 bit displacement

11 Register mode (no displacement)

Register field occupies 3 bits. It defines the register for the first operand which is specified assource or destination by the D bit.

REG W=0 W=1

000 AL AX

001 CL CX

010 DL DX

011 BL BX

100 AH SP

101 CH BP

110 DH SI

111 BH DI

The R/M field occupies 3 bits. The R/M field along with the MOD field defines the secondoperand as shown below.

Byte 1 Byte 2

Register Operand/Register to use EA

Calculation

Register Operand/Extension of opcode

Register mode/Memory mode with

displacement length

Word/byte operation

Direction is to register/from register

Operation code

DIRECTADDRESS LOW

BYTE

DIRECTADDRESS HIGH

BYTE


20/201



MOD 11

R/M W=0 W=1

000 AL AX001 CL CX

010 DL DX

011 BL BX

100 AH SP

101 CH BP

110 DH SI

111 BH DI

Effective Address Calculation

R/M MOD=00 MOD 01 MOD 10

000 (BX) + (SI) (BX)+(SI)+D8 (BX)+(SI)+D16

001 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16

010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16

011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D10

100 (SI) (SI) + D8 (SI) + D16

101 (DI) (DI) + D8 (DI) + D16

110 Direct address (BP) + D8 (BP) + D16

111 (BX) (BX) + D8 (BX) + D16

In the above, encoding of the R/M field depends on how the mode field is set. If MOD=11(register to register mode), this R/M identifies the second register operand.MOD selects memory mode, then R/M indicates how the effective address of the memoryoperand is to be calculated. Bytes 3 through 6 of an instruction are optional fields that normallycontain the displacement value of a memory operand and / or the actual value of an immediateconstant operand.

Example 1 : MOV CH, BLThis instruction transfers 8 bit content of BL

Into CH

The 6 bit Opcode for this instruction is 1000102 D bit indicates whether the register specified by

the REG field of byte 2 is a source or destination operand.D=0 indicates BL is a source operand.W=0 byte operationIn byte 2, since the second operand is a register MOD field is 112.The R/M field = 101 (CH)Register (REG) field = 011 (BL)Hence the machine code for MOV CH, BL is10001000 11 011 101Byte 1 Byte2= 88DD16


21/201



Example 2 : SUB Bx, (DI)This instruction subtracts the 16 bit content of memory location addressed by DI and DS fromBx. The 6 bit Opcode for SUB is 0010102.D=1 so that REG field of byte 2 is the destination operand. W=1 indicates 16 bit operation.MOD = 00REG = 011R/M = 101The machine code is 0010 1011 0001 1101

2 B 1 D2B1D16

Summary of all Addressing Modes

Example 3 :Code for MOV 1234 (BP), DX

Here we have specify DX using REG field, the D bit must be 0, indicating the DX is the sourceregister. The REG field must be 010 to indicate DX register. The W bit must be 1 to indicate itis a word operation. 1234 [BP] is specified using MOD value of 10 and R/M value of 110 and adisplacement of 1234H. The 4 byte code for this instruction would be 89 96 34 12H.

Opcode D W MOD REG R/M LB displacement HB displacement

100010 0 1 10 010 110 34H 12H

Example 4 : Code for MOV DS : 2345 [BP], DX

Here we have to specify DX using REG field. The D bit must be o, indicating that Dx is the

source register. The REG field must be 010 to indicate DX register. The w bit must be 1 toindicate it is a word operation. 2345 [BP] is specified with MOD=10 and R/M = 110 anddisplacement = 2345 H.

Whenever BP is used to generate the Effective Address (EA), the default segment would be SS.In this example, we want the segment register to be DS, we have to provide the segment overrideprefix byte (SOP byte) to start with. The SOP byte is 001 SR 110, where SR value is providedas per table shown below.

MOD / R/M Memory Mode (EA Calculation) Register Mode

00 01 10 W=0 W=1

000 (BX)+(SI) (BX)+(SI)+d8 (BX)+(SI)+d16 AL AX

001 (BX) + (DI) (BX)+(DI)+d8 (BX)+(DI)+d16 CL CX010 (BP)+(SI) (BP)+(SI)+d8 (BP)+(SI)+d16 DL DX

011 (BP)+(DI) (BP)+(DI)+d8 (BP)+(DI)+d16 BL BX

100 (SI) (SI) + d8 (SI) + d16 AH SP

101 (DI) (DI) + d8 (DI) + d16 CH BP

110 d16 (BP) + d8 (BP) + d16 DH SI

111 (BX) (BX) + d8 (BX) + d16 BH DI


22/201



SR Segment register

00 ES

01 CS10 SS

11 DS

To specify DS register, the SOP byte would be 001 11 110 = 3E H. Thus the 5 byte code for thisinstruction would be 3E 89 96 45 23 H.

SOP Opcode D W MOD REG R/M LB disp. HD disp.

3EH 1000 10 0 1 10 010 110 45 23

Suppose we want to code MOV SS : 2345 (BP), DX. This generates only a 4 byte code, withoutSOP byte, as SS is already the default segment register in this case.

Example 5 :Give the instruction template and generate code for the instruction ADD OFABE [BX], [DI], DX(code for ADD instruction is 000000)

ADD OFABE [BX] [DI], DXHere we have to specify DX using REG field. The bit D is 0, indicating that DX is the sourceregister. The REG field must be 010 to indicate DX register. The w must be 1 to indicate it is aword operation. FABE (BX + DI) is specified using MOD value of 10 and R/M value of 001(from the summary table). The 4 byte code for this instruction would be

Opcode D W MOD REG R/M 16 bit disp. =01 91 BE FAH000000 0 1 10 010 001 BEH FAH

Example 6 :

Give the instruction template and generate the code for the instruction MOV AX, [BX](Code for MOV instruction is 100010)AX destination register with D=1 and code for AX is 000 [BX] is specified using 00 Mode andR/M value 111It is a word operation

Opcode D W Mod REG R/M=8B 07H

100010 1 1 00 000 111

Questions :

1. Write a note on segment registers.2. List the rules for segmentation.3. What are the advantages of using segmentation?4. What do you mean by index registers?5. What is the function of SI and DI registers?6. Explain the addressing modes of 8086 with the help of examples.7. What do you mean by segment override prefix?8. Write a short notes on i) Instruction formats ii) Instruction execution timing


23/201



Unit - 2

INSTRUCTION SET OF 8086

The instructions of 8086 are classified into SIX groups. They are:

1. DATA TRANSFER INSTRUCTIONS

2. ARITHMETIC INSTRUCTIONS

3. BIT MANIPULATION INSTRUCTIONS

4. STRING INSTRUCTIONS

5. PROGRAM EXECUTION TRANSFER INSTRUCTIONS

6. PROCESS CONTROL INSTRUCTIONS

1.DATA TRANSFER INSTRUCTIONS

The DATA TRANSFER INSTRUCTIONS are those, which transfers the DATA from any one source to any one

destination. The datas may be of any type. They are again classified into four groups. They are:

GENERAL PURPOSE BYTE ORWORD TRANSFER INSTRUCTIONS

SIMPLE INPUT AND OUTPUTPORT TRANSFER INSTRUCTION

SPECIAL ADDRESSTRANSFER INSTRUCTION

FLAG TRANSFERINSTRUCTIONS

MOVPUSHPOP

XCHGXLAT

INOUT

LEALDSLES

LAHFSAHF

PUSHFPOPF

2.ARITHMETIC INSTRUCTIONS

These instructions are those which are useful to perform Arithmetic calculations, such as addition, subtraction,

multiplication and division. They are again classified into four groups. They are:

ADDITION INSTRUCTIONS SUBTRACTIONINSTRUCTIONS

MULTIPLICATIONINSTRUCTIONS

DIVISION INSTRUCTIONS

ADDADCINC

AAADAA

SUBSBBDECNEGCMPAASDAS

MULIMULAAM

DIVIDIVAADCBWCWD


24/201



3.BIT MANIPULATION INSTRUCTIONS

These instructions are used to perform Bit wise operations.

LOGICAL INSTRUCTIONS SHIFT INSTRUCTIONS ROTATE INSTRUCTIONS

NOTAND

ORXORTEST

SHL / SALSHRSAR

ROLRORRCLRCR

4. STRING INSTRUCTIONS

The string instructions function easily on blocks of memory. They are user friendly instructions, which help for easy

program writing and execution. They can speed up the manipulating code. They are useful in array handling, tables

and records.

STRING INSTRUCTIONS

REPREPE / REPZREPNE / REPNZMOVS / MOVSB / MOVSWCOMPS / COMPSB / COMPSWSCAS / SCASB / SCASWLODS / LODSB / LODSWSTOS / STOSB / STOSW

5.PROGRAM EXECUTION TRANSFER INSTRUCTIONS

These instructions transfer the program control from one address to other address. (Not in a sequence). They are

again classified into four groups. They are:

UNCONDITIONAL TRANSFERINSTRUCTIONS

CONDITIONAL TRANSFERINSTRUCTIONS

ITERATION CONTROLINSTRUCTIONS

INTERRUPTINSTRUCTIONS

CALL

RETJMP

JA / JNBEJAE / JNBJB / JNAEJBE / JNA

JCJE / JZ

JG / JNLEJGE / JNLJL / JNGE

JLE / JNGJNCJNE / JNZ

JNOJNP / JPO

JNSJO

JP / JPEJS

LOOP

LOOPE / LOOPZLOOPNE / LOOPNZ

JCXZ

INT

INTOIRET


25/201



6.PROCESS CONTROL INSTRUCTIONS

These instructions are used to change the process of the Microprocessor. They change the process with the stored

information. They are again classified into Two groups. They are:

FLAG SET / CLEAR INSTRUCTIONS EXTERNAL HARDWARESYNCHRONIZATION INSTRUCTIONS

STCCLCCMCSTDCLDSTICLI

HLTWAIT

ESCLOCKNOP

Addition:

There are two instructions ADD and ADC

Register Addition:

ADD AL,BL AL=AL+BLADD CX,DI CX=CX+DIADD CL,10H CL=CL+10ADD [BX],AL the contents of AL are added with the contents of a memory locationaddressed by BX and the result is stored in the same memory location

Example

ADD AL,BL AL=10H BL=30H the result AL=40HADD AX,[SI+2] the word content of the data segment memory location addressed by sum ofSI+2 is added with AX and the result is stored in AX

Example

AX=1234H SI=2000 SI+2=2002 and let the word stored in memory location 2002 be1122H The result AX=2356HADD BYTE PTR [DI],3 3 is added to the byte contents of the data segment memorylocation addressed by DI

Example

DI=2000 and the contents of that memory location is 11HThe contents of address 2000 will be 14H after the execution of this instructionThe contents of the flag register change after the addition operation. The flags affected areSIGN,CARRY,ZERO, AUX CARRY,PARITY,OVERFLOW


26/201



The INTR,TRAP and other flags not affected.

Immediate Addition

An 8 bit immediate data is added.

Example

MOV AL,10HADD AL,30HThe result AL=40H

Memory to Register addition

Example

MOV AX,0ADD AX,DIADD AX,DI+1Let DI=2000 the contents of this memory location is 22HAfter first add AX will have 22+0=22HThen DI+1=2001 let the contents be 11H

The result will be 33H

Array addition The offset address of the array is moved to the SI or DI register

Example

MOV AL,0MOV SI,OFFSET of ArrayADD AL,[SI]ADD AL,[SI+2]ADD AL,[SI+4]

Array

Offsetaddr

2000 10H

2001 11H

2002 22H

2003 33H

2004 44H

After first add the contents AL will be 0+10=10HAfter the second add instruction AL will be 10+22=32HAfter the third add instruction AL will be 32+44=76H


27/201



Increment addition

INC adds a 1 to a register or a memory location used for memory increments

Example

INC AXThis instruction adds one to the contents ox AX let Ax=1234H the result will be AX=1235HINC BYTE PTR [DI]This instruction adds one to the byte contents of the data segment location addressed by DI

Addition with carry

ADC adds the bit in carry flag to the operand data.

Example

ADC AL,BH AL=AL+BH+CARRYADC CX,AX CX=CX+AX+CARRYADC BX,[BP+2] the word contents of the stack segment memory location addressed byBP+2 is added to BX with carry and the result is stored in BX.

Subtraction

Many forms of subtraction appears to use with any addressing mode 8 16 and 32 bit data

SUB

SBB subtract with borrowRegister Subtraction:

SUB AL,BL AL=AL-BL

SUB CL,10H CL=CL-10The carry flag holds the borrow.

Decrement

A 1 is subtracted from the register or the memory location.

ExampleDEC AXDEC BYTE PTR [DI]DEC CL


28/201



DEC BLSubtracts 1 to from a register or a memory location

CMP

This changes only the flag the destination operand never changesThis instruction is usually followed by conditional jump instructionsand tests the condition against the flags

Multiplication

The multiplication is performed on bytes words or double words and can be a signed integer orunsigned integerMUL: unsigned

IMUL: signedFlags CARRY,OVERFLOW

8 Bit multiplicationExample

MOV BL,05HMOV AL,10HMUL BL

The multiplicand is in ALThe multiplier is in BL (even a memory location can be used)

8 Bit multiplicationExample

IMUL BYTE PTR [BX]AL is multiplied by the byte contents of the data segment memory location addressed by BX thesigned product is placed in AX

For signed multiplication the product is in true binary form if positive and in twos complementform if negativeExampleAL 00000010 BL 10000100AL contains +2 and BL contains -4

IMUL BLThe product is -8The product is in twos complement form stored in AXAX 11111000

Division

DIV,IDIV

The dividend is always a double width dividend that is divided by the operandAn 8 bit division devides a 16 bit number by a 8 bit number


29/201



Errors: Divide by zero,devide overflow

AX register stores the dividend that is divided by contents of any 8 bit register or memorylocation.the Quotient(result) moves to AL and AH has the remainder.For signed division the remainder always assumes sign of dividend and is an integerAX=0010H equivalent to +16BL=FDH equivalent to -3DIV BLAL=05H and AH=-1 11111111HAX=1111111100000101H

AX=0010H equivalent to +16BL=FDH equivalent to -3DIV BLAL=-5 11111011 and AH=1AX=0000000111111011H

BCD Arithmetic:

The microprocessor allows manipulation of BCD and ASCII dataBCD used in Cash registers and ASCII used by many programs

There are two instructionsDAA decimal adjust after addition

DAS decimal adjust after subtractionBoth instructions correct the result. The BCD number is stored as packed form 2 digits/byte andif unpacked form means 1 digit/byte it functions with AL only.DAA decimal adjust after additionThe result is in ALThe Logic of this instruction

If lower nibble>9 or AF=1 add 06After adding 06 if upper nibble>9 or CF=1 add 60DAA instruction follows ADD or ADCExample1

ADD AL,CLDAA

Let AL=53 and CL=29AL=53+29AL=7CAL=7C+06 (as C>9)AL=82

Example 2


30/201



Let AL=73 CL=29AL=9CAL=9C+06 (as C>9)AL=A2AL=A2+60=02 and CF=1

The instruction affects AF,CF,PF and ZFExample3

MOV DX,1234HMOV BX,3099HMOV AL,BLADD AL,DLDAAMOV AL,BHADC AL,DHDAAMOV CH,AL

BL=99H DL=34H99+34=CDAL=CD+6(D>9)AL=D3AL=D3+60(D>9)AL=33 and CF=1

BH=30 DH=12AL=30+12+CFAL=43DAA does not do anythingThe result is placed in CX=4333

DAS instruction follows subtractionThe result is in ALLogic of this instruction

If lower nibble>9 or AF=1 subtract 06After subtracting 06 if upper nibble>9 or CF=1 add 60The instruction affects AF,CF,PF and ZF

Example1SUB AL,BHDASLet AL=75 BH=46

AL=75-46=2F AF=1


31/201



AL=2F-6(F>9)AL=29

Example 2

SUB AL,CHDASAL=38 CH=61AL=38-61=D7 CF=1(borrow)AL=D7-60(D>9)AL=77 CF=1(borrow)

Example 3

MOV DX,1234HMOV BX,3099HMOV AL,BLSUB AL,DLDAS

MOV CL,ALMOV AL,BHSBB AL,DHDASMOV CH,AL

AL=99-34=65DAS will not have affectAL=30-12=1EAL=1E-06(E>9)AL=18The result is 1865 placed in CX

ASCII Arithmetic

Functions with ASCII coded numbersThe numbers range from 30-39H for 0-9AAA

AADAAMAAS use AX as source and destination

AAAExample

add 31H and 39H the result is 6AH it should have been 10 decimal which is 31H and 30HAAA is used to correct the answerConverts resulting contents of AL to unpacked decimal digits


32/201



AAA instruction examines the lower 4 bits of AL for valid BCD numbers and checks AF=0 setsthe 4 high order bits to 0AH cleared before additionIf lower digit of AL is between 0-9 and AF=1 06 is added

The upper 4 digits are cleared and incremented by 1If the lower value of the lower nibble is greater than 9 then increment AL by 06 AH by 1AF and CF setThe higher 4 bits of AL are cleared to 0AH modifiedTo get the exact sum add 3030H to AX

AAS

Correct result in AL after subtracting two unpacked ASCII operandsThe result is in unpacked decimal formatIf the lower 4 bits of AL are>9 or if AF=1 then AL=AL-6 and AH=AH-1 CF and AF setotherwise CF and AF set to 0 no correction

result the upper nibble of AL is 00 and the lower nibble may be any number from 0-9

AAMFollows multiplication instruction after multiplying two unpacked BCD numbersConverts the product available in AL into unpacked BCDLower byte of result is in AL and upper in AH

Examplelet the product is 5D in ALD>9 so add 6 =13H

LSD of 13H is lower unpacked byteIncrement AH, AH=5+1=6 upper unpacked byteAfter execution AH=06 and AL=03

MOV AL,5MOV CL,5MUL CLAAM

Accomplishes conversion by dividing AX by 10

Benefit of AAM converts from binary to unpacked BCDuse of AAM for conversionXOR DX,DXMOV CX,100DIV CX

AAMADD AX,3030HXCHG AX,DX

AAMADD AX,3030H


33/201



AAD

Appears before divisionrequires AX to contain two digit unpacked BCD number(not ASCII) before executingAfter adjusting AX with AAD it is divided by an unpacked BCD number to generate a singledigit result in AL with remainder in AHExample.MODEL.CODE.STARTUPMOV AL,48HMOV AH,0AAMADD AX,3030H

MOV DL,AHMOV AH,2PUSH AXINT 21HPOP AXMOV DL,ALINT 21H

.EXITEND

Logic instructions

ANDORExclusive ORNOTTEST

The above instructions perform bitwise operation and the src and destination could be register ormemory location. Their function is same as logic opeartions

JUMP Group of Instructions

Introduction:

In almost any meaningful program, we need to alter the sequential flow of execution.

Examples:

Instruction at reset CS:IP: At rest, 8086 begins execution at the address FFFF:0000H

(absolute address of FFFF0H). There are only 16 bytes from this location to the end of

the memory space (FFFFH)! It is unlikely that any meaningful program can be written

within this space. Thus the instruction at this reset location is usually a long jump


34/201



instruction that transfers control to some suitable lower address based on the available

memory.

A Sorting Program: A comparison-based sorting program would need to swap or not

swap two elements based on the outcome of the comparison of the two elements. This

would mean that we need an instruction to conditionally jump to some other location in

the program.

Any number of such examples can be given to illustrate the need for instructions that

alter the linear flow of control, either unconditionally or conditionally.

Unconditional and Conditional Jump Instructions allow such a control over the

execution flow.

Unconditional Jump:

No testing of any flags is involved in deciding whether a jump is to be executed or not.

Control transfer occurs always.

This is illustrated in the following figure:

Unconditional Jump: ExampleBefore:

CS=FFFF; IP=0000

After:

CS=F000; IP=8000

FFFF0 EA00

8000F0

F8000

UnconditionallyJump here

B800

01

TargetLocation

The instructions used for such unconditional jumps are discussed in detail later.

Conditional Jump:

Values of one or more flags are used in deciding whether a jump is to be executed or not.

Thus, a jump may or may not occur depending on the values of such flag bits


35/201



This idea is illustrated in the following figure:

Conditional JUMP: Example

CMP AX,BX

JE LAB1

MOV BX,1

LAB1: MOV BX,0

Test the Z flag

Control is transferred here only

if Z = 1. A conditional Jump.

Test fails i.e Z=0No jump;

Execution continues with the next

sequential instruction.

Target location

The instructions used for such conditional jumps are discussed in detail later.

Unconditional Jump Instructions:

Unconditionally transfer control to an instruction located else where.

3 different instructions are available for such unconditional jumps.

All have similar behavior; but differ in where the target instruction is allowed to be andconsequently, the instruction lengths also differ. And that is the main advantage.

The 3 forms are:

Short Jump: Target location must be within -128 to +127 bytes from the address

following the Jump instruction, i.e current IP. In this case, there is no change in the

CS value. Only IP is changed

Near Jump: Target location must be within -32768 to +32767 bytes from the

address following the Jump instruction, i.e current IP. In this case also, there is no

change in the CS value. Only IP is changed

Far Jump: Target location can be any where in the memory space. In this case, CS

as well as IP is changed.

Intra-Segment Jump Instructions:

Both Short Jump and Near Jump are called intra-segment jumps also because in both

the cases, there is no change in the CS value and only IP is changed. In other words, the

jump is to a location that is within the same code segment.


36/201



For these jumps, the target IP value is not specified as absolute value. Instead,

displacement (relative distance) from the current IP is specified.

Thus both are relative jumps. (Called Relative Program Memory Addressing in earlier

sessions)

Jump can be forward (to a higher address) or backwards (to a lower address).

So, displacement must be a signed number (can be positive or negative).

Short and Near Jumps differ in the way the displacement is specified.

Short Jump Instruction:

Specifies one byte displacement. It is sign-extended to 16 bits and added to current IP to

get new IP.

Displacement can be -128 to +127

This instruction occupies 2 bytes; the first byte specifies the opcode and the second byte

specifies the relative displacement as a signed 8-bit quantity. The format is shown below:

A short jump instruction with positive relative displacement is illustrated in the following

figure:

Short Jump Instruction

10000

10001EB

1A

CS = 1000 H ; IP = 0002 H (Address

following the JMP instruction)Displacement = 1A H = 0001 1010

Sign Extend = 001A H

New IP = 0002 + 001A = 001C H

Branch to 1000:001C

(+ve displacement; Forward Jump)10002

1001C Jmp Target

Opcode Displacement

EB 8-Bit Signed Value


37/201



A similar situation but with a negative relative displacement is illustrated in the following

figure:

Short Jump Instruction

10003

10004

EB

F2

CS = 1000 H ; IP = 0012 H (Addressfollowing the JMP instruction)

Displacement = F2 H = 1111 0010

Sign Extend = FFF2 HNew IP = 0012 + FFF2 = 0004 H

(ignoring the carry out)

Branch to 1000:0004

(-ve displacement; Backward Jump)

10005

10011

10012

10010

Jmp Target

In a typical Assembly Language Program, we use labels for branch targets and the

Assembler will automatically compute the displacement.

We can force Short Jump to be assembled using the SHORT directive.

Anyway, most Assemblers choose the short form if possible (that is, if the displacement

is in the range of -128 to +127)

A program illustrating the Short Jump instruction is shown below:

XOR BX, BX

ST1: MOV AX, 1

ADD AX, BX

JMP SHORT NXT5 ; assume that the forward displacement


38/201



Example: JMP $ + 2 jumps over the next 2 memory locations following the JMP

instruction. Thus if the above instruction starts at 1000:0010, the after the jump, control is

transferred to the instruction at 1000: 0014

Near Jump Instruction:

This is quite similar to Short Jump except that the displacement is specified as 16 Bit

signed integer rather than as 8-bit integer.

Target range is thus -32768 to +32767.

Target can be any where in the current code segment

Instruction is 3 Byte long. The first byte specifies the opcode and the next two bytes

specify the displacement. The format is shown in the following figure:

A near jump instruction with positive relative displacement is illustrated in the following

figure:

Near Jump Instruction

10000

10001E9

1A

CS = 1000 H ; IP = 0003 H (Address

following the JMP instruction)

Displacement = 201A H

New IP = 0003 + 201A = 201D H

Branch to 1000:201D

(+ve displacement; Forward Jump)10002

1201D Jmp Target

20

10003

A similar situation with a negative displacement is shown in the following figure:

Opcode Displacement

E9 Low Byte High Byte


39/201



Near Jump Instruction

10004

10005

E9

F2

CS = 1000 H ; IP = 0013 H (Address


Displacement = FFF2 H

New IP = 0013 + FFF2 = 0005 H

(ignoring the carry out)

Branch to 1000:0005

(-ve displacement; Backward Jump)10006

10011

10012

10010

Jmp Target

FF

An Assembly Language Program illustrating Near Jump instruction is shown below:

XOR BX, BX

ST1: MOV AX, 1

ADD AX, BX

JMP NXT5

; Some instructions

NXT5: MOV BX, AX

The above program is quite similar to Short Jump Program listed earlier except that the

displacement to NXT5 is assumed to be greater than 127 and hence the instruction JMP NXT5

is assembled as Near Jump.

Inter-Segment Jump Instruction:

FAR Jump is the only inter-segment jump instruction. It is called inter-segment because

the target location can be to any other code segment! Thus it is possible that change

occurs in the IP value as well as in the CS value.

Target is directly specified as new CS:IP.

Thus far jump can be to any where in the memory.


40/201



This instruction is 5 Byte long. The first byte specifies the opcode, the next 2 bytes

specify the new IP value and the last 2 bytes specify the new CS value. The format is

shown in the following figure:

An example illustrating the far jump is shown in the following figure:

Inter-Segment Jump Instruction

10003

10004

00

00

Before Far Jump:

CS = 2000 H ; IP = 0015 H (Address


After the Far Jump:

New CS:IP = 1000:0004 H

Branch to 10004 H10005

20013

20014

20012

Jmp Target

10

EA

0420011

20010

In the ALP, we can use a label with FAR PTRdirective.

Or, we can use a label that is defined as FAR LABEL.

(A label can be FAR only if it is external to the current code segment. So, it is preceded

by EXTRN directive.)

In such cases, the Linker will fill the CS and IP values at the link time.

An ALP showing the far jump is shown below:

EALow

Byte

Low

Byte

Low

Byte

Low

Byte

IP CSO code


41/201



EXTRN L1:FAR

ST1: MOV AX, 1

JMP FAR PTR ST1

JMP L1

Jump with Register Operands:

A 16-Bit register may be used as the operand for the jump instruction. (Indirect Jump)

Contents of the register are transferred directly into IP (no concept of relative

displacement).

This option is available for Near Jump only.

Example: Assume BX = 0080H

After the execution ofJMP BX instruction, the control is transferred to the address

0080H in the current code segment.

Indirect Jump Using Index:

Uses [] form of addressing to directly access a table of jump addresses.

FAR PTR directive indicates a far jump ( jump table is assumed to contain double words

giving CS, IP values)

Otherwise a near jump is indicated. ( jump table is assumed to contain words giving IP

values)

This form is some times called Double Indirect Jump.

Example: JMP TABLE [SI]

Fetch the word, using indexed addressing, at the offset ofTABLE [SI] from the current

code segment and copy that value into IP. (Near Jump)

Example: JMP FAR PTR [SI]

Fetch the double word, using indexed addressing, at the offset of[SI] from the current

code segment and copy the values into IP and CS.


42/201



Conditional Jump

Conditional jumps are always short jumps (relative displacement is -128 to +127).

Based on the values of one or more flags, jump to target address may occur or execution

may continue with the next sequential instruction.

Usually preceded by instructions like CMP, SUB, TEST, AND etc which affect the

flags.

Example:

CMP AX, BX

JZ LAB1

MOV AX, BX

LAB1:MOV CX, AX

In the above program, equality of the operands is tested based on the Z flag.

Conditional jumps following general relative magnitude comparison are more

complicated. Consider the comparison ofFEH with 1AH. Is FEH > 1AH ?

The answer depends on how we interpret the numbers!

Interpreted as Unsigned integers, 0FE H = 254 in decimal and 1A H = 170 in decimal.

Thus 0FE H > 1A H is true.

Interpreted as Signed integers using 2s Complement system, 0FE H = -2 in Decimal

and 1A H = 170 Decimal. Thus 0FE H > 1A H is false!

Thus, we have one set of conditional jump instructions that are to be used if the numbers

are to be interpreted as Unsigned Integers and another set of conditional jump

instructions that are to be used if the numbers are to be interpreted as Signed Integers.

After comparison ofUnsigned integers:

Mnemonic Condition Operation

JA Z=0 and C=0 Jump if above

JAE C=0 Jump if above or equal

JB C=1 Jump if below

JBE Z=1 or C=1 Jump if below or equal


43/201



After comparison ofSigned integers:


JG Z=0 and S=O Jump if greater than

JGE S=O Jump if greater or equal

JL S< >O Jump if less than

JLE Z=1 or S< >O Jump if less or equal

(Both S and O Flags are required to test the condition when comparing signed numbers!)

After comparison ofSigned or Unsigned integers:


JE or JZ Z=1 Jump if equal or Jump if Zero

JNE or JNZ Z=0 Jump if not equal or Jump if not Zero

Alternative, less often used mnemonics also exist.

JA same as JNBE JG same as JNLE

JAE same as JNB JGE same as JNL

JB same as JNAE JL same as JNGE

JBE same as JNA JLE same as JNG

Other Conditional Jump Instructions:


JC C=1 Jump if carry set

JNC C=0 Jump if no carry

JO O=1 Jump if overflow

JNO O=0 Jump if no overflow

JS S=1 Jump if sign is set

JNS S=0 Jump if no sign

Some more Conditional Jump Instructions:


JP or JPE P=1 Jump if parity set or Jump if parity is even


44/201



JNP or JPO P=0 Jump if no parity or Jump if parity is odd

JCXZ CX = 0 Jump if CX = 0

(Note that the last instruction, JCXZ is some what different from the rest in the sense that it

tests the contents of CX register rather than flags. This instruction, generally used in loops, is

illustrated in later sessions. Programs illustrating other conditional jump instructions are also

discussed in later sessions.)

LOOP Instruction:

Program loops are quite common. Most of the counting loops have a typical structure that

is shown below:

MOV CX, 10H ; Initialize the count that determines the number of

; times the loop is to be executed.

Start1:Instructions constituting the loop body

DEC CX ; Decrement counter

JNZ Start1 ; Repeat if not over

If the pair of instructions that test whether the loop body is to be executed again or not,

that is the instructions, DEC CX and JNZ Start1, could be combined in to one

instruction, we would get more elegant and clearer program.

The LOOP instruction does so combine the above pair of instructions.

Thus the single instruction:

LOOP LAB1

is equivalent in effect to the two instructions:

DEC CX

JNZ LAB1

Conditional LOOP Instructions:

These instructions are similar to LOOP instruction except that equality (Z flag) is also

tested. This allows a loop to be controlled by a count as well as a comparison test (like in

the case of String instructions).

There are two such instructions.

LOOPE (Loop While Equal) orLOOPZ

Exit the loop if the condition is not equal or if CX decrements to 0.


45/201



LOOPNE (Loop While Not Equal) or LOOPNZ

Exit the loop if the condition is equal or if CX decrements to 0.

ESC Instruction

This instruction is related to 8087 Numeric Data Coprocessor. Details of 8087 are

discussed in later sessions. Briefly, 8087 provides support for floating point operations

and works as a coprocessor to 8086. It

Shares Pin bus with 8086.

Implements floating point arithmetic

and Has its own instruction set

The program has instructions for 8086 as well as 8087. How does 8087 know the

instruction is for itself? The solution to this problem is the ESC instruction.

ESC indicates that it is 8087 instruction. Opcode has 11011 as the higher-order 5 bits.

Thus ESC is never used by itself.

Generated by Assembler automatically when 8087 mnemonic is used! Consequently,

ESC is never coded directly by the programmer.

WAIT Instruction

Monitors the TEST/ pin of 8086.

At the time of executing this instruction, if

TEST/ pin is LOW , there is no effect; execution simply continues with the next

instruction. However, if

TEST/ is HIGH , then 8086 waits in an idle state until TEST/ returns to LOW.

TEST/ is sampled during leading edge of CLK in each clock cycle during waiting.

This instruction is generally used in conjunction with 8087.

8086 and 8087 can execute in parallel (concurrently)

WAIT instruction allows synchronization between the concurrently executing 8086 and

8087.

When 8086 needs the result from 8087, it executes the WAIT instruction.

TEST/ pin of 8086 is connected to the BUSY pin of 8087.


46/201



When 8087 is busy executing its instruction, it sets its BUSY pin = HIGH. Thus TEST/

of 8086 will also be HIGH. This forces 8086 to wait for the completion of 8087

activity.

When 8087 is not executing its instruction, its BUSY pin = LOW and thus the TEST/ of

8086 will also be LOW. This allows 8086 to continue its execution.

In this manner, synchronization between 8086 and 8087 is achieved.

More on this topic in the session on 8087.

NOP Instruction

As the name implies, it is a no operation instruction!

Takes a short time to execute; otherwise no effect.

Used in early days to provide for manual code patches. Some NOP instructions would be

written every 100 bytes or so. When code was to be patched, the space occupied by the

NOP instructions was used. However, this is irrelevant in modern times because the

program development usually is based on Assemblers nad manual coding is no more

common.

Another use for this instruction is that it could be used for producing short time delays if

delay accuracy is not of concern.

HLT Instruction

As the name implies, it halts the program; the processor enters the HALT state.

An interrupt or a hardware reset will force the 8086 out of the HALT state.

May be used when the program has to wait for an interrupt to occur; but rarely used so in

practice.

In the early days, this instruction was used in the trainer kits as the last instruction of a

user program. It is no more used in this fashion. In fact, presently it is rarely used for any

other purpose either!


47/201



LOCK Prefix

LOCK can be prefix of an instruction.

When such an instruction is executed, the LOCK/ pin of 8086 is activated (forced LOW).

Now, another bus master can not gain control of the bus until the end of the bus lock.

Thus the Lock prefixed instruction executes as an indivisible instruction even if it has

several memory cycles. (Without the LOCK prefix, the bus could be taken over by

another bus master after a memory cycle, even if the current instruction is not

completed!)

This feature is useful for implementing indivisible read modify-write kind of

operations that are necessary in multi-processor systems.

Example: LOCK: XCHG AL, SEM1

The instruction is executed without the possibility of another bus master intervening.

Instruction shown above can be used in implementing semaphores in a multi-

processor system.

Shift instructions

They manipulate binary numbersUsed to control I/O Devices. Shift operation moves the number either to left or right within

memory location or a register. There are four instructions.There are two types of shift (1)

arithmetic and (2) logical. The shift left operation is equivalent to multiply operation and shiftright is divide operation. The data is shifted to left or right only by one position.

Shift left operation

Logical left: The contents of the register or memory location are shifted left by one position theMSB bit moves to Carry flag bit and a zero is added to the LSB positionExample

SHL AX,1

AX=0000 1111 0000 1111 and Carry=1

After the execution of the instruction

AX=0001 1110 0001 1110 and Carry =0Example

MOV CL,3SHL DX,CL

The contents of the DX register are shifted left by three postions

Arithmetical Left: It is same as logical left shift.


48/201



Logical right: The contents of the register or memory location are shifted right by one positionthe LSB bit moves to Carry flag bit and a zero is added to the MSB position

ExampleSHR AX,1AX=0000 1111 0000 1111 and Carry=0

ResultAX=0000 0111 1000 0111 and carry=1

Arithmetic right: The contents of the register or memory location are shifted right by oneposition the LSB bit moves to Carry flag bit and the sign bit is copied through the MSB position

Example

SAL AX,1

AX=1000 0000 0000 1111 and carry=0Result

AX=1100 0000 0000 0111 and carry=1

Example

SAR SI,3

SI= 1010 1100 1010 0101 C=0After first shift SI= 1101 0110 0101 0010 C=1

second shift SI=1110 1011 0010 1001 C=0third shift SI= 1111 0101 1001 0100 C=1

All condition flags are affected

Rotation instructions

There are four rotate instructions.

Rotate left: The contents of the memory location or the register are rotated left by the no ofpositions indicated in the instruction through the carry or without the carry.

ROL BL,4Let BL=0001 0110 C=0After first rotate C= 0 BL= 0010 1100After second rotate C=0 BL= 0101 1000After third rotate C=0 BL= 1011 0000After fourth rotate C=1 BL= 0110 0000


49/201



Rotate right

The contents of the memory location or the register are rotated right by the no of positionsindicated in the instruction through the carry or without the carry.

Assembly Language programming

Assembler: is a program that accepts an assembly language program as input and converts itinto an object module and prepares for loading the program into memory for execution.

Loader (linker) further converts the object module prepared by the assembler into executableform, by linking it with other object modules and library modules.

The final executable map of the assembly language program is prepared by the loader at thetime of loading into the primary memory for actual execution.

The assembler prepares the relocation and linkages information (subroutine, ISR) for loader. The operating system that actually has the control of the memory, which is to be allotted to

the program for execution, passes the memory address at which the program is to be loadedfor execution and the map of the available memory to the loader.

Based on this information and the information generated by the assembler, the loadergenerates an executable map of the program and further physically loads it into the memoryand transfers control to for execution.

Thus the basic task of an assembler is to generate the object module and prepare the loadingand linking information.

Procedure for assembling a program Assembling a program proceeds statement by statement sequentially. The first phase of assembling is to analyze the program to be converted. This phase is called

Pass1 defines and records the symbols, pseudo operands and directives. It also analyses thesegments used by the program types and labels and their memory requirements.

The second phase looks for the addresses and data assigned to the labels. It also finds outcodes of the instructions from the instruction machine, code database and the program data.

It processes the pseudo operands and directives. It is the task of the assembler designer to select the suitable strings for using them as

directives, pseudo operands or reserved words and decides syntax.

Directives

Also called as pseudo operations that control the assembly process. They indicate how an operand or section of a program to be processed by the assembler. They generate and store information in the memory.


50/201



Assembler Memory models

Each model defines the way that a program is stored in the memory system. Tiny: data fits into one segment written in .COM format Small: has two segments data and memory. There are several other models too.

Directive for string data in a memory segment

DB define byte DW define word DD define double word

DQ define 10 bytesExample

Data1 DB 10H,11H,12HData2 DW 1234H

SEGMENT: statement to indicate the start of the program and its symbolic name. Example

Name SEGMENTVariable_name DB .Variable_name DW .

Name ENDS

Data SEGMENTData1 DB .Data2 DW .

Data ENDS

Code SEGMENTSTART: MOV AX,BX

Code ENDS

Similarly the stack segment is also declared.

For small models.DATAENDSThe ENDS directive indicates the end of the segment.


51/201



Memory is reserved for use in the future by using a ? as an operand for DB DW or DDdirective. The assembler sets aside a location and does not initialize it to any specific value(usually stores a zero). The DUP (duplicate) directive creates an array and stores a zero.

ExampleData1 DB 5 DUP(?)This reserves 5 bytes of memory for a array data1 and initializes each

location with 05H

ALIGN: memory array is stored in word boundaries. Example

ALIGN 2 means storing from an even address

Address 0 XX

Address 1 YY

Address 2 XX

The data XX is aligned to the even address. ASSUME, EQU, ORG ASSUME tells the assembler what names have been chosen for Code, Data Extra and Stack

segments. Informs the assembler that the register CS is to be initialized with the addressallotted by the loader to the label CODE and DS is similarly initialized with the address oflabel DATA.

ExampleASSUME CS: Name of code segmentASSUME DS: Name of the data segment

ASSUME CS: Code1, DS: Data1

EQU: Equates a numeric, ASCII(American Standard Code for Information Interchange) orlabel to another label.

ExampleData SEGMENT

Num1 EQU 50HNum2 EQU 66H

Data ENDS

Numeric value 50H and 66H are assigned to Num1 and Num2

ORG: Changes the starting offset address of the data in the data segment Example

ORG 100H100 data1 DB 10Hit can be used for code too.

PROC & ENDP: indicate the start and end of the procedure. They require a label to indicatethe name of the procedure.

NEAR: the procedure resides in the same code segment. (Local)


52/201



FAR: resides at any location in the memory. Example

Add PROC NEAR ADD AX,BXMOV CX,AXRET

Add ENDP

PROC directive stores the contents of the register in the stack. EXTRN, PUBLIC informs the assembler that the names of procedures and labels declared

after this directive have been already defined in some other assembly language modules. Example

If you want to call a Factorial procedure of Module1 from Module2 itmust be declared as PUBLIC in Module1.

ExampleA sample for full segment definition

Data SEGMENTNum1 DB 10HNum2 DB 20HNum3 EQU 30H

Data ENDS

ASSUME CS:Code,DS:DataCode SEGMENT

START: MOV AX,DataMOV DS,AXMOV AX,Num1MOV CX,Num2ADD AX,CX

Code ENDS Example

A sample for small model

. MODEL SMALL

.DataNum1 DB 10HNum2 DB 20HNum3 EQU 30H

.CodeHERE:MOV AX,@Data

MOV DS,AXMOV AX,Num1MOV CX,Num2ADD AX,CX


53/201



UNIT - 3

BYTE AND STRING MANIPULATION

String instructions

REP it is a prefix used with instructionREPE/REPZREPNE/REPNZThese are used with CMPS and SCAS instructionsThese instructions are used in the program as prefix.

CMPSCompare string byte or string word

Only Flags affectedZero flag set if strings match otherwise resetDS:SI and ES:DI are used to point to the two strings

SCASScans the string of bytes or words for an operand byte or word specified in register AL or AXWhen match found the ZF=1 otherwise it is resetLODSLoad string byte or string wordLoads the AL/AX register by the contents of a string pointed by DS:SI No flag affectedSTOS

Stores contents of AL/AX register to a location in a string pointed by ES:DINo flag affected

Strings and String Handling Instructions :

The 8086 microprocessor is equipped with special instructions to handle string operations. Bystring we mean a series of data words or bytes that reside in consecutive memory locations. Thestring instructions of the 8086 permit a programmer to implement operations such as to movedata from one block of memory to a block elsewhere in memory. A second type of operationthat is easily performed is to scan a string and data elements stored in memory looking for aspecific value. Other examples are to compare the elements and two strings together in order todetermine whether they are the same or different.

Move String : MOV SB, MOV SW:An element of the string specified by the source index (SI) register with respect to the currentdata segment (DS) register is moved to the location specified by the destination index (DI)register with respect to the current extra segment (ES) register.

The move can be performed on a byte (MOV SB) or a word (MOV SW) of data. After the moveis complete, the contents of both SI & DI are automatically incremented or decremented by 1 fora byte move and by 2 for a word move. Address pointers SI and DI increment or decrementdepends on how the direction flag DF is set.


54/201



Example : Block move program using the move string instructionMOV AX, DATA SEG ADDRMOV DS, AXMOV ES, AXMOV SI, BLK 1 ADDRMOV DI, BLK 2 ADDRMOV CK, NCDF ; DF=0

NEXT : MOV SBLOOP NEXTHLT

Load and store strings : (LOD SB/LOD SW and STO SB/STO SW)LOD SB: Loads a byte from a string in memory into AL. The address in SI is used relative toDS to determine the address of the memory location of the string element.

(AL) [(DS) + (SI)](SI) (SI) + 1

LOD SW : The word string element at the physical address derived from DS and SI is to beloaded into AX. SI is automatically incremented by 2.

(AX) [(DS) + (SI)](SI) (SI) + 2

STO SB : Stores a byte from AL into a string location in memory. This time the contents of ESand DI are used to form the address of the storage location in memory

[(ES) + (DI)] (AL)(DI) (DI) + 1STO SW : [(ES) + (DI)] (AX)

(DI) (DI) + 2

Mnemonic Meaning Format Operation Flags affected

MOV SBMoveStringByte

MOVSB

((ES)+(DI))((DS)+(SI))(SI)(SI) 1(DI) 1

None

MOV SW

Move

StringWord

MOVSW

((ES)+(DI))((DS)+(SI))((ES)+(DI)+1)(DS)+(SI)+1)(SI) (SI) 2(DI) (DI) 2

None

LOD SB /LOD SW

LoadString

LODSB/

LODSW

(AL) or (AX)((DS)+(SI))(SI)(SI) 1 or 2

None

STOSB/STOSW

StoreString

STOSB/STOSW

((ES)+(DI))(AL) or (AX)(DI) (DI) 71 or 2

None


55/201



Example : Clearing a block of memory with a STOSB operation.MOV AX, 0MOV DS, AXMOV ES, AXMOV DI, A000MOV CX, OFCDF

AGAIN : STO SBLOOP NE AGAIN

NEXT :

Clear A000 to A00F to 0016

Repeat String : REP

The basic string operations must be repeated to process arrays of data. This is done by insertinga repeat prefix before the instruction that is to be repeated.

Prefix REP causes the basic string operation to be repeated until the contents of register CXbecome equal to zero. Each time the instruction is executed, it causes CX to be tested for zero, ifCX is found to be nonzero it is decremented by 1 and the basic string operation is repeated.

Example : Clearing a block of memory by repeating STOSBMOV AX, 0MOV ES, AXMOV DI, A000MOV CX, OFCDFREP STOSBNEXT:

The prefixes REPE and REPZ stand for same function. They are meant for use with the CMPSand SCAS instructions. With REPE/REPZ the basic compare or scan operation can be repeatedas long as both the contents of CX are not equal to zero and zero flag is 1.REPNE and REPNZ works similarly to REPE/REPZ except that now the operation is repeated as

long as CX0 and ZF=0. Comparison or scanning is to be performed as long as the stringelements are unequal (ZF=0) and the end of the string is not yet found (CX0).

Prefix Used with Meaning

REPMOVSSTOS

Repeat while not end of

string CX0

REPE/ REPZCMPSSCAS

CX0 & ZF=1

REPNE/REPNZCMPSSCAS

CX0 & ZF=0


56/201



Example : CLD ; DF =0MOV AX, DATA SEGMENT ADDRMOV DS, AXMOV AX, EXTRA SEGMENT ADDRMOV ES, AXMOV CX, 20MOV SI, OFFSET MASTERMOV DI, OFFSET COPYREP MOVSB

Moves a block of 32 consecutive bytes from the block of memory locations starting at offsetaddress MASTER with respect to the current data segment (DS) to a block of locations startingat offset address copy with respect to the current extra segment (ES).

Auto Indexing for String Instructions :

SI & DI addresses are either automatically incremented or decremented based on the setting ofthe direction flag DF.When CLD (Clear Direction Flag) is executed DF=0 permits auto increment by 1.When STD (Set Direction Flag) is executed DF=1 permits auto decrement by 1.

Mnemonic Meaning Format Operation Flags affected

CLD Clear DF CLD (DF) 0 DFSTD Set DF STD (DF) 1 DF

1. LDS Instruction:LDS register, memory (Loads register and DS with words from memory)This instruction copies a word from two memory locations into the register specified in theinstruction. It then copies a word from the next two memory locations into the DS register. LDSis useful for pointing SI and DS at the start of the string before using one of the stringinstructions. LDS affects no flags.Example 1 :LDS BX [1234]

Copy contents of memory at displacement 1234 in DS to BL. Contents of 1235H to BH. Copycontents at displacement of 1236H and 1237H is DS to DS register.

Example 2 : LDS, SI String Pointer

(SI) [String Pointer](DS) [String Pointer +2]

DS, SI now points at start and desired string

2. LEA Instruction :Load Effective Address (LEA register, source)

This instruction determines the offset of the variable or memory location named as the sourceand puts this offset in the indicated 16 bit register.LEA will not affect the flags.Examples :


57/201



LEA BX, PRICES ;Load BX with offset and PRICES in DSLEA BP, SS : STACK TOP ;Load BP with offset of stack-top in SSLEA CX, [BX] [DI] ;Loads CX with EA : (BX) + (DI)

3. LES instruction :LES register, memory

Example 1: LES BX, [789A H]

(BX) [789A] in DS(ES) [789C] in DS

Example 2 : LES DI, [BX]

(DI) [BX] in DS(ES) [BX+2] in DS

Modular Programming

Concepts:

Modular Programming is essential for conquering complexity inherent in the

development of large, industry-strength software systems.

The basic idea is the classical Divide & Conquer approach. Program is composed from

several smaller modules. Modules could be developed by separate teams concurrently.

The modules are only assembled producing .OBJ modules (Object modules). Each

module is produced from a separate Assembly Language program. The .OBJ modules so produced are combined using a LINK program.

The ML command of MASM typically used for smaller programs actually consists of the

two distinct steps of assembling to produce the object file and then Linking the object

module to produce the .EXE file.

Here, the two steps are separated.



58/201



Concepts - 2ASM File #1

ASM File #2

ASM File #n

Assembler

Assembler

Assembler

.OBJ file

.OBJ file

.OBJ file

Linker .EXE

A further concept that is extremely useful is that of a Library of Object Modules. Frequently

used procedures could be assembled in to object modules and these object modules are placed in

a Library file that is linked into the application. Note that only the required object modules are

pulled from the Library to be linked in to the final application. The concept of a Library is

explored in detail later.


Concepts - 3

ASM File

ASM File

Library of Assembled Modules

(.OBJ files)

Assembler

Assembler

.OBJ file

.OBJ file

Linker .EXE

Assembler Features Required to Support Modular Programming:

To appreciate the features required to support Modular Programming, consider the following

development scenario:


59/201



In Module A , we defined

BUF1 DB 10 DUP (?)

In Module B , we wish to access BUF1, say as in

MOV DX, OFFSET BUF1

BUF1 is not defined in Module B. Thus, when assembling Module B, we will get the

assembly error of Undefined Symbol. Note that the symbol is actually defined in

Module A. But, the two modules are assembled independently!

Problem: How to make the BUF1, defined in Module A, accessible to Module B?

Solution:

Declare BUF1 as public in Module A

(Interpretation: Defined in this module, may be used in other modules.)

Declare BUF1 as external in Module B

(Interpretation: Used in t

microprocesor 8086

Documents