microprocessor 8086 8087 nitin ahire
TRANSCRIPT
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8086 Microprocessor
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Comparison 0f 8085 and 8086
Parameter 8085 8086
Size It is an 8 bit processor It is 16 bit processor
Address bus Address bus is 16 bits Address bus is 20 bits
Memory It can access upto 216
=65,536 bytes ( 64KB)It can access upto 220
=1,048,576 bytes(1MB)
Instruction Queue It does not have an instruction queue
It has 6 byte instructionqueue
Pipelining It does not supportpipelining
It support pipeliningarchitecture
I/Os It Can address 28 =256 I/O locations
It can address 216
=65,536 I/O locations
Multiprocessing support
It does not have multiprocessing support
It supports multiprocessing. It has compatibility with further processors like 80386
Coprocessor interface It does not have co processor interface
Co processor like 8087 can be interface with 8086
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Parameter 8085 8086
Arithmetic Support It only support integer and decimal arithmetic
It support integer, decimal and ASC II arithmetic.
Multiplication and Division
It does not have instruction that computesThe multiplication and division operation.
It supports instructions that compute the multiplication and division operation
Clock speed It operate on freq 3 MHz It operate on freq= 5 to 10 MHZ
Memory segmentation
The memory spaces are not segmented
The memory space is segmented
Interrupts 8085 provides 8 software vectored interrupts and 5 hardware interrupts
8086 has 256 software vectored interrupts and 2 hardware interrupts
Comparison 0f 8085 and 8086
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MicroprocessorMicroprocessorMicroprocessorMicroprocessor
Program controlled semiconductor device (IC)which fetches (from memory), decodes andexecutes instructions.
It is used as CPU (Central Processing Unit) incomputers.
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MicroprocessorMicroprocessorMicroprocessorMicroprocessor
First GenerationBetween 1971 β 1973
PMOS technology, non compatible with TTL4 bit processors β 16 pins
8 and 16 bit processors β 40 pinsDue to limitations of pins, signals are
multiplexed
Second GenerationDuring 1973NMOS technology β Faster speed, Higher density, Compatible with TTL4 / 8/ 16 bit processors β 40 pinsAbility to address large memory spaces and I/O portsGreater number of levels of subroutine nestingBetter interrupt handling capabilities
Intel 8085 (8 bit processor)
Third GenerationDuring 1978
HMOS technology β Faster speed, Higher packing density
16 bit processors β 40/ 48/ 64 pinsEasier to program
Dynamically relatable programsProcessor has multiply/ divide arithmetic
hardwareMore powerful interrupt handling
capabilitiesFlexible I/O port addressing
Intel 8086 (16 bit processor)
Fourth GenerationDuring 1980sLow power version of HMOS technology (HCMOS)32 bit processorsPhysical memory space 224 bytes = 16 MbVirtual memory space 240 bytes = 1 TbFloating point hardwareSupports increased number of addressing modes
Intel 80386
Fifth Generation Pentium
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Functional blocksMicroprocessorMicroprocessorMicroprocessorMicroprocessor
Flag Register
Timing and control unit
Register array or internal memory
Instruction decoding unit
PC/ IP
ALU
Control Bus Address Bus
Data Bus
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Computational Unit;performs arithmetic andlogic operations
Various conditions of the results are stored as
status bits called flags in flag register
Internal storage of data
Generates theaddress of theinstructions to befetched from thememory and sendthrough addressbus to thememory
Decodes instructions; sendsinformation to the timing andcontrol unit
Generates control signals forinternal and externaloperations of themicroprocessor
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Overview 8086 Microprocessor
First 16- bit processor released byINTEL in the year 1978
Originally HMOS, now manufacturedusing HMOS III technique
Approximately 29, 000 transistors, 40pin DIP, 5V supply
Does not have internal clock; externalasymmetric clock source with 33%duty cycle
20-bit address to access memory ββββ canaddress up to 220 = 1 megabytes ofmemory space.
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Features
οΏ½ It is a 16-bit microprocessor.
οΏ½ 8086 has a 20 bit address bus can access up to 220
memory locations (1 MB).
οΏ½ It can support up to 64K I/O ports.
οΏ½ It provides 14, 16 -bit registers.
οΏ½ Word size is 16 bits.
οΏ½ It has multiplexed address and data bus AD0- AD15 and A16 β A19.
οΏ½ It requires single phase clock with 33% duty cycle to provide internal timing.
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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οΏ½ 8086 is designed to operate in two modes, Minimum and Maximum.
οΏ½ It can pre fetches up to 6 instruction bytes from memory and queues them in order to speed up instruction execution.
οΏ½ It requires +5V power supply.
οΏ½ A 40 pin dual in line package.
οΏ½ Address ranges from 00000H to FFFFFH
οΏ½ Memory is byte addressable - Every byte has a separate address.
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Features
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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8086 and 8088 comparison
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8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
8086 8088
Similar EU and Instruction set ; dissimilar BIU
16-bit Data bus lines obtained by demultiplexing AD0 β AD15
8-bit Data bus lines obtained by demultiplexing AD0 β AD7
20-bit address bus 8-bit address bus
Two banks of memory each of 512 kb
Single memory bank
6-bit instruction queue 4-bit instruction queue
Clock speeds: 5 / 8 / 10 MHz 5 / 8 MHz
No such signal required, since the data width is only 1-byte
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Pins and signalsPins and signalsPins and signalsPins and signals
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Pins and Signals8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
Low order address bus; these aremultiplexed with data.
When AD lines are used to transmitmemory address the symbol A is usedinstead of AD, for example A0-A15.
When data are transmitted over AD linesthe symbol D is used in place of AD, forexample D0-D7, D8-D15 or D0-D15.
A16/S3, A17/S4, A18/S5, A19/S6
High order address bus. These aremultiplexed with status signals
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Pins and Signals8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Common signals
BHE (Active Low)/S7 (Output)
Bus High Enable/Status
It is used to enable data onto the mostsignificant half of data bus, D8-D15. 8-bitdevice connected to upper half of thedata bus use BHE (Active Low) signal. Itis multiplexed with status signal S7.
MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode theprocessor is to operate in.
RD (Read) (Active Low)
The signal is used for read operation. It is an output signal. It is active when low.
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Pins and Signals8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Common signals
READY
This is the acknowledgement from theslow device or memory that they havecompleted the data transfer.
The signal made available by the devicesis synchronized by the 8284A clockgenerator to provide ready input to the8086.
The signal is active high.
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Pins and Signals8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Common signals
RESET (Input)
Causes the processor to immediatelyterminate its present activity.
The signal must be active HIGH for atleast four clock cycles.
CLK
The clock input provides the basic timingfor processor operation and bus controlactivity. Its an asymmetric square wavewith 33% duty cycle.
INTR Interrupt Request
This is a triggered input. This is sampledduring the last clock cycles of eachinstruction to determine the availabilityof the request. If any interrupt request ispending, the processor enters theinterrupt acknowledge cycle.
This signal is active high and internallysynchronized.
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Pins and Signals8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Min/ Max Pins
The 8086 microprocessor can work in twomodes of operations : Minimum mode andMaximum mode.
In the minimum mode of operation themicroprocessor do not associate with anyco-processors and can not be used formultiprocessor systems.
In the maximum mode the 8086 can workin multi-processor or co-processorconfiguration.
Minimum or maximum mode operationsare decided by the pin MN/ MX(Active low).
When this pin is high 8086 operates inminimum mode otherwise it operates inMaximum mode.
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Pins and Signals
(Data Transmit/ Receive) Output signal from the processor to control the direction of data flow through the data transceivers
(Data Enable) Output signal from the processor used as out put enable for the transceivers
ALE (Address Latch Enable) Used to demultiplex the address and data lines using external latches
Used to differentiate memory access and I/O access. For memory reference instructions, it is high. For IN and OUT instructions, it is low.
Write control signal; asserted low Whenever processor writes data to memory or I/O port
(Interrupt Acknowledge) When the interrupt request is accepted by the processor, the output is low on this line.
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Minimum mode signals
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Pins and Signals
HOLD Input signal to the processor form the bus masters as a request to grant the control of the bus.
Usually used by the DMA controller to get the control of the bus.
HLDA (Hold Acknowledge) Acknowledge signal by the processor to the bus master requesting the control of the bus through HOLD.
The acknowledge is asserted high, when the processor accepts HOLD.
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Minimum mode signals
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Pins and Signals
Status signals; used by the 8086 bus controller to generate bus timing and control signals. These are decoded as shown.
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Maximum mode signals
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Pins and Signals
(Queue Status) The processor provides the statusof queue in these lines.
The queue status can be used by external device totrack the internal status of the queue in 8086.
The output on QS0 and QS1 can be interpreted asshown in the table.
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Maximum mode signals
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Pins and Signals
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Maximum mode signals
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8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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8086 Architecture
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Architecture
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Execution Unit (EU)
EU executes instructions that have already been fetched by the BIU.
BIU and EU functions separately.
Bus Interface Unit (BIU)
BIU fetches instructions, reads data from memory and I/O ports, writes
data to memory and I/ O ports.
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Architecture
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Bus Interface Unit (BIU)
Dedicated Adder to generate 20 bit address
Four 16-bit segment registers
Code Segment (CS)Data Segment (DS)Stack Segment (SS)Extra Segment (ES)
Segment Registers >>
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Architecture
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Bus Interface Unit (BIU)
Segment Registers
8086βs 1-megabytememory is dividedinto segments of upto 64K bytes each.
Programs obtain accessto code and data in thesegments by changingthe segment registercontent to point to thedesired segments.
The 8086 can directlyaddress four segments(256 K bytes within the 1M byte of memory) at aparticular time.
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Architecture8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Bus Interface Unit (BIU)
Segment Registers
Code Segment Register
16-bit
CS contains the base or start of the current code segment; IP contains the distance or offset from this address to the next instruction byte to be fetched.
BIU computes the 20-bit physical address by logically shifting the contents of CS 4-bits to the left and then adding the 16-bit contents of IP.
That is, all instructions of a program are relative to the contents of the CS register multiplied by 16 and then offset is added provided by the IP.
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Architecture
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Physical Address (20 Bits)
Adder
Segment Register (CS)(16 bits) 0 0 0 0
Offset Value (IP) (16 bits)
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor Bus Interface Unit (BIU)
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Architecture
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Bus Interface Unit (BIU)
Segment Registers
Data Segment Register
16-bit
Points to the current data segment; operands for most instructions are fetched from this segment.
The 16-bit contents of the Source Index (SI) or Destination Index (DI) or a 16-bit displacement are used as offset for computing the 20-bit physical address.
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Architecture
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Bus Interface Unit (BIU)
Segment Registers
Stack Segment Register
16-bit
Points to the current stack.
The 20-bit physical stack address is calculated from the Stack Segment (SS) and the Stack Pointer (SP) for stack instructions such as PUSH and POP.
In based addressing mode, the 20-bit physical stack address is calculated from the Stack segment (SS) and the Base Pointer (BP).
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Architecture
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Bus Interface Unit (BIU)
Segment Registers
Extra Segment Register
16-bit
Points to the extra segment in which data (in excess of 64K pointed to by the DS) is stored.
String instructions use the ES and DI to determine the 20-bit physical address for the destination.
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Architecture
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Bus Interface Unit (BIU)
Segment Registers
Instruction Pointer
16-bit
Always points to the next instruction to be executed withinthe currently executing code segment.
So, this register contains the 16-bit offset address pointingto the next instruction code within the 64Kb of the codesegment area.
Its content is automatically incremented as the executionof the next instruction takes place.
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Segment Register
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Code Segment
3
4
Data Segment
Extra Segment
7
8
9
10
11
12
13
14
15
Stack Segment
Memory
00000H
FFFFFH
1MB
Address
Range
Sta
rti
ng
A
dd
resses o
f S
eg
men
ts
1000 0H
4000 0H
5000 0H
F000 0H
CS
DS
ES
SS
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Data Segment
Code Segment
Extra Segment
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12
13
14
15
Stack Segment
Memory
00000H
FFFFFH
1MB
Address
Range348A H
4214 H
38AB4 H
CS = Base value
IP= offset value
Physical Address
Start of Code Segment
348A0H
Code Byte MOV AL, BL38AB4H
IP = 4214H
+
0
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β’ The following examples shows the CS:IP scheme of
address formation:
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Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR
four binary digits left
3 4 B A 0 ( C S ) +8 A B 4 ( I P )
3 D 6 5 4 (next address)
34BA 8AB4
MOV AL,BL
CS IP
34BA0
3D654
44B9F
Code segment
8AB4 (offset)
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β’ Example For Address Calculation (segment: offset)
β’ If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data?
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Required Address
Offset
Segment Address
0000000000101001
0000
00010000 0000 0010 1001
0001000000000000
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Segment and Address register combinationSegment and Address register combination
β’ CS:IP
β’ SS:SP SS:BP
β’ DS:BX DS:SI
β’ DS:DI (for other than string operations)
β’ ES:DI (for string operations)
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Summary of Registers & Pipeline of 8086 Β΅PSummary of Registers & Pipeline of 8086 Β΅P
AH AL
BH BL
CH CL
DH DL
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SP
BP
SI
DI
FLAGS
DECODER
ALU
AX
BX
CX
DX
EU
Timing control
SP
BP
Default Assignment
BIU
IP
CS DS ES SS
PIPELINE(or)
QUEUE
CODE OUT
CODE
IN
IP BX
DI
SI
DI
Fetch & store code bytes in PIPELINE
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β’ Segment Override Prefix :
β’ e.g. MOV CS:[BX],AL
β’ 1000 0 H CS
+ 0020 0 H BX_____________________
1020 0 H Physical AddressIt allows the programmer to deviate from by default segments.
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Architecture
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Bus Interface Unit (BIU)
A group of First-In-First-Out (FIFO) in which up to6 bytes of instructioncode are pre fetchedfrom the memory aheadof time.
This is done in order tospeed up the executionby overlappinginstruction fetch withexecution.
This mechanism is knownas pipelining.
Instruction queue
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Architecture
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Some of the 16 bit registers can be used as two 8 bit registers as :
AX can be used as AH and ALBX can be used as BH and BLCX can be used as CH and CLDX can be used as DH and DL
Execution Unit (EU)
EU decodes and executes instructions.
A decoder in the EU control system
translates instructions.
16-bit ALU forperforming arithmeticand logic operation
Four general purpose registers(AX, BX, CX, DX);
Pointer registers (Stack Pointer, Base Pointer);
and
Index registers (Source Index, Destination Index) each of 16-bits
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Architecture8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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EURegisters
Accumulator Register (AX)
Consists of two 8-bit registers AL and AH, which can becombined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word,and AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting /outputting 16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX orAL.
Execution Unit (EU)
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Architecture
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EURegisters
Base Register (BX)
Consists of two 8-bit registers BL and BH, which can becombined together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word,and BH contains the high-order byte.
This is the general purpose register whose contents canbe used for addressing the 8086 memory.
All memory references utilizing this register content foraddressing use DS as the default segment register.
Execution Unit (EU)
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Architecture
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EURegisters
Counter Register (CX)
Consists of two 8-bit registers CL and CH, which can becombined together and used as a 16-bit register CX.
When combined, CL register contains the low order byte ofthe word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use thecontents of CX as a counter.
Execution Unit (EU)
Example:
The instruction LOOP START automatically decrementsCX by 1 without affecting flags and will check if [CX] =0.
If it is zero, 8086 executes the next instruction;otherwise the 8086 branches to the label START.
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Architecture
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EURegisters
Execution Unit (EU)
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Architecture
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EURegisters
Stack Pointer (SP) and Base Pointer (BP)
SP and BP are used to access data in the stack segment.
SP is used as an offset from the current SS duringexecution of instructions that involve the stack segment inthe external memory.
SP contents are automatically updated (incremented/decremented) due to execution of a POP or PUSHinstruction.
BP contains an offset address in the current SS, which isused by instructions utilizing the based addressing mode.
Execution Unit (EU)
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Architecture
50
EURegisters
Source Index (SI) and Destination Index (DI)
Used in indexed addressing.
Instructions that process data strings use the SI and DIregisters together with DS and ES respectively in order todistinguish between the source and destination addresses.
Execution Unit (EU)
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Architecture
51
EURegisters
Source Index (SI) and Destination Index (DI)
Used in indexed addressing.
Instructions that process data strings use the SI and DIregisters together with DS and ES respectively in order todistinguish between the source and destination addresses.
Execution Unit (EU)8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Architecture
52
Flag Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Carry Flag
This flag is set, when there isa carry out of MSB in case ofaddition or a borrow in caseof subtraction.
Parity Flag
This flag is set to 1, if the lowerbyte of the result contains evennumber of 1βs ; for odd numberof 1βs set to zero.
Auxiliary Carry Flag
This is set, if there is a carry from thelowest nibble, i.e, bit three duringaddition, or borrow for the lowestnibble, i.e, bit three, duringsubtraction.
Zero Flag
This flag is set, if the result ofthe computation or comparisonperformed by an instruction iszero
Sign Flag
This flag is set, when the result of any computation
is negative
Tarp FlagIf this flag is set, the processorenters the single step executionmode by generating internalinterrupts after the execution ofeach instruction
Interrupt Flag
Causes the 8086 to recognize external maskable interrupts;
clearing IF disables these interrupts.
Direction FlagThis is used by string manipulation instructions. If this flag bitis β0β, the string is processed beginning from the lowestaddress to the highest address, i.e., auto incrementing mode.Otherwise, the string is processed from the highest addresstowards the lowest address, i.e., auto decrementing mode.
Over flow FlagThis flag is set, if an overflow occurs, i.e, if the result of a signed
operation is large enough to accommodate in a destination register. The result is of more than 7-bits in size in case of 8-bit signed operation and more than 15-bits in size in case of 16-bit
sign operations, then the overflow will be set.
Execution Unit (EU)8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Architecture
Sl.No. Type Register width Name of register
1 General purpose register 16 bit AX, BX, CX, DX
8 bit AL, AH, BL, BH, CL, CH, DL, DH
2 Pointer register 16 bit SP, BP
3 Index register 16 bit SI, DI
4 Instruction Pointer 16 bit IP
5 Segment register 16 bit CS, DS, SS, ES
6 Flag (PSW) 16 bit Flag register
8086 registers categorized
into 4 groups
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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54
Architecture
Register Name of the Register Special Function
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations
BX Base register Used to hold base value in base addressing mode to access memory data
CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP instructions
DX Data Register Used to hold data for multiplication and division operations
SP Stack Pointer Used to hold the offset address of top stack memory
BP Base Pointer Used to hold the base value in base addressing using SS register to access data from stack memory
SI Source Index Used to hold index value of source operand (data) for string instructions
DI Data Index Used to hold the index value of destination operand (data) for string operations
Registers and Special Functions8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Introduction
55
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
ProgramA set of instructions written to solve
a problem.
InstructionDirections which a microprocessor
follows to execute a task or part of a task.
Computer language
High Level Low Level
Machine Language Assembly Language
οΏ½οΏ½οΏ½οΏ½Binary bits οΏ½ English AlphabetsοΏ½ βMnemonicsβοΏ½ Assembler
Mnemonics ββββ Machine
Language
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Assembly Language Syntax
β’ Program consists of statement per line.β’ Each statement is an instruction or assembler directive
β’ Statement syntaxβ Name operation operand(s) comment
β’ Name fieldβ Used for instruction labels, procedure names, and variable names.
β Assembler translates names into memory addresses
β Names are 1-31 characters including letters, numbers and special characters ? . @ _ $ %
β Names may not begin with a digit β Case insensitive
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Assembly Language Syntax β Cont.
β’ Examples of legal namesβ COUNTER1
β @character
β SUM_OF_DIGITS
β $1000
β Done?
β .TEST
β .data
β’ Examples of illegal namesβ 2abc
β A45.28
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Assembly Language Syntax β Cont.
β’ Name operation operand(s) comment
β’ Operation fieldβ instruction
β’ Symbolic operation code (opcode)β’ Symbolic opcodes translated into machine language
opcodeβ’ Describes operationβs function; e.g. MOV, ADD, SUB, INC.
β Assembler directiveβ’ Contains pseudo-operation code (pseudo-op)β’ Not translated into machine codeβ’ Tell the assembler to do something.
β’ Operand fieldβ Specifies data to be acted onβ Zero, one, or two operands
β’ NOPβ’ INC AXβ’ ADD AX, 2
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Assembly Language Syntax β Cont.
β’ Name operation operand(s)comment
β’ Comment fieldβ A semicolon marks the beginning of a comment
β A semicolon in beginning of a line makes it all a comment line
β Good programming practice dictates comment on every line
β’ Examplesβ MOV CX, 0 ; move 0 to CX
β’ Do not say something obvious
β MOV CX, 0 ; CX counts terms, initially 0β’ Put instruction in context of program
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Data Representation
β’ Numbersβ 11011 decimal
β 11011B binary
β 64223 decimal
β -21843D decimal
β 1,234 illegal, contains a no digit character
β 1B4DH hexadecimal number
β 1B4D illegal hex number, does not end with βHβ
β FFFFH illegal hex number, does not begin with digit
β 0FFFFH hexadecimal number
β’ Signed numbers represented using 2βs complement.
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Data Representation - Cont.
β’ Charactersβ must be enclosed in single or double quotes
β e.g. βHelloβ, βHelloβ, βAβ, βBβ
β encoded by ASCII code
β’ βAβ has ASCII code 41H
β’ βaβ has ASCII code 61H
β’ β0β has ASCII code 30H
β’ Line feed has ASCII code 0AH
β’ Back Space has ASCII code 08H
β’ Horizontal tab has ASCII code 09H
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Data Representation - Cont.
β’ The value of the content of registers or memory is dependent on the programmer.
β’ Let AL=FFHβ represents the unsigned number 255
β represents the signed number -1 (in 2βs complement)
β’ Let AH=30Hβ represents the decimal number 48
β represents the character ββ
β’ Let BL=80Hβ represents the unsigned number +128
β represents the signed number -128
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Variable Declaration
β’ Each variable has a type and assigned a
memory address.
β’ Data-defining pseudo-opsβ DB define byte
β DW define word
β DD define double word (two consecutive words)
β DQ define quad word (four consecutive words)
β DT define ten bytes (five consecutive words)
β’ Each pseudo-op can be used to define one
or more data items of given type.
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Byte Variables
β’ Assembler directive format defining a byte variable
β name DB initial value
β a question mark (β?β) place in initial value leaves variable uninitialized
β’ I DB 4 define variable I with initial value 4
β’ J DB ? Define variable J with uninitialized value
β’ Name DB βCourseβ allocate 6 bytes for Name
β’ K DB 5, 3, -1 allocates 3 bytes
05
03
FF
K
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Named Constants
β’ EQU pseudo-op used to assign a name to constant.
β’ Makes assembly language easier to understand.
β’ No memory allocated for EQU names.
β’ LF EQU 0AH
β MOV DL, 0AH
β MOV DL, LF
β’ NAME EQU βType your nameβ
β MSG DB βType your nameβ
β MSG DB NAME
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DUP Operator
β’ Used to define arrays whose elements share common initial value.
β’ It has the form: repeat count DUP (value)
β’ Numbers DB 100 DUP(0)
β Allocates an array of 100 bytes, each initialized to 0.
β’ Names DW 200 DUP(?)
β Allocates an array of 200 uninitialized words.
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General Rules
β’ Both operands have to be of the same size.β MOV AX, BL illegal
β MOV AL, BL legal
β MOV AH, BL legal
β’ Both operands cannot be memory operands simultaneously.β MOV i, j illegal
β MOV AL, i legal
β’ First operand cannot be an immediate value.β ADD 2, AX illegal
β ADD AX, 2 legal
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Memory Segmentation - Cont.
β’ Data Segmentβ contains variable definitions
β declared by .DATA
β’ Stack segmentβ used to store the stack
β declared by .STACK size
β default stack size is 1Kbyte.
β’ Code segmentβ contains programβs instructions
β declared by .CODE
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Memory Models
β’ SMALLβ code in one segment & data in one segment
β’ MEDIUMβ code in more than one segment & data in one segment
β’ COMPACTβ code in one segment & data in more than one segment
β’ LARGEβ code in more than one segment & data in more than one segment & no array larger than 64K bytes
β’ HUGEβ code in more than one segment & data in more than one segment & arrays may be larger than 64K bytes
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Program Structure: An Example
TITLE PRGM1.MODEL SMALL.ORG 100H.DATA
A DW 2B DW 5SUM DW ?
.CODEMAIN PROC; initialize DS
MOV AX, @DATAMOV DS, AX
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Program Structure: An Example
; add the numbers
MOV AX, A
ADD AX, B
MOV SUM, AX
; exit to DOS
MOV AX, 4C00H
INT 21H
MAIN ENDP
END MAIN
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NAME Addition
β’ TITLE 8086 assembly language program to add two Nos.β’ .model smallβ’ Org 100hβ’ .dataβ’ no1 db 33h ; First number storageβ’ no2 db 22h ; Second number storageβ’ result db ? ; byte reversed for resultβ’ .codeβ’ start: mov ax,@data ; [loads the address of dataβ’ mov ds,ax ; segment in DS]β’ mov al,no1 ; Get the first nuber in ALβ’ add al,no2 ; Add second to itβ’ mov result, ax ; Copy result to memoryβ’ end startβ’ end
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Addition with carry
73
β’ org 100h
β’ .data
β’ a db 0ffh
β’ b db 02h
β’ sum db ?
β’ carry db ?
β’ .data end
β’ .code
β’ start: mov ax,@data
β’ mov ds,ax
β’ xor ax,ax
β’ mov cl,00h
β’ mov al,a
β’ mov bl,b
β’ add al,bl
β’ jnc down
β’ inc cl
β’ down: mov sum, al
β’ mov carry, cl
β’ end code
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Example calculates the sum of a vector
β’ Org 100h
β’ vec1 db 1, 2, 5, 6
β’ vec2 db 3, 5, 6, 1
β’ vec3 db ?, ?, ?, ?
β’ start:
β’ lea si, vec1
β’ lea bx, vec2
β’ lea di, vec3
β’ mov cx, 4
β’ sum:
β’ mov al, [si]
β’ add al, [bx]
β’ mov [di], al
β’ inc si
β’ inc bx
β’ inc di
β’ loop sum
β’ end 74
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find average of two numbers.
β’ NAME Average
β’ TITLE 8086 ALP to find average of two numbers.β’ .model smallβ’ .stack 100β’ .dataβ’ No1 DB 21h ; First number storageβ’ No2 DB 23h ; Second number storageβ’ Avg DB ? ; Average of two numbersβ’ .codeβ’ START: MOV AX, @data ; [ Initialisesβ’ MOV DS,AX β’ XOR AX,AX ; data segment ]β’ MOV AL,NO1 ; Get first number in ALβ’ ADD AL,NO2 ; Add second to itβ’ ADC AH,00H ; Put carry in AHβ’ SAR AX,1 ; Divide sum by 2β’ MOV Avg, AL ; Copy result to memoryβ’ END START
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Bus Timing diagram
The 8086/8088 microprocessors use the memory and I/O in periods called bus cycles.
Each bus cycle consists of 4 clock cycles.
Thus for 8086 running at 5MHz it would take 800ns for a complete bus cycle.
Each read or write operation take 1 bus cycles.
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Read Timing
Bus Timing diagram
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Read Timing
During T 1 :
β’The address is placed on the Address/Data bus.
β’Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the address onto the address bus and set the direction of data transfer on data bus.
Bus Timing diagram
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Read Timing
During T 2 :
β’8086 issues the RD or WRsignal, DEN , and, for a write, the data.
β’DEN enables the memory or I/O device to receive the data for writes and the 8086 to receive the data for reads.
Bus Timing diagram
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During T 3 :β’This cycle is provided to allow memory to access data.β’READY is sampled at the end of T 2 .
β’If low, T 3 becomes a wait state.β’Otherwise, the data bus is sampled at the end of T 3 .
During T :
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During T 4 :β’All bus signals are deactivated, in preparation for next bus cycle.β’Data is sampled for reads, writes occur for writes.
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Write Timing
Convert this simple timeline to include all the necessary pins Do as an EXERCISE !
Bus Timing diagram
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ADDRESSING MODESADDRESSING MODESADDRESSING MODESADDRESSING MODES
&&&&
Instruction setInstruction setInstruction setInstruction set
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Introduction
84
Program is a set of instructions written to solve a problem. Instructions arethe directions which a microprocessor follows to execute a task or part of atask. Broadly, computer language can be divided into two parts as high-level language and low level language. Low level language are machinespecific. Low level language can be further divided into machine languageand assembly language.
Machine language is the only language which a machine can understand.Instructions in this language are written in binary bits as a specific bitpattern. The computer interprets this bit pattern as an instruction toperform a particular task. The entire program is a sequence of binarynumbers. This is a machine-friendly language but not user friendly.Debugging is another problem associated with machine language.
To overcome these problems, programmers develop another way in whichinstructions are written in English alphabets. This new language is knownas Assembly language. The instructions in this language are termedmnemonics. As microprocessor can only understand the machinelanguage so mnemonics are translated into machine language eithermanually or by a program known as assembler.
Efficient software development for the microprocessor requires a completefamiliarity with the instruction set, their format and addressing modes. Herein this chapter, we will focus on the addressing modes and instructionsformats of microprocessor 8086.
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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ADDRESSING MODESADDRESSING MODESADDRESSING MODESADDRESSING MODES
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Group I : Addressing modes for register and immediate data
Group IV : Relative Addressing mode
Group V : Implied Addressing mode
Group III : Addressing modes for I/O ports
Group II : Addressing modes for memory data
Addressing Modes
86
8086 8086 8086 8086
MicroprocessorMicroprocessorMicroprocessorMicroprocessor
Every instruction of a program has to operate on a data.The different ways in which a source operand is denotedin an instruction are known as addressing modes.
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
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Addressing Modes
87
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
The instruction will specify the name of theregister which holds the data to be operated bythe instruction.
Example:
MOV CL, DH
The content of 8-bit register DH is moved toanother 8-bit register CL
(CL) ββββ (DH)
Group I : Addressing modes for register and immediate data8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Addressing Modes
88
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
In immediate addressing mode, an 8-bit or 16-bitdata is specified as part of the instruction
Example:
MOV DL, 08H
The 8-bit data (08H) given in the instruction ismoved to DL
(DL) ββββ 08H
MOV AX, 0A9FH
The 16-bit data (0A9FH) given in the instruction ismoved to AX register
(AX) ββββ 0A9FH
Group I : Addressing modes for register and immediate data8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Addressing Modes : Memory Access
89
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Addressing Modes : Memory Access
90
20 Address lines ββββ 8086 can address up to 220 = 1M bytes of memory
However, the largest register is only 16 bits
Physical Address will have to be calculated Physical Address : Actual address of a byte in memory. i.e. the value which goes out onto the address bus.
Memory Address represented in the form βSeg : Offset (E g - 89AB:F012)
Each time the processor wants to access memory, it takes the contents of a segment register, shifts it one hexadecimal place to the left (same as multiplying by 1610), then add the required offset to form the 20- bit address
89AB : F012 ββββ 89AB ββββ 89AB0 (Paragraph to byte ββββ 89AB x 10 = 89AB0)F012 ββββ 0F012 (Offset is already in byte unit)
+ -------98AC2 (The absolute address)
16 bytes of contiguous memory
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Addressing Modes : Memory Access
91
To access memory we use these four registers: BX, SI, DI, BP
Combining these registers inside [ ] symbols, we can get different memory locations (Effective Address, EA)
Supported combinations:
[BX + SI][BX + DI][BP + SI][BP + DI]
[SI][DI]d16 (variable offset only)[BX]
[BX + SI + d8][BX + DI + d8][BP + SI + d8][BP + DI + d8]
BX
BP
SI
DI+ disp
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Addressing Modes
92
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
Here, the effective address of the memorylocation at which the data operand is stored isgiven in the instruction.
The effective address is just a 16-bit numberwritten directly in the instruction.
Example:
MOV BL, [0400H]
The square brackets around the 0400H denotesthe contents of the memory location. Whenexecuted, this instruction will copy the contents ofthe memory location into BL register.
This addressing mode is called direct because thedisplacement of the operand from the segmentbase is specified directly in the instruction.
Group II : Addressing modes for memory data8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Addressing Modes
93
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
In Register indirect addressing, name of theregister which holds the effective address (EA)will be specified in the instruction.
Registers used to hold EA are any of the followingregisters:
BX, BP, DI and SI.
Content of the DS register is used for baseaddress calculation.
Example:
MOV CX, [BX]
Operations:
EA = (BX)BA = (DS) x 1610
MA = BA + EA
(CX) ββββ (MA) or,
(CL) ββββ (MA)(CH) ββββ (MA +1)
Group II : Addressing modes for memory data
Note : Register/ memoryenclosed in brackets referto content of register/memory
8086 8086 8086 8086 MicroprocessorMicroprocessorMicroprocessorMicroprocessor
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Addressing Modes
94
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
In Based Addressing, BX or BP is used to hold thebase value for effective address and a signed 8-bitor unsigned 16-bit displacement will be specifiedin the instruction.
In case of 8-bit displacement, it is sign extendedto 16-bit before adding to the base value.
When BX holds the base value of EA, 20-bitphysical address is calculated from BX and DS.
When BP holds the base value of EA, BP and SS isused.
Example:
MOV AX, [BX + 08H]
Operations:
0008H ββββ 08H (Sign extended)
EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA
(AX) ββββ (MA) or,
(AL) ββββ (MA)(AH) ββββ (MA + 1)
Group II : Addressing modes for memory data8086 8086 8086 8086 MicroprocessorMicroprocessorMicroprocessorMicroprocessor
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Addressing Modes
95
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
SI or DI register is used to hold an index value formemory data and a signed 8-bit or unsigned 16-bit displacement will be specified in theinstruction.
Displacement is added to the index value in SI orDI register to obtain the EA.
In case of 8-bit displacement, it is sign extendedto 16-bit before adding to the base value.
Example:
MOV CX, [SI + FFA2H]
Operations:
FFA2H ββββ FFA2H (Sign extended)
EA = (SI) + FFA2H
BA = (DS) x 1610
MA = BA + EA
(CX) ββββ (MA) or,
(CL) ββββ (MA)(CH) ββββ (MA + 1)
Group II : Addressing modes for memory data8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Addressing Modes
96
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
In Based Index Addressing, the effective addressis computed from the sum of a base register (BXor BP), an index register (SI or DI) and adisplacement.
Example:
MOV DX, [BX + SI + 0AH]
Operations:
000AH ββββ 0AH (Sign extended)
EA = (BX) + (SI) + 000AH
BA = (DS) x 1610
MA = BA + EA
(DX) ββββ (MA) or,
(DL) ββββ (MA)(DH) ββββ (MA + 1)
Group II : Addressing modes for memory data8086 8086 8086 8086 MicroprocessorMicroprocessorMicroprocessorMicroprocessor
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Addressing Modes
97
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
Employed in string operations to operate on stringdata.
The effective address (EA) of source data is storedin SI register and the EA of destination is stored inDI register.
Segment register for calculating base address ofsource data is DS and that of the destination datais ES
Example: MOVS BYTE
Operations:
Calculation of source memory location:EA = (SI) BA = (DS) x 1610 MA = BA + EA
Calculation of destination memory location:EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
(MAE) ββββ (MA)
If DF = 1, then (SI) ββββ (SI) β 1 and (DI) = (DI) - 1If DF = 0, then (SI) ββββ (SI) +1 and (DI) = (DI) + 1
Group II : Addressing modes for memory data
Note : Effective address ofthe Extra segment register
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Addressing Modes
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
These addressing modes are used to access datafrom standard I/O mapped devices or ports.
In direct port addressing mode, an 8-bit portaddress is directly specified in the instruction.
Example: IN AL, [09H]
Operations: PORTaddr = 09H
(AL) ββββ (PORT)
Content of port with address 09H ismoved to AL register
In indirect port addressing mode, the instructionwill specify the name of the register which holdsthe port address. In 8086, the 16-bit port addressis stored in the DX register.
Example: OUT [DX], AX
Operations: PORTaddr = (DX)(PORT) ββββ (AX)
Content of AX is moved to portwhose address is specified by DXregister. 98
Group III : Addressing modes for I/O ports8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Addressing Modes
99
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
In this addressing mode, the effective address ofa program instruction is specified relative toInstruction Pointer (IP) by an 8-bit signeddisplacement.
Example: JZ 0AH
Operations:
000AH ββββ 0AH (sign extend)
If ZF = 1, then
EA = (IP) + 000AH
BA = (CS) x 1610
MA = BA + EA
If ZF = 1, then the program control jumps tonew address calculated above.
If ZF = 0, then next instruction of theprogram is executed.
Group IV : Relative Addressing mode8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Addressing Modes
100
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
Instructions using this mode have no operands.The instruction itself will specify the data to beoperated by the instruction.
Example: CLC
This clears the carry flag to zero.
Group IV : Implied Addressing mode8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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INSTRUCTION SETINSTRUCTION SETINSTRUCTION SETINSTRUCTION SET
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1. Data Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. String manipulation Instructions
5. Process Control Instructions
6. Control Transfer Instructions
Instruction Set
102
8086 8086 8086 8086
MicroprocessorMicroprocessorMicroprocessorMicroprocessor
8086 supports 6 types of instructions.
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1. Data Transfer Instructions
Instruction Set
103
Instructions that are used to transfer data/ address in to registers, memory locations and I/O ports.
Generally involve two operands: Source operand and Destination operand of the same size.
Source: Register or a memory location or an immediate dataDestination : Register or a memory location.
The size should be a either a byte or a word.
A 8-bit data can only be moved to 8-bit register/ memory and a 16-bit data can be moved to 16-bit register/ memory.
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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1. Data Transfer Instructions
Instruction Set
104
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT β¦
MOV reg2/ mem, reg1/ mem
MOV reg2, reg1 MOV mem, reg1MOV reg2, mem
(reg2) ββββ (reg1)(mem) ββββ (reg1) (reg2) ββββ (mem)
MOV reg/ mem, data
MOV reg, dataMOV mem, data
(reg) ββββ data(mem) ββββ data
XCHG reg2/ mem, reg1
XCHG reg2, reg1XCHG mem, reg1
(reg2) ββββ (reg1)(mem) ββββ (reg1)
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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1. Data Transfer Instructions
Instruction Set
105
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT β¦
PUSH reg16/ mem
PUSH reg16
PUSH mem
(SP) ββββ (SP) β 2MA S = (SS) x 1610 + SP(MA S ; MA S + 1) ββββ (reg16)
(SP) ββββ (SP) β 2MA S = (SS) x 1610 + SP(MA S ; MA S + 1) ββββ (mem)
POP reg16/ mem
POP reg16
POP mem
MA S = (SS) x 1610 + SP(reg16) ββββ (MA S ; MA S + 1)(SP) ββββ (SP) + 2
MA S = (SS) x 1610 + SP(mem) ββββ (MA S ; MA S + 1)(SP) ββββ (SP) + 2
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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1. Data Transfer Instructions
Instruction Set
106
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT β¦
IN A, [DX]
IN AL, [DX]
IN AX, [DX]
PORTaddr = (DX)(AL) ββββ (PORT)
PORTaddr = (DX)(AX) ββββ (PORT)
IN A, addr8
IN AL, addr8
IN AX, addr8
(AL) ββββ (addr8)
(AX) ββββ (addr8)
OUT [DX], A
OUT [DX], AL
OUT [DX], AX
PORTaddr = (DX)(PORT) ββββ (AL)
PORTaddr = (DX)(PORT) ββββ (AX)
OUT addr8, A
OUT addr8, AL
OUT addr8, AX
(addr8) ββββ (AL)
(addr8) ββββ (AX)
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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2. Arithmetic Instructions
Instruction Set
107
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMPβ¦
ADD reg2/ mem, reg1/mem
ADD reg2, reg1ADD reg2, memADD mem, reg1
(reg2) ββββ (reg1) + (reg2)(reg2) ββββ (reg2) + (mem)(mem) ββββ (mem)+(reg1)
ADD reg/mem, data
ADD reg, dataADD mem, data
(reg) ββββ (reg)+ data(mem) ββββ (mem)+data
ADD A, data
ADD AL, data8ADD AX, data16
(AL) ββββ (AL) + data8(AX) ββββ (AX) +data16
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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2. Arithmetic Instructions
Instruction Set
108
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMPβ¦
ADC reg2/ mem, reg1/mem
ADC reg2, reg1ADC reg2, memADC mem, reg1
(reg2) ββββ (reg1) + (reg2)+CF(reg2) ββββ (reg2) + (mem)+CF(mem) ββββ (mem)+(reg1)+CF
ADC reg/mem, data
ADC reg, dataADC mem, data
(reg) ββββ (reg)+ data+CF(mem) ββββ (mem)+data+CF
ADDC A, data
ADD AL, data8ADD AX, data16
(AL) ββββ (AL) + data8+CF(AX) ββββ (AX) +data16+CF
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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2. Arithmetic Instructions
Instruction Set
109
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMPβ¦
SUB reg2/ mem, reg1/mem
SUB reg2, reg1SUB reg2, memSUB mem, reg1
(reg2) ββββ (reg2) - (reg1)(reg2) ββββ (reg2) - (mem)(mem) ββββ (mem) - (reg1)
SUB reg/mem, data
SUB reg, dataSUB mem, data
(reg) ββββ (reg) - data(mem) ββββ (mem) - data
SUB A, data
SUB AL, data8SUB AX, data16
(AL) ββββ (AL) - data8(AX) ββββ (AX) - data16
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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2. Arithmetic Instructions
Instruction Set
110
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMPβ¦
SBB reg2/ mem, reg1/mem
SBB reg2, reg1SBB reg2, memSBB mem, reg1
(reg2) ββββ (reg2) - (reg1) - CF(reg2) ββββ (reg2) - (mem)- CF(mem) ββββ (mem) - (reg1) βCF
SBB reg/mem, data
SBB reg, dataSBB mem, data
(reg) ββββ (reg) β data - CF(mem) ββββ (mem) - data - CF
SBB A, data
SBB AL, data8SBB AX, data16
(AL) ββββ (AL) - data8 - CF(AX) ββββ (AX) - data16 - CF
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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2. Arithmetic Instructions
Instruction Set
111
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMPβ¦
INC reg/ mem
INC reg8
INC reg16
INC mem
(reg8) ββββ (reg8) + 1
(reg16) ββββ (reg16) + 1
(mem) ββββ (mem) + 1
DEC reg/ mem
DEC reg8
DEC reg16
DEC mem
(reg8) ββββ (reg8) - 1
(reg16) ββββ (reg16) - 1
(mem) ββββ (mem) - 1
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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2. Arithmetic Instructions
Instruction Set
112
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMPβ¦
MUL reg/ mem
MUL reg
MUL mem
For byte : (AX) ββββ (AL) x (reg8)For word : (DX)(AX) ββββ (AX) x (reg16)
For byte : (AX) ββββ (AL) x (mem8)For word : (DX)(AX) ββββ (AX) x (mem16)
IMUL reg/ mem
IMUL reg
IMUL mem
For byte : (AX) ββββ (AL) x (reg8)For word : (DX)(AX) ββββ (AX) x (reg16)
For byte : (AX) ββββ (AX) x (mem8)For word : (DX)(AX) ββββ (AX) x (mem16)
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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2. Arithmetic Instructions
Instruction Set
113
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMPβ¦
DIV reg/ mem
DIV reg
DIV mem
For 16-bit :- 8-bit :(AL) ββββ (AX) :- (reg8) Quotient(AH) ββββ (AX) MOD(reg8) Remainder
For 32-bit :- 16-bit :(AX) ββββ (DX)(AX) :- (reg16) Quotient(DX) ββββ (DX)(AX) MOD(reg16) Remainder
For 16-bit :- 8-bit :(AL) ββββ (AX) :- (mem8) Quotient(AH) ββββ (AX) MOD(mem8) Remainder
For 32-bit :- 16-bit :(AX) ββββ (DX)(AX) :- (mem16) Quotient(DX) ββββ (DX)(AX) MOD(mem16) Remainder
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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2. Arithmetic Instructions
Instruction Set
114
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMPβ¦
IDIV reg/ mem
IDIV reg
IDIV mem
For 16-bit :- 8-bit :(AL) ββββ (AX) :- (reg8) Quotient(AH) ββββ (AX) MOD(reg8) Remainder
For 32-bit :- 16-bit :(AX) ββββ (DX)(AX) :- (reg16) Quotient(DX) ββββ (DX)(AX) MOD(reg16) Remainder
For 16-bit :- 8-bit :(AL) ββββ (AX) :- (mem8) Quotient(AH) ββββ (AX) MOD(mem8) Remainder
For 32-bit :- 16-bit :(AX) ββββ (DX)(AX) :- (mem16) Quotient(DX) ββββ (DX)(AX) MOD(mem16) Remainder
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2. Arithmetic Instructions
Instruction Set
115
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMPβ¦
CMP reg2/mem, reg1/ mem
CMP reg2, reg1
CMP reg2, mem
CMP mem, reg1
Modify flags ββββ (reg2) β (reg1)
If (reg2) > (reg1) then CF=0, ZF=0, SF=0If (reg2) < (reg1) then CF=1, ZF=0, SF=1If (reg2) = (reg1) then CF=0, ZF=1, SF=0
Modify flags ββββ (reg2) β (mem)
If (reg2) > (mem) then CF=0, ZF=0, SF=0If (reg2) < (mem) then CF=1, ZF=0, SF=1If (reg2) = (mem) then CF=0, ZF=1, SF=0
Modify flags ββββ (mem) β (reg1)
If (mem) > (reg1) then CF=0, ZF=0, SF=0If (mem) < (reg1) then CF=1, ZF=0, SF=1If (mem) = (reg1) then CF=0, ZF=1, SF=0
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2. Arithmetic Instructions
Instruction Set
116
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMPβ¦
CMP reg/mem, data
CMP reg, data
CMP mem, data
Modify flags ββββ (reg) β (data)
If (reg) > data then CF=0, ZF=0, SF=0If (reg) < data then CF=1, ZF=0, SF=1If (reg) = data then CF=0, ZF=1, SF=0
Modify flags ββββ (mem) β (mem)
If (mem) > data then CF=0, ZF=0, SF=0If (mem) < data then CF=1, ZF=0, SF=1If (mem) = data then CF=0, ZF=1, SF=0
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2. Arithmetic Instructions
Instruction Set
117
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMPβ¦
CMP A, data
CMP AL, data8
CMP AX, data16
Modify flags ββββ (AL) β data8
If (AL) > data8 then CF=0, ZF=0, SF=0If (AL) < data8 then CF=1, ZF=0, SF=1If (AL) = data8 then CF=0, ZF=1, SF=0
Modify flags ββββ (AX) β data16
If (AX) > data16 then CF=0, ZF=0, SF=0If (mem) < data16 then CF=1, ZF=0, SF=1If (mem) = data16 then CF=0, ZF=1, SF=0
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3. Logical Instructions
Instruction Set
118
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL β¦
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3. Logical Instructions
Instruction Set
119
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL β¦
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3. Logical Instructions
Instruction Set
120
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL β¦
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3. Logical Instructions
Instruction Set
121
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL β¦
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3. Logical Instructions
Instruction Set
122
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL β¦
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3. Logical Instructions
Instruction Set
123
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL β¦
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3. Logical Instructions
Instruction Set
124
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL β¦
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3. Logical Instructions
Instruction Set
125
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL β¦
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4. String Manipulation Instructions
Instruction Set
126
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
οΏ½ String : Sequence of bytes or words
οΏ½ 8086 instruction set includes instruction for string movement, comparison, scan, load and store.
οΏ½ REP instruction prefix : used to repeat execution of string instructions
οΏ½ String instructions end with S or SB or SW. S represents string, SB string byte and SW string word.
οΏ½ Offset or effective address of the source operand is stored in SI register and that of the destination operand is stored in DI register.
οΏ½ Depending on the status of DF, SI and DI registers are automatically updated.
οΏ½ DF = 0 ββββ SI and DI are incremented by 1 for byte and 2 for word.
οΏ½ DF = 1 ββββ SI and DI are decremented by 1 for byte and 2 for word.
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4. String Manipulation Instructions
Instruction Set
127
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
REP
REPZ/ REPE
(Repeat CMPS or SCAS untilZF = 0)
REPNZ/ REPNE
(Repeat CMPS or SCAS untilZF = 1)
While CX β β β β 0 and ZF = 1, repeat execution of string instruction and(CX) ββββ (CX) β 1
While CX β β β β 0 and ZF = 0, repeat execution of string instruction and(CX) ββββ (CX) - 1
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4. String Manipulation Instructions
Instruction Set
128
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
MOVS
MOVSB
MOVSW
MA = (DS) x 1610 + (SI)MAE = (ES) x 1610 + (DI)
(MAE) ββββ (MA)
If DF = 0, then (DI) ββββ (DI) + 1; (SI) ββββ (SI) + 1If DF = 1, then (DI) ββββ (DI) - 1; (SI) ββββ (SI) - 1
MA = (DS) x 1610 + (SI)MAE = (ES) x 1610 + (DI)
(MAE ; MAE + 1) ββββ (MA; MA + 1)
If DF = 0, then (DI) ββββ (DI) + 2; (SI) ββββ (SI) + 2If DF = 1, then (DI) ββββ (DI) - 2; (SI) ββββ (SI) - 2
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4. String Manipulation Instructions
Instruction Set
129
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
CMPS
CMPSB
CMPSW
MA = (DS) x 1610 + (SI)MAE = (ES) x 1610 + (DI)
Modify flags ββββ (MA) - (MAE)
If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0
For byte operationIf DF = 0, then (DI) ββββ (DI) + 1; (SI) ββββ (SI) + 1If DF = 1, then (DI) ββββ (DI) - 1; (SI) ββββ (SI) - 1
For word operationIf DF = 0, then (DI) ββββ (DI) + 2; (SI) ββββ (SI) + 2If DF = 1, then (DI) ββββ (DI) - 2; (SI) ββββ (SI) - 2
Compare two string byte or string word
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4. String Manipulation Instructions
Instruction Set
130
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
SCAS
SCASB
SCASW
MAE = (ES) x 1610 + (DI)Modify flags ββββ (AL) - (MAE)
If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI) ββββ (DI) + 1 If DF = 1, then (DI) ββββ (DI) β 1
MAE = (ES) x 1610 + (DI)Modify flags ββββ (AL) - (MAE)
If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI) ββββ (DI) + 2 If DF = 1, then (DI) ββββ (DI) β 2
Scan (compare) a string byte or word with accumulator
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4. String Manipulation Instructions
Instruction Set
131
8086 8086 8086 8086
MicroprocessorMicroprocessorMicroprocessorMicroprocessor
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
LODS
LODSB
LODSW
MA = (DS) x 1610 + (SI)(AL) ββββ (MA)
If DF = 0, then (SI) ββββ (SI) + 1 If DF = 1, then (SI) ββββ (SI) β 1
MA = (DS) x 1610 + (SI)(AX) ββββ (MA ; MA + 1)
If DF = 0, then (SI) ββββ (SI) + 2 If DF = 1, then (SI) ββββ (SI) β 2
Load string byte in to AL or string word in to AX
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4. String Manipulation Instructions
Instruction Set
132
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
STOS
STOSB
STOSW
MAE = (ES) x 1610 + (DI)(MAE) ββββ (AL)
If DF = 0, then (DI) ββββ (DI) + 1 If DF = 1, then (DI) ββββ (DI) β 1
MAE = (ES) x 1610 + (DI)(MAE ; MAE + 1 ) ββββ (AX)
If DF = 0, then (DI) ββββ (DI) + 2 If DF = 1, then (DI) ββββ (DI) β 2
Store byte from AL or word from AX in to string
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Mnemonics Explanation
STC Set CF ββββ 1
CLC Clear CF ββββ 0
CMC Complement carry CF ββββ CF/
STD Set direction flag DF ββββ 1
CLD Clear direction flag DF ββββ 0
STI Set interrupt enable flag IF ββββ 1
CLI Clear interrupt enable flag IF ββββ 0
NOP No operation
HLT Halt after interrupt is set
WAIT Wait for TEST pin active
ESC opcode mem/ reg Used to pass instruction to a coprocessor which shares the address and data bus with the 8086
LOCK Lock bus during next instruction
5. Processor Control Instructions
Instruction Set
133
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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6. Control Transfer Instructions
Instruction Set
134
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Transfer the control to a specific destination or target instructionDo not affect flags
Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine
RET Return from subroutine
JMP reg/ mem/ disp8/ disp16 Unconditional jump
οΏ½ 8086 Unconditional transfers
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6. Control Transfer Instructions
Instruction Set
135
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
οΏ½ 8086 signed conditional branch instructions
οΏ½ 8086 unsigned conditional branch instructions
Checks flags
If conditions are true, the program control is transferred to the new memory location in the same segment by modifying the content of IP
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6. Control Transfer Instructions
Instruction Set
136
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Name Alternate name
JE disp8Jump if equal
JZ disp8Jump if result is 0
JNE disp8Jump if not equal
JNZ disp8Jump if not zero
JG disp8Jump if greater
JNLE disp8Jump if not less or equal
JGE disp8Jump if greater than or equal
JNL disp8Jump if not less
JL disp8Jump if less than
JNGE disp8Jump if not greater than or equal
JLE disp8Jump if less than or equal
JNG disp8Jump if not greater
οΏ½ 8086 signed conditional branch instructions
οΏ½ 8086 unsigned conditional branch instructions
Name Alternate name
JE disp8Jump if equal
JZ disp8Jump if result is 0
JNE disp8Jump if not equal
JNZ disp8Jump if not zero
JA disp8Jump if above
JNBE disp8Jump if not below or equal
JAE disp8Jump if above or equal
JNB disp8Jump if not below
JB disp8Jump if below
JNAE disp8Jump if not above or equal
JBE disp8Jump if below or equal
JNA disp8Jump if not above
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6. Control Transfer Instructions
Instruction Set
137
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Mnemonics Explanation
JC disp8 Jump if CF = 1
JNC disp8 Jump if CF = 0
JP disp8 Jump if PF = 1
JNP disp8 Jump if PF = 0
JO disp8 Jump if OF = 1
JNO disp8 Jump if OF = 0
JS disp8 Jump if SF = 1
JNS disp8 Jump if SF = 0
JZ disp8 Jump if result is zero, i.e, Z = 1
JNZ disp8 Jump if result is not zero, i.e, Z = 1
οΏ½ 8086 conditional branch instructions affecting individual flags
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AssemblerAssemblerAssemblerAssembler directivesdirectivesdirectivesdirectives
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Assemble Directives
139
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Instructions to the Assembler regarding the program being executed.
Control the generation of machine codes and organization of the program; but no machine codes are generated for assembler directives.
Also called βpseudo instructionsβ
Used to :βΊ specify the start and end of a programβΊ attach value to variablesβΊ allocate storage locations to input/ output dataβΊ define start and end of segments, procedures, macros etc..
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Assemble Directives
140
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Define Byte
Define a byte type (8-bit) variable
Reserves specific amount of memory locations to each variable
Range : 00H β FFH for unsigned value; 00H β 7FH for positive value and 80H β FFH for negative value
General form : variable DB value/ values
Example:
LIST DB 7FH, 42H, 35H
Three consecutive memory locations are reserved forthe variable LIST and each data specified in theinstruction are stored as initial value in the reservedmemory location
DB
DW
SEGMENTENDS
ASSUME
ORGENDEVENEQU
PROCFARNEARENDP
SHORT
MACROENDM
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Assemble Directives
141
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Define Word
Define a word type (16-bit) variable
Reserves two consecutive memory locations to each variable
Range : 0000H β FFFFH for unsigned value; 0000H β 7FFFH for positive value and 8000H β FFFFH for negative value
General form : variable DW value/ values
Example:
ALIST DW 6512H, 0F251H, 0CDE2H
Six consecutive memory locations are reserved forthe variable ALIST and each 16-bit data specified inthe instruction is stored in two consecutive memorylocation.
DB
DW
SEGMENTENDS
ASSUME
ORGENDEVENEQU
PROCFARNEARENDP
SHORT
MACROENDM
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Assemble Directives
142
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
SEGMENT : Used to indicate the beginning of a code/ data/ stack segment
ENDS : Used to indicate the end of a code/ data/ stack segment
General form:
Segnam SEGMENT
β¦β¦β¦β¦β¦β¦
Segnam ENDS
Program code orData Defining Statements
User defined name of the segment
DB
DW
SEGMENTENDS
ASSUME
ORGENDEVENEQU
PROCFARNEARENDP
SHORT
MACROENDM
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Assemble Directives
143
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
DB
DW
SEGMENTENDS
ASSUME
ORGENDEVENEQU
PROCFARNEARENDP
SHORT
MACROENDM
Informs the assembler the name of the program/ data segment that should be used for a specific segment.
General form:
Segment Register
ASSUME segreg : segnam, .. , segreg : segnam
User defined name of the segment
ASSUME CS: ACODE, DS:ADATA Tells the compiler that theinstructions of the program arestored in the segment ACODE anddata are stored in the segmentADATA
Example:
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Assemble Directives
144
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
DB
DW
SEGMENTENDS
ASSUME
ORGENDEVENEQU
PROCFARNEARENDP
SHORT
MACROENDM
ORG (Origin) is used to assign the starting address (Effective address) for a program/ data segment
END is used to terminate a program; statements after END will be ignored
EVEN : Informs the assembler to store program/ data segment starting from an even address
EQU (Equate) is used to attach a value to a variable
ORG 1000H Informs the assembler that the statementsfollowing ORG 1000H should be stored inmemory starting with effective address1000H
LOOP EQU 10FEH Value of variable LOOP is 10FEH
_SDATA SEGMENTORG 1200HA DB 4CHEVENB DW 1052H
_SDATA ENDS
In this data segment, effective address ofmemory location assigned to A will be 1200H
and that of B will be 1202H and 1203H.
Examples:
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Assemble Directives
145
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
DB
DW
SEGMENTENDS
ASSUME
ORGENDEVENEQU
PROCENDPFARNEAR
SHORT
MACROENDM
PROC Indicates the beginning of a procedure
ENDP End of procedure
FAR Intersegment call
NEAR Intrasegment call
General form
procname PROC[NEAR/ FAR]
β¦β¦β¦
RET
procname ENDP
Program statements of the procedure
Last statement of the procedure
User defined name of the procedure
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Assemble Directives
146
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
DB
DW
SEGMENTENDS
ASSUME
ORGENDEVENEQU
PROCENDPFARNEAR
SHORT
MACROENDM
ADD64 PROC NEAR
β¦β¦β¦
RETADD64 ENDP
The subroutine/ procedure named ADD64 isdeclared as NEAR and so the assembler willcode the CALL and RET instructions involvedin this procedure as near call and return
CONVERT PROC FAR
β¦β¦β¦
RETCONVERT ENDP
The subroutine/ procedure named CONVERTis declared as FAR and so the assembler willcode the CALL and RET instructions involvedin this procedure as far call and return
Examples:
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Assemble Directives
147
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
DB
DW
SEGMENTENDS
ASSUME
ORGENDEVENEQU
PROCENDPFARNEAR
SHORT
MACROENDM
Reserves one memory location for 8-bit signed displacement in jump instructions
JMP SHORT AHEAD
The directive will reserve onememory location for 8-bitdisplacement named AHEAD
Example:
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Assemble Directives
148
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
DB
DW
SEGMENTENDS
ASSUME
ORGENDEVENEQU
PROCENDPFARNEAR
SHORT
MACROENDM
MACRO Indicate the beginning of a macro
ENDM End of a macro
General form:
macroname MACRO[Arg1, Arg2 ...]
β¦β¦β¦
macroname ENDM
Program statements in the macro
User defined name of the macro
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149
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Interfacing memory and i/o Interfacing memory and i/o Interfacing memory and i/o Interfacing memory and i/o
portsportsportsports
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Memory
151
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Memory
Processor Memory
Primary or Main Memory
Secondary Memory
Store Programs and Data
οΏ½ Registers inside a microcomputerοΏ½ Store data and results temporarilyοΏ½ No speed disparityοΏ½ Cost ββββ
οΏ½ Storage area which can be directly accessed by microprocessor
οΏ½ Store programs and data prior to execution
οΏ½ Should not have speed disparity with processor ββββ Semi Conductor memories using CMOS technology
οΏ½ ROM, EPROM, Static RAM, DRAM
οΏ½ Storage media comprising of slow devices such as magnetic tapes and disks
οΏ½ Hold large data files and programs: Operating system, compilers, databases, permanent programs etc.
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Memory organization in 8086
152
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
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Memory organization in 8086
153
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Operation A0 Data Lines Used
1 Read/ Write byte at an even address 1 0 D7 β D0
2 Read/ Write byte at an odd address 0 1 D15 β D8
3 Read/ Write word at an even address 0 0 D15 β D0
4 Read/ Write word at an odd address 0 1 D15 β D0 in first operation byte from odd bank is transferred
1 0 D7 β D0 in first operation byte from odd bank is transferred
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Memory organization in 8086
154
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Available memory space = EPROM + RAM
Allot equal address space in odd and even bank for both EPROM and RAM
Can be implemented in two ICβs (one for even and other for odd) or in multiple ICβs
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Interfacing SRAM and EPROM
155
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Memory interface ββββ Read from and write in to a set of semiconductor memory IC chip
EPROM ββββ Read operations
RAM ββββ Read and Write
In order to perform read/ write operations,
Memory access time <<<< read / write time of the processor
Chip Select (CS) signal has to be generated
Control signals for read / write operations
Allot address for each memory location
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Interfacing SRAM and EPROM
156
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Typical Semiconductor IC Chip
No ofAddress
pins
Memory capacity Range of address in
hexaIn Decimal In kilo In hexa
20 220= 10,48,576 1024 k = 1M 100000 00000to
FFFFF
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Interfacing SRAM and EPROM
157
8086 Microprocessor8086 Microprocessor8086 Microprocessor8086 Microprocessor
Memory map of 8086
RAM are mapped at the beginning; 00000H is allotted to RAM
EPROMβs are mapped at FFFFFH
ββββ Facilitate automatic execution of monitor programs and creation of interrupt vector table
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Monitor Programs
Certain locations in 1Mbyte memory are reserved
Location from: FFFF0H to FFFF5H are dedicated to the initialization procedure of 8086
FFFF6H to FFFFBH are dedicated to the initialization procedure of 8086 input/output procedure .
00000H to 00013H used for vector addresses of dedicated interrupts.
Intel has also reserved several locations for future hardware and software products.
like 00014H to 0007FH and FFFFCH to FFFFFH
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Interfacing SRAM and EPROM
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Monitor Programs
ββββ Programing 8279 for keyboard scanning and display refreshing
ββββ Programming peripheral ICβs 8259, 8257, 8255, 8251, 8254 etc
ββββ Initialization of stack
ββββ Display a message on display (output)
ββββ Initializing interrupt vector table
8279 Programmable keyboard/ display controller
8257 DMA controller
8259 Programmable interrupt controller
8255 Programmable peripheral interface
Note :
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Interfacing I/O and peripheral devices
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I/O devices
ββββ For communication between microprocessor and outside world
ββββ Keyboards, CRT displays, Printers, Compact Discs etc.
ββββ
ββββ Data transfer types
Microprocessor I/ O devicesPorts / Buffer ICβs
(interface circuitry)
Programmed I/ OData transfer is accomplished through an I/O port controlled by software
Interrupt driven I/ OI/O device interrupts the processor and initiate data transfer
Direct memory accessData transfer is achieved by bypassing the microprocessor
Memory mapped
I/O mapped
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8086 and 8088 comparison
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Memory mapping I/O mapping
20 bit address are provided for I/O devices
8-bit or 16-bit addresses are provided for I/O devices
The I/O ports or peripherals can be treated like memory locations and so all instructions related to memory can be used for data transmission between I/O device and processor
Only IN and OUT instructions can be used for data transfer between I/O device and processor
Data can be moved from any register to ports and vice versa
Data transfer takes place only between accumulator and ports
When memory mapping is used for I/O devices, full memory address space cannot be used for addressing memory.
ββββ Useful only for small systems where memory requirement is less
Full memory space can be used for addressing memory.
ββββ Suitable for systems which require large memory capacity
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8086 and 8088 comparison8086 and 8088 comparison8086 and 8088 comparison8086 and 8088 comparison
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8086 and 8088 comparison
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8086 8088
Similar EU and Instruction set ; dissimilar BIU
16-bit Data bus lines obtained by demultiplexing AD0 β AD15
8-bit Data bus lines obtained by demultiplexing AD0 β AD7
20-bit address bus 8-bit address bus
Two banks of memory each of 512 kb
Single memory bank
6-bit instruction queue 4-bit instruction queue
Clock speeds: 5 / 8 / 10 MHz 5 / 8 MHz
No such signal required, since the data width is only 1-byte
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8087 Coprocessor8087 Coprocessor8087 Coprocessor8087 Coprocessor
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Co-processor β Intel 8087
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Multiprocessorsystem
A microprocessor system comprising of two or more processors
Distributed processing: Entire task is divided in to subtasks
Advantages Better system throughput by having more than one processor
Each processor have a local bus to access local memory or I/O devices so that a greater degree of parallel processing can be achieved
System structure is more flexible. One can easily add or remove modules to change the system configuration without affecting the other modules in the system
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Co-processor β Intel 8087
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Specially designed to take care of mathematical calculations involving integer and floating point data
βMath coprocessorβ or βNumeric Data Processor (NDP)β
Works in parallel with a 8086 in the maximum mode
8087 coprocessor
1) Can operate on data of the integer, decimal and real types with lengths ranging from 2 to 10 bytes
2) Instruction set involves square root, exponential, tangent etc. in addition to addition, subtraction, multiplication and division.
3) High performance numeric data processor ββββ it can multiply two 64-bit real numbers in about 27¡¡¡¡s and calculate square root in about 36 ¡¡¡¡s
4) Follows IEEE floating point standard
5) It is multi bus compatible
Features
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Co-processor β Intel 8087
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16 multiplexed address / data pins and 4 multiplexed address / status pins
Hence it can have 16-bit external data bus and 20-bit external address bus like 8086
Processor clock, ready and reset signals are applied as clock, ready and reset signals for coprocessor
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Co-processor β Intel 8087
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BUSY
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Co-processor β Intel 8087
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The request / grant signal from the 8087 is usually connected to the request / grant pin of the independent processor such as 8089
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Co-processor β Intel 8087
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The interrupt pin is connected to the interrupt management logic.
The 8087 can interrupt the 8086 through this interrupt management logic at the time error condition exists
INT
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Co-processor β Intel 8087
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Status
1 0 0 Unused
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive
QS0 β QS1
QS0 QS1 Status
0 0 No operation
0 1 First byte of opcodefrom queue
1 0 Queue empty
1 1 Subsequent byte ofopcode from queue
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Co-processor β Intel 8087
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8087 instructions are inserted in the 8086 program
8086 and 8087 reads instruction bytes and puts them in the respective queues
NOP
8087 instructions have 11011 as the MSB of their first code byte
Ref: Microprocessor, Atul P. Godse, Deepali A. Gode, Technical publications, Chap 11
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Co-processor β Intel 8087
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ESC
Execute the 8086
instructions
WAIT
Monitor 8086/ 8088
Deactivate the Deactivate the hostβs TEST pin and execute the
specific operation
Activate the TEST
pin
Wake up the coprocessor
Wake up the 8086/ 8088
8086/ 8088 Coprocessor
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