mikhail chupilko, alexander kamkin , and dmitry vorobyev institute for system programming of ras
DESCRIPTION
Simulation-Based Verification of Microprocessor Units Based on Cycle-Accurate Contract Specifications. Mikhail Chupilko, Alexander Kamkin , and Dmitry Vorobyev Institute for System Programming of RAS. Cost of microprocessor error. Pentium FDIV Bug (Intel, 1994) The cost is 475 000 000 $ - PowerPoint PPT PresentationTRANSCRIPT
Simulation-Based Verification of Microprocessor Units Based on Cycle-Accurate Contract Specifications
Mikhail Chupilko, Alexander Kamkin, and Dmitry Vorobyev
Institute for System Programming of RAS
SYRCoSE'2008 229-30 May, 2008
Cost of microprocessor error
Pentium FDIV Bug (Intel, 1994) The cost is 475 000 000 $
Phenom (9x00 Stepping B2) L3 Cache’s TLB Errata (AMD, 2007) Implicit negative profit
Design new microprocessor The cost is about 100 000 000 $
SYRCoSE'2008 329-30 May, 2008
Levels of verification
System-level verification
Unit-level verification
Test action
Target system
Test action
Target system
Target unit
SYRCoSE'2008 429-30 May, 2008
Operation execution
Operation
Operands
Time
Clock
Executing 1st stage 2nd stage
SYRCoSE'2008 529-30 May, 2008
Pipelined operations execution
Operation A
Operands
Time
Clock
Executing A1 stage A2 stage
Operation B
Operands
Executing B2 stageB1 stage
Bubble
SYRCoSE'2008 629-30 May, 2008
Contract specifications
pre(input) // obligation for client
output = operation(input)
post(intput, output) // benefit for client
If a client meets the precondition, then the component must fulfill the postcondition
SYRCoSE'2008 729-30 May, 2008
Specification of operations
Operation A Contracts of A’s stages Contract of A
A1
…
AN
guard(A1)post(A1)
guard(AN)post(AN)
…
pre(A)
SYRCoSE'2008 829-30 May, 2008
Idea of the approach
post(A2) post(B1)
Operation A
Operation B
A1 A2 … AN
B1 B2 … BN
Time
Test Oracle
1 2 3 …
SYRCoSE'2008 929-30 May, 2008
Requirements
Requirement is a formal atomic predicate constructed on the defined functions. Types:
Pre – req. on microoperation precondition Guard – req. on microoperation guard condition Update – implicit requirements on
microoperation functionality Post – explicit requirements on
microoperation functionality
SYRCoSE'2008 1029-30 May, 2008
Tool support
The approach is integrated into the CTESK tool from the UniTESK toolkit
Special library is developed to simplify the creation of specifications and tests for Verilog designs using CTESK
http://www.unitesk.com
SYRCoSE'2008 1129-30 May, 2008
Specification example
Floating-point adder
Stage 0: alignment of exponentStage 1: addition of fractionsStage 2: normalization of result
SYRCoSE'2008 1229-30 May, 2008
Catalogue example
Operation ADDStage 0 Stage 1 Stage 2 Stage 3
pre [next cycle] [next cycle] [next cycle]
alignment of exponent
addition of fractions
normalization of result
SYRCoSE'2008 1329-30 May, 2008
Precondition
pre {
return (isZero(op1) || isNormalized(op1))
&& (isZero(op2) || isNormalized(op2));
}
SYRCoSE'2008 1429-30 May, 2008
Postcondition (for stage 3)
post {
return result == op1 + op2;
}
SYRCoSE'2008 1529-30 May, 2008
Case study
The approach was applied to several units of MIPS64-compatible microprocessor: TLB (Translation Lookaside Buffer) L2 Cache
SYRCoSE'2008 1629-30 May, 2008
TLB requirements
Pre Guard Update Post Total Read 5 0 0 2 7 Write 5 0 2 2 9 Probe 5 0 0 3 8 Translate
(Data) 5 0 3 30 38 Translate
(Instruction) 5 3 2 27 37 Total 25 3 7 64 99
SYRCoSE'2008 1729-30 May, 2008
TLB verification results
Specification consists 2.5 KLOC Labor-costs of testbench development is
about 2.5 man-months We have found 9 errors
SYRCoSE'2008 1829-30 May, 2008
L2 cache requirements
Pre Guard Update Post Total Load 4 10 7 4 24 Loadi 2 5 0 2 9 Store 6 13 77 15 111 Cache 5 3 20 6 34 Load (DSP) 1 0 0 1 2 Store (DSP) 1 0 1 0 2 Total 18 31 27 105 181
SYRCoSE'2008 1929-30 May, 2008
L2 cache verification results
Specifications consists 3 KLOC Labor-costs of testbench development is
about 4 man-months We have found 6 errors
SYRCoSE'2008 2029-30 May, 2008
Future work
Generalization for branching pipelines, pipelines with cycles, etc.
Improvement of tool support for specification and tests development
SYRCoSE'2008 2129-30 May, 2008
Contacts
Institute for System Programming of RAShttp://www.ispras.ru
UniTESK Technologyhttp://www.unitesk.com
Alexander Kamkin, Dmitry Vorobyev, Mikhail Chupilko{kamkin, vorobyev, chupilko}@ispras.ru
SYRCoSE'2008 2229-30 May, 2008
Thank You!Questions?