minimizing capacitor bank

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Copyright © FPL and SEL 2013 Minimizing Capacitor Bank Outage Time Through Fault Location Joseph Schaefer Florida Power & Light Company Satish Samineni, Casper Labuschagne, Steven Chase, and Dereje Jada Hawaz Schweitzer Engineering Laboratories, Inc.

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Minimizing Capacitor Bank

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Page 1: Minimizing Capacitor Bank

Copyright © FPL and SEL 2013

Minimizing Capacitor Bank Outage

Time Through Fault Location

Joseph Schaefer Florida Power & Light Company

Satish Samineni, Casper Labuschagne,

Steven Chase, and Dereje Jada Hawaz Schweitzer Engineering Laboratories, Inc.

Page 2: Minimizing Capacitor Bank

Capacitor Bank Configuration

Units in

Series

Units in ParallelCapacitor

Element

Page 3: Minimizing Capacitor Bank
Page 4: Minimizing Capacitor Bank

Problem Statement

• Unit or element failures result in

overvoltages

• Unbalance protection usually trips bank if

overvoltages are too high

• Locating faulty unit is time-consuming

process, resulting in long outage time

Page 5: Minimizing Capacitor Bank

Steps to Put Bank Back in Service

• Take bank out of service

• Isolate and ground bank

• Disconnect each unit

• Measure capacitance across each unit

• Replace faulty unit

• Balance bank

• Energize bank

Page 6: Minimizing Capacitor Bank

Fault Location Technique

• Unbalance protection provides primary

protection against unit or element failures in

capacitor banks

• Unbalance protection methods

♦ Phase voltage

♦ Neutral voltage

♦ Phase current

♦ Neutral current

Page 7: Minimizing Capacitor Bank

Fault Location Technique

• Unbalance protection uses measured

quantities from instrument transformers to

calculate unbalance quantity

• Unbalance quantity is phasor

♦ Magnitude

♦ Phase angle

Page 8: Minimizing Capacitor Bank

Fault Location Technique

Phase and Section With Faulty Unit

Reference

Quantity

Unbalance

Quantity

ɸ°

±15°

Page 9: Minimizing Capacitor Bank

Fault Location Technique

• Supervised by alarm or trip for sensitivity

• ±15° blinder applied for security

• Affected by fusing method

• Immune to inherent unbalance

Page 10: Minimizing Capacitor Bank

Advantages of Proposed Fault

Location Technique

• Minimal outage time – by identifying phase

and section

• Economical – embedded in protection

• Versatile – can be applied to wide range of

bank configurations

Page 11: Minimizing Capacitor Bank

Power System Modeled in RTDS

Load

L1G1 T1

Capacitor

Bank

Page 12: Minimizing Capacitor Bank

Phase Voltage Unbalance Protection Single-Wye Bank

DVp = VBUSp – Kp • VTAPp

Bus

Tap

ABC

VBUSp

VTAPp

Page 13: Minimizing Capacitor Bank

Fault Location Principle

ALARMTRIP

DVpA

–15° Φ 15°

165° Φ –165°

Enable

1

2

Switch at Position a if Bank Is Fuseless

Switch at Position b if Bank Is Fused

2

1Phase p

Top Section

Phase p

Bottom Section

a

b

1

2

a

b

Page 14: Minimizing Capacitor Bank

Capacitor Bank Model

12

3

Single Capacitor Unit

88 kV Bus

Tap

4

4 Top

Bottom

4

Page 15: Minimizing Capacitor Bank

Fault in Phase A and Top Section

Page 16: Minimizing Capacitor Bank

Fault in Phase A and Bottom Section

Page 17: Minimizing Capacitor Bank

Neutral Voltage Unbalance Protection Single-Wye Bank

DVG = VBUSA + VBUSB + VBUSC – 3 • VN –

(K1 • (VBUSB – VN) + K2 • (VBUSC – VN))

BusABC

VBUSp

VN

N

Page 18: Minimizing Capacitor Bank

Fault Location Principle

ALARM

TRIP

DVGA

–15° Φ 15°

165° Φ –165°

Enable

1

2

–135° Φ –105°

45° Φ 75°

105° Φ 135°

–75° Φ –45°

3

4

5

6

2

1Phase A

4

3Phase B

6

5Phase C

Page 19: Minimizing Capacitor Bank

Capacitor Bank Model

230 kV Bus

8

ABC

8N

1

8

Single Capacitor Unit

Page 20: Minimizing Capacitor Bank

Fault in Phase A

Page 21: Minimizing Capacitor Bank

Fault in Phase C

Page 22: Minimizing Capacitor Bank

Neutral Voltage Unbalance Protection Double-Wye Bank

DVG = VNn – Kn • V1BUS

Bus ABC

VBUSp N n

VNn

RightLeft

Page 23: Minimizing Capacitor Bank

Fault Location Principle

ALARM

TRIP

DVGA

–15° Φ 15°

165° Φ –165°

Enable

–135° Φ –105°

45° Φ 75°

105° Φ 135°

–75° Φ –45°

Switch at Position a if Bank Is FuselessSwitch at Position b if Bank Is Fused

1

2 Phase A Left Section

Phase A Right Section

a

b

2

1

a

b

3

4 Phase B Left Section

Phase B Right Section

a

b

4

3

a

b

5

6 Phase C Left Section

Phase C Right Section

a

b

6

5

a

b

1

2

3

4

5

6

Page 24: Minimizing Capacitor Bank

Phase Current Unbalance Protection H-Bridge Bank

60p = IHp – Kp • ICAPp

BusABC

ICAPA ICAPB ICAPC

IHA IHB IHC

Page 25: Minimizing Capacitor Bank

Fault Location Principle

ALARM

TRIP

60pA

–15° Φ 15°

165° Φ –165°

Enable

Switch at Position a if Bank Is FuselessSwitch at Position b if Bank Is Fused

1

2

Phase p

Top Left or

Bottom Right

Section

Phase p

Top Right or

Bottom Left

Section

a

b

2

1

a

b

1

2

Page 26: Minimizing Capacitor Bank

Capacitor Bank Model

345 kV Bus

11

2

A

2

11

Top

Right

Bottom

Right

2 2 1

6

Single Capacitor Unit

Page 27: Minimizing Capacitor Bank

Fault in Top Left Section of Phase A

Page 28: Minimizing Capacitor Bank

Fault in Bottom Left Section of Phase A

Page 29: Minimizing Capacitor Bank

Phase Current

and Voltage

Unbalance

Protection Fault Location

Principle

ALARM

TRIP

60pA

–15° Φ 15°

165° Φ –165°

Enable

1

2

3

4

–15° Φ 15°

165° Φ –165° DVpA

TRIP

Enable

ALARM

Page 30: Minimizing Capacitor Bank

Switch at Position a if Bank Is Fuseless

Switch at Position b if Bank Is Fused

Phase p

Top Left

Section

a

b

a

b

Phase p

Bottom

Right

Section

a

b

a

b

Phase p

Top

Right

Section

a

b

a

b

Phase p

Bottom

Left

Section

a

b

a

b4

3

1

2

3

4

1

2

4

3

2

1

3

4

2

1

Page 31: Minimizing Capacitor Bank

Fault in Top Left Section of Phase A

Page 32: Minimizing Capacitor Bank

Fault in Bottom Right Section of Phase A

Page 33: Minimizing Capacitor Bank

Phase Current Unbalance Protection Double-Wye Bank

BusABC

IPB IPC

ICA ICB ICC

IPA

Page 34: Minimizing Capacitor Bank

Fault Location Principle

ALARM

TRIP

60ФA

–15° Φ 15°

165° Φ –165°

Enable

Switch at Position a if Bank Is FuselessSwitch at Position b if Bank Is Fused

1

2Phase Ф

Left Section

a

b

2

1

a

b

1

2 Phase Ф

Right Section

Page 35: Minimizing Capacitor Bank

Neutral Current Unbalance Protection Double-Wye Bank

BusABC

ICAPA ICAPB ICAPC

IN

Left Right

60N = IN – (K1 • ICAPB + K2 • ICAPC)

Page 36: Minimizing Capacitor Bank

Fault Location Principle

ALARM

TRIP

60NA

–15° Φ 15°

165° Φ –165°

Enable

–135° Φ –105°

45° Φ 75°

105° Φ 135°

–75° Φ –45°

Switch at Position a if Bank Is FuselessSwitch at Position b if Bank Is Fused

1

2 Phase A Left Section

Phase A Right Section

a

b

2

1

a

b

3

4 Phase B Left Section

Phase B Right Section

a

b

4

3

a

b

5

6 Phase C Left Section

Phase C Right Section

a

b

6

5

a

b

1

2

3

4

5

6

Page 37: Minimizing Capacitor Bank

Capacitor Bank Model

15

5

Single Capacitor Unit

33 kV Bus

2

ABC

12Left Right

Page 38: Minimizing Capacitor Bank

Fault in Left Section of Phase B

Page 39: Minimizing Capacitor Bank

Fault in Right Section of Phase C

Page 40: Minimizing Capacitor Bank

Conclusion

• Locating faulty unit is time-consuming

• Proposed fault location technique

♦ Reduces investigating time by 50 to 92%

♦ Minimizes capacitor bank outage time

♦ Is embedded in unbalance protection,

making it economical

♦ Can be applied to any bank configuration

and fusing method

Page 41: Minimizing Capacitor Bank

Conclusion

• Proposed fault location technique

♦ Is not affected by inherent unbalance

♦ Provides advanced alarms for planned

maintenance

♦ Provides fuse savings in externally fused bank

• Using multiple unbalance protection

methods improves protection reliability and

fault location

Page 42: Minimizing Capacitor Bank

Questions?