minimizing plasma-induced charging damage during multi ...€¦ · etch product business group 2...

Etch Product Business Group

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Minimizing Plasma-Induced Charging Damage during Multi-Step Etching of Dual-Damascene Trench and Via Structures with Process Optimization

M. Kutney, S. Ma, D. Buchberger, A. Zhao, G. Delgadino, D. Hoffman, and K. Horioka*Etch Product Business Group, Dielectric Etch Div.*Applied Materials, Inc., Japan

Etch Product Business Group 2

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Introduction and Objectives

Plasma-induced charging effects are– Influenced by plasma stability and uniformity – Strong functions of chamber design and process conditions

The role of plasma stability can be examined using multiple charging-sensitive electrical test structures– EEPROM-based sensors – Metal-gate and poly-gate antenna structures

Identify the risk factors that contribute to charging effects in a very-high-frequency capacitively coupled (VHF CCP) dielectric etcher

Factors related to plasma uniformity and stability were studied in the VHF CCP Centura® Enabler® dielectric-etch chamber – Designed for all-in-one processing of sub-65 nm dual-

damascene structures


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Plasma Charging Damage – Responsible Groups

Four different groups influence the plasma-charging-damage riskUnderstanding all of the group details is challenging

Process•profile•uniformity•selectivity•sequence

Hardware•chamber•power source•cathode•process kit

Device•scaling•integration•reliability•testing method

Layout•design rule•die stepping•alignment mark•edge exclusion

chiller

RF power supply

Throttle valveGate valveTurbo pump

wafer

ESC

Magnet liner

gas distribution plate


External Use

Available Plasma-Damage Characterization ToolsDevice Characterization– 200 mm CHARM®-2 wafers: reprogrammable EEPROM wafer

Measures threshold-voltage shifts following plasma exposure on various antenna EEPROM structuresLocal peak voltages and currents are then determined

– 200 & 300 mm MOS antenna capacitor & transistor wafersWidely accepted in industry for plasma-damage characterizationDifficult and expensive for equipment vendors to acquire, especially 300 mm!!

Surface-Charge Characterization– 200 & 300 mm Contact Potential Difference (CPD)

Measures residue charge before and after plasma exposure on blanket 1kÅ thermal oxide wafersIncompatible for oxide-etching chemistries

Chamber Characterization– Langmuir probe: measures plasma density

Plasma density does not necessarily correlate to real plasma damageCannot be used for every process condition

– VDC cathode: special cathode for VDC uniformity measurementMeasure Vdc at different location and use ∆VDC to relate to damage


External Use

300 mm Enabler® Dielectric Etch Chamber OverviewVery high frequency source (>100MHz) allows very low DC bias etching and ashing capabilities

Controllable plasma density and neutral dissociation for different etching applications

Two additional knobs –CSTU (magnetic field) and NSTU (gas distribution) to tune etch rate and CD uniformities

Very wide, easily tunable and usable operating windows

Ion Energy Distribution control with dual bias RF

~

~

Polymer/plasma confinement

2.0 MHz RF bias power option

Charged species tuning unit (CSTU)

Neutral species tuning unit (NSTU)

Wafer temperature control

>100 MHz VHF source

~

13.56 MHz RF bias power


External Use

Process Risk #1 – Excessive Magnetic-Field Strength

As the CSTU value exceeds the optimum setpoint for a process, the plasma and the etch rate become non-uniform

Too little CSTU Too much CSTU

Center slow ERCenter fast ER

VDC diagnostic cathode

Normalized ratio optimum CSTU

CSTU3.0%3.5%4.0%4.5%5.0%5.5%6.0%6.5%

Nor

mal

ized

VD

C

σ/mean

PuckPedestal

34 VDC probe pins

RF

VDC

Voltagedivider

Low passfilter

0% 500% 1000% 1500% 100%

%

%

%

%

%

%

%

%

%

%

%

-150 -100 -50 0 50 100 150

Radial position (mm)

Too little CSTUNearly optimum CSTU Too much CSTU

Ash

rat

eM

ax a

sh r

ate


External Use

0 2 4 6 8 10 12 14 16.01

.1

1

51020305070809095

99

99.9

99.99

Pre100% CSTU270% CSTU670% CSTU

EEPROM-based voltage response

Perc

entil

e


As the CSTU value exceeds the optimum setpoint for a process, the risk of plasma-induced charging damage grows

200 mm EEPROM-based voltageversus normalized CSTU

Pre 100% 270% 670%

Logic customer’s poly-gate MOS capacitor

voltage-breakdown yield

100% 100% 100% 82%

82%100%100%

Ref: www.charm-2.com


External Use

2

6

10

14

18

0% 500% 1000% 1500%

Normalized ratio

Vol

tage

(V)

0.0

0.5

1.0

1.5

2.0 Current (m

A/cm

2)

Mean & 2σ voltageMaximum current

Fail Fail

optimum CSTUCSTU

100%

3.0%3.5%4.0%4.5%5.0%5.5%6.0%6.5%

Nor

mal

ized

VD

C

σ/mean

2σco

nfiden

ce

band



200 mm EEPROM voltageversus normalized CSTU


voltage-breakdown yield

Pre 100% 270% 670%

100% 100% 100% 82%


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Simplified Antenna MOS Capacitor Structure: SPIDER(SPIDER Systems, Inc)

SPIDER structure

Pre-leakage should be <0.1 nAσ = ±5% accuracyPass criteria = ≥95% at 1 nA

Field thermal oxide 5000 Å

Gate oxide 50 Å

Aluminum antenna electrode 2 µm2

Silicon

Bare metal-gate antenna MOS capacitor structure for plasma-charging-damage evaluation (Ref: IEEE TED, 45(3), p.722, 1998)

Short-flow plasma charging damage test: gate leakage current

– Two terminals: plasma-exposed Al pad & Si substrate backside

– Metal gate is directly on top of gate oxide and has various areas

– Sensitive to plasma charging damage to every part of the process

– Measure leakage before & immediately after plasma exposure

– Cannot detect electron-shading effect


External Use


voltage-breakdown yield(200k:1 antenna ratio)



Pre 100% 270% 670%

100% 100% 100% 82%

300 mm metal-gate leakage currentversus normalized CSTU

N/A

10-13 10-11 10-9 10-7 10-5.01

.1

1

51020305070809095

99

99.9

99.99

Pre 100:1Pre 200k:1100% 100:1100% 200k:1670% 100:1670% 200k:1

Gate-leakage current (A)

Perc

entil

e

Pass Fail

82%100%


External Use

Process Risk #2 – Unstable Plasma during Transitions

Often, many process parameters are changed between steps– For example, bias & source powers, pressure, CSTU, & chemistry– Linearly ramped to new set points or without any control– Simultaneously changed at the beginning of each step with

varying rates Unoptimized transitions increase the plasma-damage risk – Plasma is unstable as it undergoes significant distribution,

density, and energy changesPlasma changes can be represented by plasma conductance– Characterizes the energy allowed to flow through the plasma


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Process Risk #2 – Unstable Plasma during Transitions

Unoptimized transitions have– Significant plasma conductance changes during transitions to

and from the steady-state step-2 etching condition– Plasma conductance before and after step 2 also deviate

Optimized transitions have– Significantly less plasma conductance change– Plasma conductance before and after step 2 deviate less than the

steady-state step-2 value


External Use

10-13 10-11 10-9 10-7 10-5.01

.1

1

51020305070809095

99

99.9

99.99

Pre 200:1Pre 100000:1Post 200:1Post 100000:1

Gate-leakage current (A)

Perc

entil

e

Low-k trench etch with the optimized single-step process

Pass Fail

MOS Gate-Leakage Yields for Unoptimized & Optimized Low-κ Single-Step Etching

300 mm MOS metal-gate-leakage currents verify risk:Unoptimized does not passOptimized does pass

Logic customer’s MOS poly-gate-breakdown-voltage yield also validate:Unoptimized: 88% & 37%Optimized: 100% & 100%

1k:1 100k:1

.01

.1

1

51020305070809095

99

99.9

99.99

Pre 200:1Pre 100000:1Post 200:1Post 100000:1

Perc

entil

e

Low-k trench etch with the unoptimized single-step process

Pass Fail

Optim

ized

pro

cess

Unoptim

ized

pro

cess


External Use

Plasma-Induced Charging-Damage Results for Single-and Multi-Step Processes before and after Optimization

100%100%+0.9 & −0.2−2 & −54 & 5N/AN/AOptimized multiple step

N/AN/A+11.0 & −2.0−6 & −1010 & 14N/AN/AUnoptimized multiple step

100%100%+0.6 & −0.3−2 & −43 & 599.5%97.1%Optimized single step

37%88%+2.0 & −0.9−2 & −66 & 1032.1%79.1%Unoptimized single step

100%100%+0.0 & −0.0~−2 &−2~2 & ~2100%100%Pre-measure control

100%100%|I | < 1 mA/cm2

|Vmean| < 5 V & |V95% | < 10 V

≥95% @1 nA(σ±5%)

Passing specification:

100k:11k:1+Imax &

−Imin

−Vmean & −V95%

+Vmean & +V95%

100k:1200:1

200 & 300 mm poly-gate MOS cap. voltage-

breakdown yield

200 mm EEPROM-based

voltage and current sensors

300 mm metal-gate MOS cap. leakage-current yieldMeasurement:

Data that meet the threshold specifications and customer criteria are bolded,while data that do not meet are not

By optimizing the process, the plasma-damage risk is significantly reduced


External Use

Conclusions

Two risk factors that contribute to plasma-induced-charging sensitivity in a VHF CCP have been identified– Excessive magnetic fields generate a larger charge

distribution that is conducive to charging damageCan be easily avoided with simple process ground rules

– Plasma instability can occur during transitions from one plasma state to another

By continuously controlling and stabilizing the plasma during a transition, charging effects can be reduced

Continuous damage-free etch processes can now be developed– Etching and ashing of complex multi-layer stacks– For example, all-in-one via and trench etching


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minimizing plasma-induced charging damage during multi ...€¦ · etch product business group 2...

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