E. T. TELECOMMUNICATIONS Digital Electronic Systems

2AT4 10/10/2007 Prof. Josep Conesa and F. J. Sànchez

- First minimum control: 30 min Part A; deadline for Part B: October 12th 23:00 - Grades will be available on October, 16th . Questions about the exam: Tuesday 15:00 - 17:00; Thursday 15:00-19:00

VERY IMPORTANT: Draw a general schematic or plan, develop the exercise and justify the results always explaining what are you doing

Minimum 11: Designing an 6-bit comparator using VHDL Develop the VHDL code for the comparator COMP8 sketched in Fig. 1a using an internal architecture consisting in cascadable COMP4’s as shown Fig. 1 having the function table described in Fig. 2.

B[5..0]

A[5..0]

A0

A5

A4

A3

A2

A1

B0

B5

B4

B3

B2

B1

COMP6

COMP6

1

010100

A[5..0]

GT

010000

B[5..0]

0EQ

0LT

B[2..0]

A[2..0]

B[5..3]

A[5..3]GT

EQ

LT

COMP3_1

X[2..0]GT1

Y[2..0] EQ1

LT1

GI1EI1LI1

COMP3_2

Z[2..0]GT2

W[2..0] EQ2

LT2

GI2EI2LI2

Fig. 1 a) Entity for the 8-bit comparator. b) proposed internal architecture

Fig. 2 Function table for the cascadable 3-bit comparator COMP3

Part A 1. Explain the design flow you will follow to produce your circuit 2. Write down the VHDL code (high level or behavioural) directly as a single block as in Fig. 1a planning first

some kind of flux diagram or chart 3. Write down the VHDL code (high level or behavioural) following the architecture described in Fig. 1b (use

signals to interconnect the internal blocks) Part B

4. Create a single-file VHDL project in ispLEVER Classic for a simple programmable logic device (sPLD) GAL22V10 (24 pins)

5. Compile the project and produce the report RPT and de JED files 6. Open a Proteus-VSM project for verifying your design. Compare solutions for both projects (3) and (2).

7. Document your design using the same quality standards and templates for other course exercises. Make a zip file containing the whole project and the document and upload it on the Atenea before the due date.

1 Remember that in an individual exercise these rules are applied: http://epsc.upc.edu/projectes/sed/grups_classe/05-06_Q1/2AT4/COMPORTAMENT_INDIVIDUAL.pdf . Student interview about the submitted work may be also requested

X[2..0] Y[2..0] GI EI LI GT EQ LT X > Y x x x 1 0 0 X is grater than Y X < Y x x x 0 0 1 X is lesser than Y

1 0 0 1 0 0 GI input decides X = Y 0 1 0 0 1 0 EI input decides

0 0 1 0 0 1 LI input decides