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6.004 Computation StructuresSpring 2009
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L03 - CMOS Technolog y 16.004 Spring 2009 2/10/09

CMOS Technology

1. Qualiaive MOSFET model2. CMOS logic gaes3. CMOS design issues

poly meal

pdiffndiff

modified 2/9/09 15:07

NEXT WEEK: TUE: no lecure THU: Lab 1 due! FRI: QUIZ 1!!!


Combinaional Device Wish Lis

Design our sysem o oleraesome amoun of error

Add posiive noise margins VTC: gain>1 & nonlineariy

Los of gain big noise margin Cheap, small Changing volages will require

us o dissipae power, bu if novolages are changing, wed like

zero power dissipaion Wan o build devices wih

useful funcionaliy (wha sorof operaions do we wan operform?)

VOL

VIL VIH

VOH

Vin

VouVin

Vou


W

L

MOSFETS: Gain & non-lineariygae

drain

source

bulk

Iner-layer SiO2 insulaion

Polysilicon wire

Doped (p-ype or n-ype) silicon subsrae

Very hin (

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CMOS complemensWha a niceVOHyou have...

Thanks. I runsin he family...

conducs when VGS is high conducs when VGS is low

conducs when A is highand B is high: A.B

A

B

A B

conducs when A is lowor B is low: A+B = A.B

conducs when A is highor B is high: A+B

A

BA B

conducs when A is lowand B is low: A.B = A+B


A pop quiz!

A

B

Wha funcion does

his gae compue?

A B C

0 00 11 01 1

11 NAND10

16

82

Curren echnology: = 45nm

COST:$3500 per 300mm wafer300mm round wafer = (150e-3)2 = .07m2NAND gae = (82)(16)(45e-9)2=2.66e-12m22.6e10 NAND gaes/wafer (= 100 billion FETS!)marginal cos of NAND gae: 132n$

L03 - CMOS Technology 116.004 Spring 2009 2/10/09

Heres anoher

Wha funcion doeshis gae compue?

A B C

0 00 11 01 1

A

B

10 NOR00


General CMOS gae recipe

Sep 1. Figure ou pulldown nework hadoes wha you wan, e.g.,

(Wha combinaion of inpusgeneraes a low oupu)

A

B C

Sep 2. Walk he hierarchy replacing nfeswih pfes, series subnes wih parallelsubnes, and parallel subnes wih seriessubnes

AB

C

So, whas he bigdeal?

Sep 3. Combine pfe pullup neworkfrom Sep 2 wih nfe pulldownnework from Sep 1 o form fully-

complemenary CMOS gae.

AB

C

A

B C

F= A (B +C)

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A Quick Review A combinaional deviceis a circui elemen ha has

one or more digial inpus one or more digial oupus a funcional specificaionha deails he value of each oupu for

every possible combinaion of valid inpu values

a iming specificaionconsising (a minimum) of an upper boundPD on he required ime for he device o compue he specifiedoupu values from an arbirary se of sable, valid inpu values

Saicdiscipline

If C is 1 hen copy A o Y,oherwise copy B o Y

I will generae a validoupu in no more han

2 weeks aferseeing valid inpus

inpu A

inpu B

inpu C

oupu Y


Big Issue 1: Wires

Today (i.e., 100nm):RC 50ps/mmImplies > 1 ns o raverse a 20mm x 20mm chipThis is a long ime in a 2GHz processor

VIN

RVou VIN

C


Due o unavoidable delays

Propagaion delay (PD):An UPPER BOUND on he delay from valid inpuso valid oupus.

GOAL:

minimizepropagaiondelay!

ISSUE:keepCapacianceslow andransisors

fas

VOUT < PD< PD

VIN

VOL

VOH

VIL

VIH

time constant

= RPD

CL

time constant

= RPUCLL03 - CMOS Technolog y 166.004 Spring 2009 2/10/09

Conaminaion Delayan opional, addiional iming spec

INVALID inpus ake ime o propagae, oo...

CONTAMINATION DELAY, CDA LOWER BOUND on he delay from any invalid inpu o an invalid oupu

VOUT > CD> CD

VIN

VOL

VOH

VIL

VIH Do we really need CD?

Usually no ill beimporan when wedesign circuis wihregisers (comingsoon!)

If CD is no specified,safe o assume is 0.

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The Combinaional Conrac

A BA B

0 11 0

PD propagaion delay

CD conaminaion delay

A

B

Mus be ___________

Mus be ___________

Noe:1. No Promisesduring2. Defaul (conservaive) spec: CD = 0

< PD

> CD


Acyclic Combinaional Circuis

If NAND gaes have a PD = 4nS and CD = 1nS

B

C

A

Y

PD = _______ nS

CD = _______ nS

12

2

PD is he maximumcumulaivepropagaion delay over all pahsfrom inpus o oupus

CD is he minimumcumulaiveconaminaion delay over allpahs from inpus o oupus


Oh yeah one las issue

Recall he rules for combinaional devices:

Oupu guaraneed o be valid when all inpus have beenvalid for a leas PD, and, oupus may become invalid noearlier han CD afer an inpu changes!

A

B

Z

PD

CD

AZB

001

1

010

1

100

0

A B ZNOR:

A

B

Z

PD

CD

Many gae implemenaions--e.g., CMOSadhere o even igher resricions.


Wha happens in his case?

A

B

Z

PD

CD

Inpu A alone issufficien o

deermine heoupu

A

B

Z

A

B

Z

0X1

01X

100

A B Z

0011

0101

1000

A B ZNOR: Lenien

NOR:

LENIENTCombinaional Device:Oupu guaraneed o be valid when any combinaion of inpussufficien o deermine oupu value has been valid for a leas PD.Toleraes ransiions -- and invalid levels -- on irrelevan inpus!

CMOS NOR:

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Big Issue 2: Power

Energy dissipaed = C VDD2

per cyclePower consumed = f n C VDD2 per chip

where f = frequency of charge/discharge

n = number of gaes /chip

VIN

VDD

C

VOUT

VIN

moves fromL o H o L

VOUT

moves fromH o L o H

C discharges andhen recharges


Unforunaely

Modern chips (UlraSparc III, Power4, Ianium 2)dissipae from 80W o 150W wih a Vdd 1.2V

(Power supply curren is 100 Amps)

Hey: could weSomehow recycle

he charge?

Worse ye

Litle room lef o reduce VddnC and f coninue o grow

Cooling challenge is like making he filamen of a100W incandescen lamp cool o he ouch!


MUST compuaion consume energy?(a iny digression)

A B C

0 00 11 01 1

1110

How energy-efficien can we make a gae? Iseems ha swiching he inpu o a NAND gaewill always dissipae some energy

Landauers Principle (1961): discardinginformaionis wha coss energy!

Bennet (1973): Use reversiblelogic gaes, no NAND, and heres no lowerbound o energy use!

NAND GATE:2 bis 1 bi

(informaion

Loss!)

A B

0 00 11 01 1

0011

P Q

0110

FEYNMANGATE:

2 bis 2 bis

(informaionPreserving!)

Bennet, Fredkin, Feynman, ohers: Compuersysems consruced from info-preserving elemens.

Theory: NOlower bound on energy use!

Pracice: Research fronier (qubis, ec.)

htp://www.research.ibm.com/journal/rd/441/landauerii.pdf

The fundamenal physical limis of compuaion, Bennet & Landauer, Scienific American. Vol. 253, pp. 48-56. July 1985

htp://www.research.ibm.com/journal/rd/176/ibmrd1706G.pdf


Summary CMOS

Only use NFETs in pulldowns, PFETs in pullups mosfes behave asvolage-conrolled swiches

Series/parallel Pullup and pulldown swich circuis arecomplemenary

CMOS gaes are naurally invering (rising inpu ransiion can onlycause falling oupu ransiion, and vice versa). Perfec VTC (high gain, VOH = VDD, VOL = GND) means large noise

margins and no saic power dissipaion.

Timing specs PD: upper bound on ime from valid inpus o valid oupus CD: lower bound on ime from invalid inpus o invalid oupus If no specified, assume CD = 0

Lenien gaes: oupu unaffeced by some inpu ransiions Nex ime: logic simplificaion, oher canonical forms

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