mitsubishi power module

Sep.1998

6.0 Introduction to IntelligentPower Modules (IPM)

Mitsubishi Intelligent Power Mod-ules (IPMs) are advanced hybridpower devices that combine highspeed, low loss IGBTs with opti-mized gate drive and protection cir-cuitry. Highly effective over-currentand short-circuit protection is real-ized through the use of advancedcurrent sense IGBT chips that al-low continuous monitoring of powerdevice current. System reliability isfurther enhanced by the IPM’s inte-grated over temperature and undervoltage lock out protection. Com-pact, automatically assembled In-telligent Power Modules are de-signed to reduce system size, cost,and time to market. MitsubishiElectric introduced the first full lineof Intelligent Power Modules in No-vember, 1991. Continuous im-provements in power chip, packag-ing, and control circuit technologyhave lead to the IPM lineup shownin Table 6.1.

6.0.1 Third Generation Intelli-gent Power Modules

Mitsubishi third generation intelli-gent power module family shown inTable 6.1 represents the industriesmost complete line of IPMs. Sincetheir original introduction in 1993the series has been expanded toinclude 36 types with ratings rang-ing from 10A 600V to 800A 1200V.The power semiconductors used inthese modules are based on thefield proven H-Series IGBT and di-ode processes. In Table 6.1 thethird generation family has been di-vided into two groups, the “LowProfile Series” and “High PowerSeries” based on the packagingtechnology that is used. The third

generation IPM has been optimizedfor minimum switching losses in or-der to meet industry demands foracoustically noiseless inverterswith carrier frequencies up to20kHz. The built in gate drive andprotection has been carefully de-signed to minimize the componentsrequired for the user supplied inter-face circuit.

6.0.2 V-Series High Power IPMs

The V-Series IPM was developedin order to address newly emergingindustry requirements for higher re-liability, lower cost and reducedEMI. By utilizing the low inductancepackaging technology developed

for the U-Series IGBT module (de-scribed in Section 4.1.5) combinedwith an advanced super soft free-wheel diode and optimized gatedrive and protection circuits the V-Series IPM family achieves im-proved performance at reducedcost. The detailed descriptions ofIPM operation and interface re-quirements presented in Sections6.1 through 6.8 apply to V-Seriesas well as third generation IPMs.The only exception being that V-Series IPMs have a unified shortcircuit protection function that takesthe place of the separate short cir-cuit and over current functions de-scribed in Sections 6.4.4 and 6.4.5.The unified protection was made

Third Generation Low Profile Series - 600V

PM10CSJ060 10 Six IGBTs




PM50RSK060 50 Six IGBTs + Brake ckt.


Third Generation Low Profile Series - 1200V

PM10CZF120 10 Six IGBTs

PM10RSH120 10 Six IGBTs + Brake ckt.

PM15CZF120 15 Six IGBTs

PM15RSH120 15 Six IGBTs + Brake ckt.


Third Generation High Power Series - 600V

PM75RSA060 75 Six IGBTs + Brake ckt.

PM100CSA060 100 Six IGBTs






PM200DSA060 200 Two IGBTs: Half Bridge


PM400DAS060 400 Two IGBTs: Half Bridge


PM800HSA060 800 One IGBT

Third Generation High Power Series - 1200V

PM25RSB120 25 Six IGBTs + Brake ckt.









PM400HSA120 400 Two IGBTs: Half Bridge



V-Series High Power - 600V

PM75RVA060 75 Six IGBTs + Brake ckt.

PM100CVA060 100 Six IGBTs




PM400DVA060 400 Two IGBTs: Half Bridge


V-Series High Power - 1200V

PM50RVA120 50 Six IGBTs + Brake ckt.






Type Number Amps Power Circuit Type Number Amps Power Circuit

Table 6.1 Mitsubishi Intelligent Power Modules

MITSUBISHI SEMICONDUCTORS POWER MODULES MOS

USING INTELLIGENT POWER MODULES

Sep.1998

possible by an advanced RTC(Real Time Control) current clamp-ing circuit that eliminates the needfor the over current protection func-tion. In V-Series IPMs a unifiedshort circuit protection with a delayto avoid unwanted operation re-places the over current and shortcircuit modes of the third genera-tion devices.

6.1 Structure of IntelligentPower Modules

Mitsubishi Intelligent Power Mod-ules utilize many of the same fieldproven module packaging tech-nologies used in Mitsubishi IGBTmodules. Cost effective implemen-tation of the built in gate drive andprotection circuits over a widerange of current ratings wasachieved using two different pack-aging techniques. Low power de-vices use a multilayer epoxy isola-tion system while medium and highpower devices use ceramic isola-tion. These packaging technologiesare described in more detail in Sec-tions 6.1.1 and 6.1.2. IPM areavailable in four power circuit con-figurations, single (H), dual (D), sixpack (C), and seven pack (R).Table 6.1 indicates the power cir-cuit of each IPM and Figure 6.1shows the power circuit configura-tions.

6.1.1 Multilayer Epoxy Construc-tion

Low power IPM (10-50A, 600V and10-15A, 1200V) use a multilayerepoxy based isolation system. Inthis system, alternate layers of cop-per and epoxy are used to create ashielded printed circuit directly onthe aluminum base plate. Power

chips and gate control circuit com-ponents are soldered directly to thesubstrate eliminating the need for aseparate printed circuit board andceramic isolation materials. Mod-ules constructed using this tech-nique are easily identified by their

extremely low profile packages.This package design is ideallysuited for consumer and industrialapplications where low cost andcompact size are important.Figure 6.2 shows a cross sectionof this type of IPM package. Figure6.3 is a PM20CSJ060 20A, 600VIPM.

P

U V W

C2E1

C1

E2

E

C

N

TYPE C

TYPE D TYPE H

P

N

U

TYPE R

V WB

Figure 6.2 Multi-Layer EpoxyConstruction

Figure 6.1 Power CircuitConfiguration

Figure 6.3 PM20CSJ060

1. 2. 3. 4. 5. 6. 7. 8. 9.

10. 11.

Case Epoxy Resin Input Signal Terminal SMT Resistor Gate Control IC SMT Capacitor IGBT Chip Free-wheel Diode Chip Bond Wire Copper Block Baseplate with Epoxy Based Isolation

111098

67

12 3

45



Sep.1998

6.1.2 Ceramic Isolation Con-struction

Higher power IPMs are constructedusing ceramic isolation material. Adirect bond copper process inwhich copper patterns are bondeddirectly to the ceramic substratewithout the use of solder is used inthese modules. This substrate pro-vides the improved thermal charac-teristics and greater current carry-ing capabilities that are needed inthese higher power devices. Gatedrive and control circuits are con-tained on a separate PCB mounteddirectly above the power devices.The PCB is a multilayer construc-tion with special shield layers forEMI noise immunity. Figure 6.4shows the structure of a ceramicisolated Intelligent Power Module.Figure 6.5 is a PM75RSA060 75 A,600V IPM.

Figure 6.4 Ceramic Isolation Construction

Figure 6.5 PM75RSA060

SILICON CHIP

DBC PLATE

BASE PLATE

SILICON GEL

CASE

MAIN TERMINAL

EPOXY RESIN

GUIDE PIN

INPUT SIGNAL TERMINAL

INTERCONNECT TERMINALELECTRODE

ALUMINUM WIRE

SHIELD LAYER

RESISTOR

CONTROL BOARD PCB

SHIELD LAYER

SIGNAL TRACE



Sep.1998

6.1.3 V-Series IPM Construction

V-Series IPMs are similar to the ce-ramic isolated types describedin Section 6.1.2 except that an in-sert molded case similar to theU-Series IGBT is used. Like theU-Series IGBT described in Sec-tion 4.1.5, the V-Series IPMhas lower internal inductance andimproved power cycle durability.Figure 6.6 is a cross section draw-ing showing the construction of theV-Series IPM. The insert moldedcase makes the V-Series IPM iseasier to manufacture and lower incost. Figure 6.7 shows aPM150CVA120 which is a 150A1200V V-Series IPM.

6.1.4 Advantages of IntelligentPower Module

IPM (Intelligent Power Module)products were designed and devel-oped to provide advantages toCustomers by reducing design, de-velopment, and manufacturing

costs as well as providing improve-ment in system performance andreliability over conventional IGBTs.Design and development effort issimplified and successful drive co-ordination is assured by the inte-gration of the drive and protectioncircuitry directly into the IPM. Re-duced time to market is only one ofthe additional benefits of using anIPM. Others include increased sys-tem reliability through automatedIPM assembly and test and reduc-tion in the number of componentsthat must be purchased, stored,and assembled. Often the systemsize can be reduced throughsmaller heatsink requirements as aresult of lower on-state and switch-ing losses. All IPMs use the samestandardized gate control interfacewith logic level control circuits al-lowing extension of the product linewithout additional drive circuit de-sign. Finally, the ability of the IPMto self protect in fault situations re-duce the chance of device destruc-tion during development testing aswell as in field stress situations.

6.2 IPM Ratings and Characteris-tics

IPM datasheets are divided intothree sections:

• Maximum Ratings• Characteristics (electrical,

thermal, mechanical)• Recommended Operating

Conditions

The limits given as maximum ratingmust not be exceeded under anycircumstances, otherwise destruc-tion of the IPM may result.

Key parameters needed for systemdesign are indicated as electrical,thermal, and mechanical character-istics.

The given recommended operatingconditions and application circuitsshould be considered as a prefer-able design guideline fitting mostapplications.

POWER TERMINALS

SILICONE GEL

COVERINSERT MOLD CASE

DBC AIN CERAMIC SUBSTRATE

SILICON CHIPS BASE PLATE

PRINTED CIRCUIT BOARD

ALUMINUM BOND WIRES

SIGNAL TERMINALS

Figure 6.6 V-Series IPM Construction Figure 6.7 PM150CVA120



Sep.1998

6.2.1 Maximum Ratings Symbol Parameter Definition

Inverter Part

VCC Supply Voltage Maximum DC bus voltage applied between P-N

VCES Collector-Emitter Voltage Maximum off-state collector-emitter voltage at applied control input off signal

±IC Collector-Current Maximum DC collector and FWDi current @ Tj ≤ 150°C

±ICP Collector-Current (peak) Maximum peak collector and FWDi current @ Tj ≤ 150°C PC Collector Dissipation Maximum power dissipation per IGBT switch at Tj = 25°C Tj Junction Temperature Range of IGBT junction temperature during operation

Brake Part

VR(DC) FWDi Reverse Voltage Maximum reverse voltage of FWDi

IF FWDi Forward Current Maximum FWDi DC current at Tj ≤ 150°C

Control Part

VD Supply Voltage Maximum control supply voltage

VCIN Input Voltage Maximum voltage between input (I) and ground (C) pins

VFO Fault Output Supply Voltage Maximum voltage between fault output (FO) and ground (C) pins

IFO Fault Output Current Maximum sink current of fault output (FO) pin

Total System

VCC(prot) Supply Voltage Protected Maximum DC bus voltage applied between P-N with guaranteed OC and SC protection

by OC & SC

TC Module Case Operating Range of allowable case temperature at specified reference point during operation

Temperature

Tstg Storage Temperature Range of allowable ambient temperature without voltage or current

Viso Isolation Voltage Maximum isolation voltage (AC 60Hz 1 min.) between baseplate and module terminals

(all main and signal terminals externally shorted together)

6.2.2 Thermal Resistance Symbol Parameter Definition

Rth(j-c) Junction to Case Maximum value of thermal resistance between junction and case per switch

Thermal Resistance

Rth(c-f) Contact Thermal Maximum value of thermal resistance between case and fin (heatsink) per IGBT/FWDi pair

Resistance with thermal grease applied according to mounting recommendations

6.2.3 Electrical Characteristics Symbol Parameter Definition

Inverter and Brake Part

VCE(sat) Collector-Emitter IGBT on-state voltage at rated collector current under specified conditions

Saturation Voltage

VEC FWDi Forward Voltage FWDi forward voltage at rated current under specified conditions

ton Turn-On Time

trr FWDi Recovery Time Inductive load switching times under rated conditions

tc(on) Turn-On Crossover Time (See Figure 6.10)

toff Turn-Off Time

tc(off) Turn-Off Crossover Time

ICES Collector-Emitter Cutoff Collector-Emitter current in off-state at VCE = VCES under specified conditions



Sep.1998

The following test circuits are usedto evaluate the IPM characteristics.

1. VCE(sat) and VEC

To ensure specified junctiontemperature, Tj, measurementsof VCE(sat) and VEC must beperformed as low duty factorpulsed tests. (See Figures 6.8and 6.9)

6.2.3 Electrical Characteristics (continued) Symbol Parameter Definition

Control Part

VD Supply Voltage Range of allowable control supply voltage in switching operation

ID Circuit Current Control supply current in stand-by mode

VCIN(on) Input ON-Voltage A voltage applied between input (I) and ground (C) pins less than this value will turn on the IPM

VCIN(off) Input OFF-Voltage A voltage applied between input (I) and ground (C) pins higher than this value will turn off the IPM

fPWM PWM Input Frequency Range of PWM frequency for VVVF inverter operations

tdead Arm Shoot Through Time delay required between high and low side input off/on signals to prevent an

Blocking Time arm shoot through

OC Over-Current Trip Level Collector that will activate the over-current protection

SC Short-Circuit Trip Level Collector current that will activate the short-circuit protection

toff(OC) Over-Current Delay Time Time delay after collector current exceeds OC trip level until OC protection is activated

OT Over-Temperature Trip Level Baseplate temperature that will activate the over-temperature protection

OTr Over-Temperature Temperature that the baseplate must fall below to reset an over-temperature fault

Reset Level

UV Control Supply Control supply voltage below this value will activate the undervoltage protection

Undervoltage Trip Level

UVr Control Supply Control supply voltage that must exceed to reset an undervoltage fault

Undervoltage Reset Level

IFO(H) Fault Output Inactive Current Fault output sink current when no fault has occurred

IFO(L) Fault Output Active Current Fault Output sink current when a fault has occurred

tFO Fault Output Pulsed Width Duration of the generated fault output pulse

VSXR SXR Terminal Output Voltage Regulated power supply voltage on SXR terminal for driving the external optocoupler

6.2.4 Recommended Operation Conditions Symbol Parameter Definition

VCC Main Supply Voltage Recommended DC bus voltage range

VD Control Supply Voltage Recommended control supply voltage range

VCIN(on) Input ON-Voltage Recommended input voltage range to turn on the IPM

VCIN(off) Input OFF-Voltage Recommended input voltage range to turn off the IPM

fPWM PWM Input Frequency Recommended range of PWM carrier frequency using the recommended application circuit

tDEAD Arm Shoot Through Recommended time delay between high and low side off/on signals to the optocouplers

Blocking Time using the recommended application circuit

VX1

SXR

CX1

VXC

E1(E2)

C1(C2)

VD V IC

VX1

SXR

CX1

VXC

E1(E2)

C1(C2)

VD V IC

Figure 6.8 V CE(sat) Test Figure 6.9 V EC Test

6.2.5 Test Circuits and Conditions



Sep.1998

2. Half-Bridge Test Circuit andSwitching Time Definitions.

Figure 6.10 shows the stan-dard half-bridge test circuit andswitching waveforms. Switch-ing times and FWDi recoverycharacteristics are defined asshown in this figure.

3. Overcurrent andShort-Circuit Test

Itrip levels and timing specifica-tions in short circuit andovercurrent are defined asshown in Figure 6.11. By usinga fixed load resistance the sup-ply voltage, VCC, is graduallyincreased until OC and SC triplevels are reached.

Precautions:A. Before applying any main bus

voltage, VCC, the input termi-nals should be pulled up by re-sistors to their correspondingcontrol supply (or SXR) pin,each input signal should bekept in OFF state, and the con-trol supply should be provided.After this, the specified ON andOFF level for each input signalshould be applied. The controlsupply should also be appliedto the non-operating arm of themodule under test and inputsof these arms should be keptto their OFF state.

B. When performing OC and SCtests the applied voltage, VCC,must be less than VCC(prot)and the turn-off surge voltagespike must not be allowed torise above the VCES rating ofthe device. (These tests mustnot be attempted using acurve tracer.)

+

IC

INTEGRATED GATE

CONTROL CIRCUIT

INTEGRATED GATE

CONTROL CIRCUIT

+

+

td (on)

ICIN

(t on = td (on) + tr)

tr td (off)

(t off = td (off) + tf)

tf

tc (off)tc (on)

10%

90%

10%

90%

IC

trr

IrrVCE

IC

VCE

OFF SIGNAL

ON PULSE

VCC

VD

VD

Figure 6.10 Half-Bridge Test Circuit and Switching Time Definitions

ON PULSE

SC

OC

INPUT SIGNAL

NORMAL OPERATION

OVER CURRENT

SHORT CIRCUIT

VCON

PULSE

R*

R IS SIZED TO CAUSE SC AND OC CONDITIONS

*

VCC+

toff (OC)

IC

INTEGRATED GATE

CONTROL CIRCUIT

SC

OC

SC

OC

IC

IC

IC

Figure 6.11 Over-Current and Short-Circuit Test Circuit



Sep.1998

6.3 Area of Safe Operation forIntelligent Power Modules

The IPMs built-in gate drive andprotection circuits protect it frommany of the operating modes thatwould violate the Safe OperationArea (SOA) of non-intelligent IGBTmodules. A conventional SOA defi-nition that characterizes all pos-sible combinations of voltage, cur-rent, and time that would causepower device failure is not re-quired. In order to define the SOAfor IPMs, the power device capabil-ity and control circuit operationmust both be considered. The re-sulting easy to use short circuit andswitching SOA definitions for Intelli-gent Power Modules are summa-rizedin this section.

6.3.1 Switching SOA

Switching or turn-off SOA is nor-mally defined in terms of the maxi-mum allowable simultaneous volt-age and current during repetitiveturn-off switching operations. In thecase of the IPM the built-in gatedrive eliminates many of the dan-gerous combinations of voltageand current that are caused by im-proper gate drive. In addition, themaximum operating current is lim-ited by the over current protectioncircuit. Given these constraints theswitching SOA can be defined us-ing the waveform shown in Figure6.12. This waveform shows that theIPM will operate safely as long asthe DC bus voltage is below thedata sheet VCC(prot) specification,the turn-off transient voltage acrossC-E terminals of each IPM switch is

maintained below the VCES specifi-cation, Tj is less than 125°C, andthe control power supply voltage isbetween 13.5V and 16.5V. In thiswaveform IOC is the maximum cur-rent that the IPM will allow withoutcausing an Over Current (OC) faultto occur. In other words, it is justbelow the OC trip level. This wave-form defines the worst case forhard turn-off operations becausethe IPM will initiate a controlledslow shutdown for currents higherthan the OCtrip level.

6.3.2 Short Circuit SOA

The waveform in Figure 6.13 de-picts typical short circuit operation.The standard test condition uses aminimum impedance short circuitwhich causes the maximum shortcircuit current to flow in the device.In this test, the short circuit current(ISC) is limited only by the devicecharacteristics. The IPM is guaran-teed to survive non-repetitive shortcircuit and over current conditionsas long as the initial DC bus volt-age is less than the VCC(prot)specification, all transient voltagesacross C-E terminals of each IPMswitch are maintained less than theVCES specification, Tj is less than125°C, and the control supply volt-age is between 13.5V and 16.5V.

The waveform shown depicts thecontrolled slow shutdown that isused by the IPM in order to helpminimize transient voltages.

Note:The condition VCE ≤ VCES has tobe carefully checked for each IPMswitch. For easing the design an-other rating is given on the datasheets, VCC(surge), i.e., the maxi-mum allowable switching surgevoltage applied between the P andN terminals.

6.3.3 Active Region SOA

Like most IGBTs, the IGBTs used inthe IPM are not suitable for linearor active region operation. Nor-mally device capabilities in thismode of operation are described interms of FBSOA (Forward BiasedSafe Operating Area). The IPM’sinternal gate drive forces the IGBTto operate with a gate voltage of ei-ther zero for the off state or thecontrol supply voltage (VD) for theon state. The IPMs under-voltagelock out prevents any possibility ofactive or linear operation by auto-matically turning the power deviceoff if VD drops to a levelthat could cause desaturation ofthe IGBT.

Figure 6.13 Short-CircuitOperationFigure 6.12 Turn-Off Waveform

IOC ≤VCES ≤VCC(PROT)

toff(OC)

≤VCES

≤VCES

≤VCC(PROT)

ISC



Sep.1998

6.4. IPM Self Protection

6.4.1 Self Protection Features

IPM (Intelligent Power Modules)have sophisticated built-in protec-tion circuits that prevent the powerdevices from being damagedshould the system malfunction orbe over stressed. Our design andapplications engineers have devel-oped fault detection and shut downschemes that allow maximum utili-zation of power device capabilitywithout compromising reliability.Control supply under-voltage, over-temperature, over-current, andshort-circuit protection are all pro-vided by the IPM's internal gatecontrol circuits. A fault output signalis provided to alert the system con-troller if any of the protection cir-cuits are activated. Figure 6.14 is ablock diagram showing the IPMsinternally integrated functions. Thisdiagram also shows the isolated in-terface circuits and control powersupply that must be provided bythe user. The internal gate controlcircuit requires only a simple +15VDC supply. Specially designed gatedrive circuits eliminate the need fora negative supply to off bias theIGBT. The IPM control input is de-signed to interface withoptocoupled transistors with a mini-mum of external components. The

operation and timing of each pro-tection feature is described in Sec-tions 6.4.2 through 6.4.5.

6.4.2 Control SupplyUnder-Voltage Lock-Out

The Intelligent Power Module's in-ternal control circuits operate froman isolated 15V DC supply. If, forany reason, the voltage of this sup-ply drops below the specified un-der-voltage trip level (UVt), thepower devices will be turned offand a fault signal will be generated.Small glitches less than the speci-fied tdUV in length will not affect theoperation of the control circuitryand will be ignored by the under-voltage protection circuit. In orderfor normal operation to resume, thesupply voltage must exceed the un-der-voltage reset level (UVr). Op-eration of the under-voltage protec-tion circuit will also occur duringpower up and power down of thecontrol supply. This operation isnormal and the system controller'sprogram should take the fault out-put delay (tfo) into account. Figure6.15 is a timing diagram showingthe operation of the under-voltagelock-out protection circuit. In thisdiagram an active low input signalis applied to the input pin of theIPM by the system controller. Theeffects of control supply power up,

power down and failure on thepower device gate drive and faultoutput are shown.

Caution:1. Application of the main bus

voltage at a rate greater than20V/µs before the controlpower supply is on and stabi-lized may cause destruction ofthe power devices.

2. Voltage ripple on the controlpower supply with dv/dt in ex-cess of 5V/µs may cause afalse trip of the UV lock-out.

6.4.3 Over-TemperatureProtection

The Intelligent Power Module has atemperature sensor mounted onthe isolating base plate near theIGBT chips. If the temperature ofthe base plate exceeds the over-temperature trip level (OT) theIPMs internal control circuit willprotect the power devices by dis-abling the gate drive and ignoringthe control input signal until theover temperature condition hassubsided. In six and seven packmodules all three low side deviceswill be turned off and a low sidefault signal will be generated. Highside switches are unaffected andcan still be turned on and off by thesystem controller. Similarly, in dualtype modules only the low side de-vice is disabled. The fault outputwill remain as long as the over-temperature condition exists. Whenthe temperature falls below theover-temperature reset level (OTr),and the control input is high (off-state) the power device will be en-abled and normal operation will re-sume at the next low (on) input sig-nal. Figure 6.16 is a timing diagramshowing the operation of the over-

GATE CONTROL CIRCUIT

GATE DRIVE OVER TEMP UV LOCK-OUT OVER CURRENT SHORT CIRCUIT

ISOLATED POWER SUPPLY

ISOLATING INTERFACE

CIRCUIT

ISOLATING INTERFACE

CIRCUIT

CURRENT SENSE IGBT

TEMPERATURE SENSOR

SENSE CURRENT

INTELLIGENT POWER MODULE

INPUT SIGNAL

FAULT OUTPUT

COLLECTOR

EMITTER

Figure 6.14 IPM Functional Diagram



Sep.1998

temperature protection circuit.The over temperature function pro-vides effective protection againstoverloads and cooling system fail-ures in most applications. However,it does not guarantee that the maxi-mum junction temperature rating ofthe IGBT chip will never be ex-ceeded. In cases of abnormallyhigh losses such as failure of thesystem controller to properly regu-late current or excessively highswitching frequency it is possiblefor IGBT chip to exceed Tj(max) be-fore the base plate reaches the OTtrip level.

Caution:Tripping of the over-temperatureprotection is an indication of stress-ful operation. Repetitive trippingshould be avoided.

6.4.4 Over-Current Protection

The IPM uses current sense IGBTchips to continuously monitorpower device current. If the currentthough the Intelligent Power Mod-ule exceeds the specifiedovercurrent trip level (OC) for a pe-riod longer than toff(OC) the IPMsinternal control circuit will protectthe power device by disabling thegate drive and generating a faultoutput signal. The timing of theover-current protection is shown inFigure 6.17. The toff(OC) delay isimplemented in order to avoid trip-ping of the OC protection on shortpulses of current above the OClevel that are not dangerous for thepower device. When an over-cur-

rent is detected a controlled shut-down is initiated and a fault outputis generated. The controlled shut-down lowers the turn-off di/dt whichhelps to control transient voltagesthat can occur duringshut down from high fault currents.Most Intelligent Modules use thetwo step shutdown depicted in Fig-ure 6.17. In the two step shutdown,the gate voltage is reduced to an

intermediate voltage causing thecurrent through the device to dropslowly to a low level. Then, about5µs later, the gate voltage is re-duced to zero completing the shutdown. Some of the large six andseven pack IPMs use an activeramp of gate voltage to achieve thedesired reduction in turn off di/dtunder high fault currents. The oscil-lographs in Figure 6.18 illustrate

Figure 6.15 Operation of Under-Voltage Lockout

INPUT SIGNAL

BASE PLATE TEMPERATURE

(Tb)

FAULT OUTPUT CURRENT

(IFO)

INTERNAL GATE

VOLTAGE VGE

OTOTr

Figure 6.16 Operation of Over-Temperature

INPUT SIGNAL

CONTROL SUPPLY

VOLTAGE

FAULT OUTPUT

CURRENT (IFO)

INTERNAL GATE

VOLTAGE VGE

CONTROL SUPPLY ON SHORT GLITCH

IGNORED

POWER SUPPLY FAULT AND RECOVERY

CONTROL SUPPLY OFF

UVrUVt

tFOtdUV tFO

tdUV



Sep.1998

the effect of the controlled shut-down (for obtaining the oscillo-graph in “A”the internal soft shutdown was in-tentionally deactivated). The IPMuses actual device current mea-surement to detect all types of over

current conditions. Even resistiveand inductive shorts to ground thatare often missed by conventionaldesaturation and bus current sens-ing protection schemes will be de-tected by the IPMs current senseIGBTs.

Note:V-Series IPMs do not have anover- current protection function.Instead a unified short circuit pro-tection function that has a delaylike the over current protection de-scribed in this section is used.

NORMAL OPERATION FWD RECOVERY CURRENT

IGNORED BY OC PROTECTION

OVER CURRENT FAULT AND RECOVERY

SHORT CIRCUIT FAULT AND RECOVERY

NORMAL OPERATION

tFO tFO

tholdtholdtoff (OC)

INPUT SIGNAL

INTERNAL GATE

VOLTAGE (VGE)

SHORT CIRCUIT TRIP LEVEL

OVER CIRCUIT TRIP LEVEL

COLLECTOR CURRENT

IFO

FAULT OUTPUT CURRENT

Figure 6.17 Operation of Over-Current and Short-Circuit Protection

OC PROTECTION WITHOUT SOFT SHUTDOWN

VCE (surge)

OC PROTECTION WITH SOFT SHUTDOWN

IC VCEIC VCE

VCE (surge)

Figure 6.18 OC Operation of PM200DSA060 (I C: 100A/div; 100V/div; t: 1 µs/div)



Sep.1998

6.4.5 Short Circuit Protection

If a load short circuit occurs or thesystem controller malfunctionscausing a shoot through, the IPMsbuilt in short circuit protection willprevent the IGBTs from being dam-aged. When the current, throughthe IGBT exceeds the short circuittrip level (SC), an immediate con-trolled shutdown is initiated and afault output is generated. The samecontrolled shutdown techniquesused in the over current protectionare used to help control transientvoltages during short circuit shutdown. The short circuit protectionprovided by the IPM uses actualcurrent measurement to detectdangerous conditions. This type ofprotection is faster and more reli-able than conventional out-of-satu-ration protection schemes. Figure6.17 is a timing diagram showingthe operation of the short circuitprotection.

To reduce the response time be-tween SC detection and SC shut-down, a real time current controlcircuit (RTC) has been adopted.The RTC bypasses all but the finalstage of the IGBT driver in SC op-eration thereby reducing the re-sponse time to less than 100ns.The oscillographs in Figure 6.19 il-lustrate the effectiveness of theRTC technique by comparing shortcircuit operation of second genera-tion IPM (without RTC) and thirdgeneration IPM (with RTC).A significant improvement can beseen as the power stress is muchlower as the time in short circuitand the magnitude of the short cir-cuit current are substantially re-duced.

Note:The short circuit protection inV-Series IPMs has a delay similarto the third generation over currentprotection function described in6.4.4. The need for a quick trip hasbeen eliminated through the use ofa new advanced RTC circuit.

Caution:1. Tripping of the over current

and short circuit protection indi-cates stressful operation of theIGBT. Repetitive tripping mustbe avoided.

2. High surge voltages can occurduring emergency shutdown.Low inductance buswork andsnubbers are recommended.

6.5 IPM Selection

There are two key areas that mustbe coordinated for proper selectionof an IPM for a particular inverterapplication. These are peakcurrent coordination to the IPMovercurrent trip level and properthermal design to ensure thatpeak junction temperature is al-ways less than the maximum junc-tion temperature rating(150°C) and that the baseplatetemperature remains below theover-temperature trip level.

6.5.1 Coordination of OC Trip

Peak current is addressed by refer-ence to the power rating of the mo-tor. Tables 6.2, 6.3 and 6.4 giverecommended IPM types derivedfrom the OC trip level and the peakmotor current requirement basedon several assumptions for the in-verter and motor operation regard-ing efficiency, power factor, maxi-mum overload, and current ripple.For the purposes of this table, themaximum motor current is takenfrom the NEC table. This alreadyincludes the motor efficiency andpower factor appropriate to the par-ticular motor size. Peak invertercurrent is then calculated using thisRMS current, a 200% overload re-quirement, and a 20% ripple factor.An IPM is then selected which hasa minimum overcurrent trip levelthat is above this calculated peakoperating requirement.

Figure 6.19 WaveformsShowing the Effectof the RTC Circuit

SHORT CIRCUIT OPERATION WITHOUT RTC CIRCUIT 100A, 600V, IPM

SHORT CIRCUIT OPERATION WITH RTC CIRCUIT 100A, 600V, IPM

800AVCE

IC

IC=200A/div, VCE=100V/div, t=1µs/div

VCET

ICT

410A

IC=200A/div, VCE=100V/div, t=1µs/div

T

T



Sep.1998

Table 6.2 Motor Rating vs. OC Protection (230 VAC Line)Current

Motor Rating (HP) NEC Current Rating A(RMS)τ Inverter Peak Current (A)* Applicable IPM Minimum OC Trip (A)

0.5 2.0 6.8 PM10CSJ060 12

0.75 2.8 9.5 PM10CSJ060 12

1 3.6 12.2 PM15CSJ060 18

1.5 5.2 17.6 PM15CSJ060 18

2 6.8 23 PM20CSJ060 28

3 9.6 32 PM30CSJ060, PM30RSF060 39

5 15.2 52 PM50RSA060, PM50RSK060 65

7.5 22 75 PM75RSA060, PM75RSK060 115

10 28 95 PM75RSA060, PM75RSK060 115

15 42 143 PM100CSA060, PM100RSA060 158

20 54 183 PM150CSA060, PM150RSA060 210

25 68 231 PM200CSA060, PM200RSA060, 310

PM200DSA060 x3

30 80 271 PM200CSA060, PM200RSA060, 310

PM200DSA060 x3

40 104 353 PM300DSA060 x3 390

50 130 441 PM400DSA060 x3 500

60 154 523 PM600DSA060 x3 740

75 192 652 PM600DSA060 x3 740

100 256 869 PM800HSA060 x6 1000τ - From NEC Table 430-150* - Inverter peak current is based on 200% overload requirement and a 20% current ripple factor.

Table 6.3 Motor Rating vs. OC Protection (460 VAC Line)Current

Motor Rating (HP) NEC Current Rating A(RMS)τ Inverter Peak Current (A)* Applicable IPM Minimum OC Trip (A)

0.5 1.0 3.4 PM10RSH120, PM10CZF120 15

0.75 1.4 4.8 PM10RSH120, PM10CZF120 15

1 1.8 6.1 PM10RSH120, PM10CZF120 15

1.5 2.6 8.8 PM10RSH120, PM10CZF120 15

2 3.4 12 PM10RSH120, PM10CZF120 15

3 4.8 16 PM15RSH120, PM15CZF120 22

5 7.6 26 PM25RSB120, PM25RSK120 32

7.5 11 37 PM50RSA120 59

10 14 48 PM50RSA120 59

15 21 71 PM75CSA120, PM75DSA120 x3 105

20 27 92 PM75CSA120, PM75DSA120 x3 105

25 34 115 PM100CSA120, PM100DSA120 x3 145

30 40 136 PM100CSA120, PM100DSA120 x3 145

40 52 176 PM150DSA120 x3 200

50 65 221 PM200DSA120 x3 240

60 77 261 PM300DSA120 x3 380

75 96 326 PM300DSA120 x3 380

100 124 421 PM400HSA120 x6 480

125 156 529 PM600HSA120 x6 740

150 180 611 PM600HSA120 x6 740

200 240 815 PM800HSA120 x6 1060

250 300 1020 PM800HSA120 x6 1060τ - From NEC Table 430-150* - Inverter peak current is based on 200% overload requirement and a 20% current ripple factor.



Sep.1998

6.5.2 Estimating Losses

Once the coordination of theOC trip with the application require-ments has been established thenext step is determining the coolingsystem requirements. Section 3.4provides a general description ofthe methodology for loss estimationand thermal system design. Figure6.20 shows the total switching en-ergy (ESW(on)+ESW(off)) versus ICfor all third generation IPMs.Figure 6.21 shows total switchingenergy versus IC for V-SeriesIPMs. A detailed explanation ofthese curves and their use can befound in Section 3.4.1. Figures6.22 through 6.34 show simulationresults calculating total power loss(switching and conduction) per armin a sinusoidal output PWM inverterapplication using V-Series IPMs.

Table 6.4 Motor Rating vs. SC Protection for V-Series IPMsCurrent

Motor Rating (HP) NEC Current Rating A(RMS)τ Inverter Peak Current (A)* Applicable IPM Minimum SC Trip (A)

240VAC Line

10 28 95 PM75RVA060 115

15 42 143 PM100CVA060 158

20 54 183 PM150CVA060 210

30 80 271 PM200CVA060 310

40 104 353 PM300CVA060 396

50 130 441 PM400DVA060 650

75 192 652 PM600DVA060 1000

460VAC Line

10 14 48 PM50RVA120 59

20 27 92 PM75CVA120 105

30 40 136 PM100CVA120 145

40 52 176 PM150CVA120 200

50 65 221 PM200DVA120 240

75 96 326 PM300DVA120 380τ - From NEC Table 430-150* - Inverter peak current is based on 200% overload requirement and a 20% current ripple factor.

100 101 102 103 10410-1

100

COLLECTOR CURRENT, IC, (AMPERES)

SW

ITC

HIN

TG

DIS

SIP

AT

ION

, (m

J/P

ULS

E)

101

103

102

CONDITIONS: INDUCTIVE LOAD SWITCHING OPERATION Tj = 125oC VCC = 1/2 VCES VD = 15V

SWITCHING DISSIPATION = TURN-ON DISSIPATION + TURN-OFF DISSIPATION COMPATIBLE IC RANGE: RATED IC × 0.1 ~ 1.4

600V SERIES1200V SERIES

APPLICABLE TYPES: THIRD-GENERATION IPM PM200DSA060, PM75DSA120, PM300DSA120, PM75CSA120, PM20CSJ060, PM50RSK060, PM10RSH120,

PM300DSA060, PM100DSA120, PM100CSA060, PM100CSA120, PM300CSJ060, PM75RSA060, PM15RSH120,

PM400DSA060, PM150DSA120, PM150CSA060, PM10CSJ060, PM30RSF060, PM100RSA060, PM25RSB120,

PM600DSA060, PM200DSA120, PM200CSA060, PM15CSJ060, PM50RSA060, PM150RSA060, PM50RSA120

Figure 6.20 Switching Energy vs. I C for Third Generation IPMs



Sep.1998

100 101 102 103 10410-1

100

COLLECTOR CURRENT, IC, (AMPERES)

SWITCHING ENERGY LOSS FOR V-SERIES IPMs

SW

ITC

HIN

G E

NE

RG

Y, (

mJ/

PU

LSE

)

101

103

102

CONDITIONS: INDUCTIVE LOAD Tj = 125oC VCC = 1/2 VCES VD = 15V

600V SERIES1200V SERIES

ESW (ON) + ESW (OFF) COMPATIBLE IC RANGE: RATED IC × 0.1 ~ 1.4

0 20 40 60 10080 1200

IO(ARMS)

50

P(W

)

100

150

200

250

DC LOSS SW LOSS TOTAL LOSS

VCC = 300V VD = 15V Tj = 125°C P.F. = 0.8 fc = 10kHz

Figure 6.21 Figure 6.22 Power LossSimulation ofPM75RVA060 (Typ.)

Figure 6.23 Power LossSimulation ofPM100CVA060 (Typ.)



Figure 6.27 Power LossSimulation ofPM400DVA060 (Typ.)



Figure 6.29 Power LossSimulation ofPM50RVA120 (Typ.)

0 20 40 60 10080 1200

IO(ARMS)

50

P(W

)

100

150

200

250



0 20 40 60 10080 1200

IO(ARMS)

50

P(W

)

100

150

200

250



0 40 80 120 200160 2400

IO(ARMS)

50

P(W

)

100

150

200

250



0 40 80 120 200160 2400

IO(ARMS)

50

P(W

)

100

150

200

250



0 40 80 120 200160 2400

IO(ARMS)

50

P(W

)

100

150

200

250



0 40 80 120 200160 360320240 2800

IO(ARMS)

50

P(W

)

100

150

300

250

200

350



0 15 30 45 9075600

IO(ARMS)

50

P(W

)

100

150

300

250

200

350





Sep.1998

6.6 Controlling the IntelligentPower Module

IPM (Intelligent Power Modules)are easy to operate. The integrateddrive and protection circuits requireonly an isolated power supply anda low level on/off control signal. Afault output is provided for monitor-ing the operation of the modules in-ternal protection circuits.

6.6.1 The Control Power Supply

Depending on the power circuitconfiguration of the module one,two, or four isolated power suppliesare required by the IPMs internaldrive and protection circuits. In highpower 3-phase inverters usingsingle or dual type IPMs it is goodpractice to use six isolated powersupplies. In these high current ap-plications each low side devicemust have its own isolated controlpower supply in order to avoidground loop noise problems. Thecontrol supplies should be regu-lated to 15V +/-10% in order toavoid over-voltage damage or falsetripping of the under-voltage pro-tection. The supplies should havean isolation voltage rating of atleast two times the IPM’s VCES rat-ing (i.e. Viso = 2400V for 1200Vmodule). The current that must besupplied by the control power sup-ply is the sum of the quiescent cur-rent needed to power the internalcontrol circuits and the current re-quired to drive the IGBT gate.

Table 6.5 summarizes the typicaland maximum control powersupply current requirements for

Figure 6.30 Power LossSimulation ofPM75RVA1200 (Typ.)





0 15 30 45 9075600

IO(ARMS)

50

P(W

)

100

150

300

250

200

350



0 20 40 60 10080 180160120 1400

IO(ARMS)

50

P(W

)

100

150

300

250

200

350



0 20 40 60 10080 180160120 1400

IO(ARMS)

50

P(W

)

100

150

300

250

200

350



0 20 40 60 10080 180160120 1400

IO(ARMS)

50

P(W

)

100

150

300

250

200

350



0 20 40 60 10080 180160120 1400

IO(ARMS)

50

P(W

)

100

150

300

250

200

350





Sep.1998

third generation Intelligent PowerModules. Table 6.6 summarizescontrol supply requirements forV-Series IPMs. These tables givecontrol circuit currents for the qui-escent (not switching) state and for20kHz switching. This data is pro-vided in order to help the user de-sign appropriately sized controlpower supplies.

Power requirements for operatingfrequencies other than 20kHz canbe determined by scaling the fre-quency dependent portion of thecontrol circuit current. For example,to determine the maximum controlcircuit current for a PM300DSA120operating at 7kHz the maximumquiescent control circuit current issubtracted from the maximum20kHz control circuit current:

70mA – 30mA = 40mA

40mA is the frequency dependentportion of the control circuit currentfor 20kHz operation. For 7kHzoperation the frequencydependent portion is:

40mA x (7kHz ÷ 20kHz) = 14mA

To get the total control power sup-ply current required, the quiescentcurrent must be added back:

30mA + 14mA = 44mA

44mA is the maximum control cir-cuit current required for aPM300DSA120 operating at 7kHz.

Capacitive coupling between pri-mary and secondary sidesof isolated control supplies mustbe minimized as parasitic capaci-tances in excess of 100pF cancause noise that may trigger

Table 6.5 Control Power Requirements for Third Generation IPMs(VD = 15V, Duty = 50%) ma

N Side P Side (Each Supply)

DC 20kHz DC 20kHz

Type Name Typ. Max Typ. Max. Typ. Max. Typ. Max.

600V Series

PM10CSJ060 18 25 23 32 7 10 8 12

PM15CSJ060 18 25 23 32 7 10 8 12

PM20CSJ060 18 25 24 34 7 10 8 12

PM30CSJ060 18 25 24 34 7 10 9 13

PM100CSA060 40 55 78 100 13 18 25 34

PM150CSA060 40 55 80 110 13 18 25 38

PM200CSA060 40 55 85 120 13 18 27 40

PM30RSF060 25 30 32 45 7 10 9 13

PM50RSA060 44 60 70 100 13 18 23 32

PM50RSK060 44 60 70 100 13 18 23 32

PM75RSA060 44 60 75 100 13 18 24 35

PM100RSA060 44 60 78 105 13 18 25 36

PM150RSA060 52 72 72 113 13 18 26 38

PM200RSA060 52 72 85 115 13 18 26 40

PM200DSA060 19 26 30 42 19 26 30 42

PM300DSA060 19 26 35 48 19 26 35 48

PM400DSA060 23 30 40 60 23 30 40 60

PM600DSA060 23 30 50 70 23 30 50 70

PM800HSA060 23 30 50 70 – – – –

1200V SERIES

PM10RSH120 25 35 31 44 7 10 9 13

PM10CZF120 18 25 7 10 9 13

PM15RSH120 25 35 32 45 7 10 9 13

PM15CZF120 18 25 7 10 9 13

PM25RSB120 44 60 60 83 13 18 18 25

PM25RSK120 44 60 60 83 13 18 18 25

PM50RSA120 44 60 65 90 13 18 19 27

PM75CSA120 44 60 60 83 13 18 20 28

PM100CSA120 40 55 75 104 13 18 25 35

PM75DSA120 13 20 20 28 13 20 20 28

PM100DSA120 19 26 30 42 19 26 30 42

PM150DSA120 19 26 35 48 19 26 35 48

PM200DSA120 23 30 48 67 23 30 48 67

PM300DSA120 23 30 50 70 23 30 50 70

PM400HSA120 23 30 60 90 – – – –

PM600JSA120 23 30 60 90 – – – –

PM800HSA120 30 40 – – – – – –



Sep.1998

the control circuits. An electrolyticor tantalum decoupling capacitorshould be connected across thecontrol power supply at the IPMsterminals. This capacitor will helpto filter common noise on the con-trol power supply and provide thehigh pulse currents required by theIPMs internal gate drive circuits.Isolated control power supplies canbe created using a variety of tech-niques. Control power can be de-rived from the main input line usingeither a switching power supplywith multiple outputs or a line fre-quency transformer with multiplesecondaries. Control power sup-plies can also be derived from themain logic power supply using DC-to-DC converters. Using a compactDC-to-DC converter for each iso-lated supply can help to simplifythe interface circuit layout. A distrib-uted DC-to-DC converter in whicha single oscillator is used to driveseveral small isolation transformers

can provide the layout advantagesof separate DC-to-DC converters ata lower cost.

In order to simplify the design ofthe required isolated power sup-plies, Mitsubishi has developed twoDC-to-DC converter modules towork with the IPMs. The M57120Lis a high input voltage step downconverter. When supplied with 113to 400VDC the M57120L will pro-duce a regulated 20VDC output.The 20VDC can then be connectedto the M57140-01 to produce fourisolated 15VDC outputs to powerthe IPMs control circuits. TheM57140-01 can also be used as astand alone unit if 20VDC is avail-able from another source such asthe main logic power supply. Figure6.35 shows an isolated interfacecircuit for a seven pack IPM usingM57140-01. Figure 6.36 shows acomplete high input voltage iso-lated power supply circuit for a dual

type intelligent power module.

Caution:Using bootstrap techniques is notrecommended because the voltageripple on VD may cause a false tripof the undervoltage protection incertain inverter PWM modes.

6.6.2 Interface Circuit Require-ments

The IGBT power switches in theIPM are controlled by a low levelinput signal. The active low controlinput will keep the power devicesoff when it is held high. Typicallythe input pin of the IPM is pulledhigh with a resistor connected tothe positive side of the controlpower supply. An ON signal is thengenerated by pulling the control in-put low. The fault output is an opencollector with its maximum sink cur-rent internally limited. When a faultcondition occurs the open collectordevice turns on allowing the faultoutput to sink current from the posi-tive side of the control supply. Faultand on/off control signals are usu-ally transferred to and from the sys-tem controller using isolating inter-face circuits. Isolating interfaces al-low high and low side control sig-nals to be referenced to a commonlogic level. The isolation is usuallyprovided by optocouplers. How-ever, fiber optics, pulse transform-ers, or level shifting circuits couldbe used. The most important con-sideration in interface circuit designis layout. Shielding and carefulrouting of printed circuit wiring isnecessary in order to avoid cou-pling of dv/dt noise into control cir-cuits. Parasitic capacitance be-tween high side

Table 6.6 V-Series IPM Control Power Supply Current

N Side P Side (Each Supply)

DC 20kHz DC 20kHz

Type Name Typ. Max Typ. Max. Typ. Max. Typ. Max.

600V Series

PM75RVA060 44 60 72 94 13 18 21 27

PM100CVA060 40 55 68 88 13 18 22 29

PM150CVA060 40 55 72 94 13 18 23 30

PM200CVA060 40 55 84 110 13 18 28 36

PM300CVA060 52 72 130 170 17 24 43 56

PM400DVA060 23 30 56 73 23 30 56 73

PM600DVA060 23 30 56 73 23 30 56 73

1200V SERIES

PM50RVA120 44 60 73 95 13 18 21 27

PM75CVA120 40 55 70 92 13 18 24 31

PM100CVA120 40 55 80 104 13 18 26 34

PM150CVA120 72 100 128 166 24 34 42 55

PM200DVA120 37 48 52 68 37 48 52 68

PM300DVA120 37 48 52 68 37 48 52 68



Sep.1998

1

HCPL4504

0.1µF

SEVEN PACK IPM

VUP1

UP

VUPC

UFOC1

20k

0.1µF20k

2

3

4

8

7

6

5

3PC817

4

2

1

1

HCPL4504

2

3

4

8

7

6

5

3PC817

4

1

2

3

4

5

-

+

+

6

7

8

9

10

11VIN

12

13

14

0+15

0+15

0+15

0+15

2

1

4

3

2

1

VVP1

VP

VVPC

VFO

VWP1

WP

VWPC

WFO

UN

BR

VNC

VNI

FO

VN

WN

8

7

6

5

12

11

10

9

16

15

14

13

19

18

17

1

HCPL4504

0.1µF

+

+

20k2

3

4

8

7

6

5

3PC817

4

2

1

C1

+

C1

+

1

HCPL4504

0.1µF

4.7k

C2

+

2

3

4

8

7

6

5

1PC817

2

4

3

1

HCPL4504

0.1µF2

3

4

8

7

6

5

1

HCPL4504

0.1µF

20k

20k

20k

2

3

4

8

7

6

5

3PC817

4

2

1

20V

330µF

FON

WN

VN

UN

B

WP

FOWP

VP

FOVP

UP

FOUP

NOTE: FOR C1 AND C2 SEE SECTION 6.6.3

Figure 6.35 Isolated Interface Circuit for Seven-Pack IPMs



Sep.1998

interface circuits, high and low sideinterface circuits, or primary andsecondary sides of the isolating de-vices can cause noise problems.Careful layout of control powersupply and isolating circuit wiring isnecessary. The following is a list ofguidelines that should be followedwhen designing interface circuits.Figure 6.37 shows an example in-terface circuit layout for dual typeIPMs. Figure 6.38 shows an ex-ample interface circuit layout for aV-Series IPMs.The shielding andprinted circuit routing techniquesused in this example are intendedto illustrate a typical application ofthe layout guidelines.

INTERFACE CIRCUITLAYOUT GUIDELINES

I. Maintain maximum interfaceisolation. Avoid routing printedcircuit board traces from pri-mary and secondary sides ofthe isolation device near to orabove and below each other.Any layout that increases theprimary to secondary capaci-tance of the isolating interfacecan cause noise problems.

II. Maintain maximum controlpower supply isolation. Avoidrouting printed circuit boardtraces from UP, VP, WP, and Nside supplies near to eachother. High dv/dts exist be-tween these supplies andnoise will be coupled throughparasitic capacitances.If isolated power supplies arederived from a common trans-former interwinding capaci-tance should be minimized.

III. Keep printed circuit boardtraces between the interfacecircuit and IPM short. Longtraces have a tendency to pickup noise from other parts of thecircuit.

IV. Use recommended decouplingcapacitors for power suppliesand optocouplers. Fast switch-ing IGBT power circuits gener-ate dv/dt and di/dt noise. Everyprecaution should be taken toprotect the control circuits fromcoupled noise.

V. Use shielding. Printed circuitboard shield layers are helpful

for controlling coupled dv/dtnoise. Figure 6.37 shows anexample of how the primaryand secondary sides of the iso-lating interface can beshielded.

VI. High speed optocouplers withhigh common mode rejection(CMR) should be used for sig-nal input:

tPLH,tPHL < 0.8µsCMR > 10kV/µs@ VCM = 1500V

Appropriate optocoupler typesare HCPL 4503, HCPL 4504(Hewlett Packard) and PS2041(NEC). Usually high speedoptos require a 0.1µFdecoupling capacitor close tothe opto.

VII. Select the control input pull-upresistor with a low enoughvalue to avoid noise pick-up bythe high impedance IPM inputand with a high enough valuethat the high speedoptotransistor can still pull theIPM safely below the recom-mended maximum VCIN(on).

Figure 6.36 Isolated Interface Circuit for Dual Intelligent Power Modules

1

HCPL4504

0.1µF

C1

V1 (+)

P

SR (+5)

CIN

FO

VC (-)

V1 (+)

N

C1

DUAL IPM

SR (+5)

CINCI

FO

VC (-)

+

6.8k

0.1µF6.8k

2

3

4

8

7

6

5

3PC817

4

2

1

1

HCPL4504

2

3

4

8

7

6

5

3PC817

4

3

22.2µF

47µF 50V

330µF 50V 1

7 5 2 112

113-400 VDC

11

6

5

-

+

+

+

+

+

+

4

14

NFO

NIN

PFO

PIN

13

12

11

10VIN

9

8

7

+150

+150

+150

+150

2

1

M57120L

1

2

3

45

1

2

3

45



Sep.1998

Figure 6.37 Interface Circuit Layout Example for Dual IPMs

WNVNUNWPVPUP

+-

+-

+-

+-

+-

+-FO

WN

FO

WP

FO

VN

VP

FO

UN

FO

UP

FO

SHIELDS GROUND TO NEGATIVE SIDE OF EACH CONTROL

POWER SUPPLY

DIGITAL GROUND

MID-LAYER SHIELD

TO CONTROL POWER SOURCE

W

V

U

LEGEND

TOP LAYER

MIDDLE LAYER

BOTTOM LAYER

SHIELD GROUND TO VUNC

SHIELD GROUND TO VUPC

SHIELD GROUND TO VVNC

SHIELD GROUND TO VVPC

SHIELD GROUND TO VWNC

SHIELD GROUND TO VWPC



Sep.1998

VIII.If some IPM switches are notused in actual application theircontrol power supply must stillbe applied. The related signalinput terminals should bepulled up by resistors to thecontrol power supply (VD orVSXR) to keep the unusedswitches safely in off-state.

IX. Unused fault outputs must betied high in order to avoid noisepick up and unwanted activa-tion of internal protection cir-cuits. Unused fault outputsshould be connected directly tothe +15V of local isolated con-trol power supply.

6.6.3 Example Interface Circuits

IPM (Intelligent Power Modules)are designed to use optocoupledtransistors for control input andfault output interfaces. In most ap-plications optocouplers will provide

a simple and inexpensive isolatedinterface to the system controller.Figures 6.39 through 6.43 show ex-ample interface circuits for the fourIPM power circuit configurations.These circuits use two types ofoptocoupled transistors. The con-trol input on/off signals are trans-ferred from the system controllerusing high speed optocoupled tran-sistors. Usually high speed optosrequire a 0.1µF film or ceramicdecoupling capacitor connectednear their VCC and GND pins. Thevalue of the control input pull up re-sistor is selected low enough toavoid noise pick up by the high im-pedance input and high enough sothat the high speed optotransistorwith its relatively low current trans-fer ratio can still pull the input lowenough to assure turn on. The cir-cuits shown use a Hewlett PackardHCPL-4504 optotransistor. Thisopto was chosen mainly for its highcommon mode transient immunity

of 15,000V/µs. For reliable opera-tion in IGBT power circuitsoptocouplers should have a mini-mum common mode noise immu-nity of 10,000 V/µs. Low speedoptocoupled transistors can beused for the fault output and brakeinput. Slow optos have the addedadvantages of lower cost andhigher current transfer ratios. Theexample interface circuits use aSharp PC817 low speedoptocoupled transistor for thetransfer of brake and fault signals.Like most low speed optos thePC817 does not have internalshielding. Some switching noisewill be coupled through the opto.An RC filter with a time constant ofabout 10ms can be added to theopto’s output to remove this noise.The IPMs 1.5ms long fault outputsignal will be almost unaffected bythe addition of this filter. When de-signing interface circuits always fol-low the interface circuit layoutguidelines given in Section 6.6.2.

Figure 6.38 Interface Circuit Layout for a V-Series IPMs

BPN

U V WIPM

IPM

INTERFACE CIRCUIT

PCB



Sep.1998

Figure 6.39 Interface Circuit for Seven-Pack IPMs

N

P

B

U

V

W

LIN

EM

OT

OR

+

CS

VUPC

UFO

UP

VUP1

VVPC

VFO

VP

VVP1

VWPC

WFO

WP

VWP1

VNC

VN1

BR

UN

VN

WN

FO

7-P

AC

K T

HIR

D G

EN

ER

AT

ION

IPM

10µF

20k 0.1µF

15 V

+

FAULT

UP IN

TE

RF

AC

E

INPUT

15 V

+

15 V

+

15 V

+

VP IN

TE

RF

AC

EW

P IN

TE

RF

AC

EN

SID

E IN

TE

RF

AC

E

FAULT OUTPUT

INPUT

BRAKE

UN INPUT

VN INPUT

WN INPUT

FAULT

0.1µF

0.1µF

0.1µF

33µF

20k

4.7k

20k

20k

SAME AS

UP INTERFACE

CIRCUIT

SAME AS

UP INTERFACE

CIRCUIT

FAULT OUTPUT

INPUT

Rated Decoupling

Applicable Current Capacitor

Types (Amps) (CS)

600V Modules

PM30RSF060 30 0.3µF

PM50RSK060 55 0.47µF

PM50RSA060 50 0.47µF

PM75RSA060, 75 1.0µF

PM75RSK060,

PM75RVA060

PM100RSA060 100 1.0µF

PM150RSA060 150 1.5µF

PM200RSA060 200 2.0µF

1200V Modules

PM10RSH120 10 0.1µF

PM15RSH120 15 0.1µF

PM25RSB120, 25 0.22µF

PM25RSK120

PM50RSA120, 50 0.47µF

PM50RVA120

NOTE: If high side fault outputs are not used, theymust be connected to the +15V of the local powersupply.



Sep.1998

Figure 6.40 Interface Circuit for Six-Pack IPMs

N

P

U

V

W

LIN

EM

OT

OR

+

CS

VUPC

UFO

UP

VUP1

VWPC

VFO

VP

VVP1

WFO

VWP1

VNC

VN1

UN

VN

WN

FO

6-P

AC

K T

HIR

D G

EN

ER

AT

ION

IPM

10µF

20k 0.1µF

15 V

+

FAULT

UP IN

TE

RF

AC

E

INPUT

15 V

+

15 V

+

15 V

+

VP

INT

ER

FA

CE

WP IN

TE

RF

AC

EN

SID

E IN

TE

RF

AC

E

FAULT OUTPUT

INPUT

UN INPUT

VN INPUT

WN INPUT

FAULT

0.1µF

0.1µF

0.1µF

33µF

20k

20k

20k

SAME AS

UP INTERFACE

CIRCUIT

VWPC

WP

SAME AS

UP INTERFACE

CIRCUIT

FAULT OUTPUT

INPUT

Rated Decoupling

Applicable Current Capacitor

Types (Amps) (CS)

600V Modules

PM10CSJ060 10 0.1µF

PM15CSJ060 15 0.1µF

PM20CSJ060 20 0.1µF

PM30CSJ060 30 0.3µF

PM100CSA060, 100 1.0µF

PM100CVA060

PM150CSA060, 150 1.5µF

PM150CVA060

PM200CSA060, 200 2.2µF

PM200CVA060

PM300CVA060 300 3.0µF

1200V Modules

PM75CSA120, 75 1.0µF

PM75CVA120

PM100CSA120, 100 1.0µF

PM100CVA120

PM150CVA120 150 1.5µF

NOTE: Unused fault outputs must be connected tothe +15V of the local control supply.



Sep.1998

Figure 6.41 Interface Circuit for Dual IPMs

C2

6.8k

+

C2 C2

15 V 15 V

15 V15 V15 V

VCCWVU

MOTOR

IPM

+

+++ +

IPMIPM

INPUT

FAULT

++

0.1µF

0.1µF

6.8k

C1 +

C1 +

15 V

FNO

VNC

CNI

SNR

VN1

FPO

VPC

CPI

SPR

VP1

FNO

VNC

CNI

SNR

VN1

FPO

VPC

CPI

SPR

VP1

FNO

VNC

CNI

SNR

VN1

FPO

VPC

CPI

SPR

VP1

E1C2 C1E2 E1C2 C1E2 E1C2 C1E2

INPUT

FAULT

Control Power

Rated Decoupling Snubber

Applicable Current Capacitor Capacitor

Types (Amps) (C1) (C2)

600V Modules

PM200DSA060 200 47µF 2.0µF

PM300DSA060 300 47µF 3.0µF

PM400DSA060, 400 68µF 4.0µF

PM400DVA060

PM600DSA060, 600 68µF 6.0µF*

PM600DVA060

1200V Modules

PM75DSA120 75 22µF 0.68µF

PM100DSA120 100 47µF 1.5µF

PM150DSA120 150 47µF 2.0µF

PM200DSA120, 200 68µF 3.0µF

PM200DVA120

PM300DSA120, 300 68µF 5.0µF

PM300DVA120

*Depending on maximum DC link voltage andmain circuit layout, an RCDi clamp may beneeded. (see Section 3.3)



Sep.1998

Control Power Main Bus

Rated Decoupling Snubber Decoupling

Applicable Current Capacitor Capacitor Capacitor

Types (Amps) (C1) (C2) (C3) Snubber Diode

600V Modules

PM800HSA060 800 68µF 3.0µF 6.0µF RM50HG-12S (2 pc. parallel)

1200V Modules

PM400HSA120 400 68µF 1.5µF 4.0µF RM25HG-24S

PM600HSA120 600 68µF 2.0µF 6.0µF RM25HG -24S (2 pc. parallel)

PM800HSA120 800 68µF 3.0µF 6.0µF RM25HG-24S (3 pc. parallel)

Figure 6.42 Interface Circuit for Single IPMs

+

+15 V

6.8k

IPM

0.1µF

C1

INPUT

FAULT

V1

SR

C1

C2

VC

C

E

D

FO

+

+15 V

6.8k

IPM

0.1µF

C1

V1

SR

C1

VC

C

E

FO

C2

C3 C3 C3

D

IPM

V1

SR

C1

C2

VC

C

E

D

FO

IPM

V1

SR

C1

VC

C

E

FO

C2

D

IPM

V1

SR

C1

C2

VC

C

E

D

FO

IPM

V1

SR

C1

VC

C

E

FO

C2

D

+ +

+15V

+

VCC

+

MOTOR

U V W

INPUT

FAULT

15V

15V 15V



Sep.1998

Figure 6.43 Interface Circuit for PM10CZF120 and PM15CZF120

0.1µ

0.1µ

10µ+

–

20k

20k

VWP

WP

VWPC

UN

VN

WN

VN1

FO

VNC

IFVD3VD3

VD4

5V

10k

0.1µ10µ

+

–

20kVVP

VP

VVPC

IFVD2

0.1µ10µ

+

–

20kVUP

UP

VUPC

IFVD1

IF

0.1µ

20k

IF

0.1µ

20k

IF

33µ+

–

M

CS

P

U

V

W

N

+

–

VCC



Sep.1998

6.6.4 Connecting theInterface Circuit

The input pins of Mitsubishi Intelli-gent Power Modules are designedto be connected directly to aprinted circuit board. Noise pick upcan be minimized by building theinterface circuit on the PCB nearthe input pins of the module. Lowpower modules have tin platedcontrol and power pins that are de-signed to be soldered directly tothe PCB. Higher power moduleshave gold plated pins that are de-signed to be connected to the PCBusing an inverse mounted headerreceptacle. An example of this con-nection for a dual type IPM isshown in Figure 6.44. This connec-tion technique can also be adaptedto large six and seven pack mod-ules. Table 6.7 shows the sug-gested connection method andconnector for each Third Genera-tion IPM.

Table 6.8 shows the suggestedconnection method and connectorfor V-Series IPMs. Figure 6.45shows the PCB layout for V-Seriessix and seven pack connector.

Figure 6.44 Connection of the Interface Circuit

A B C D E

Hole for Header receptacle pin Clearance Hole for IPM pin Clearance Hole for IPM guide pin IPM pin spacing Header Receptacle Pin Spacing

.040" Typ.

.070" Typ.

.090" Typ. 0.10" Typ.

per connector mfg.

A

C

B

SIDE VIEW

END VIEW

E

D

HEADER RECEPTACLE

PRINTED CIRCUIT BOARD

IPMS GUIDE PINS

C1

PCB LAYOUT EXAMPLE FOR DUAL TYPE 3RD GENERATION IPM

Table 6.7 Third Generation IPM Connection Methods

Third Generation Intelligent Power Module Type Connection Method

PM10CSJ060, PM15CSJ060, PM20CSJ060, Solder to PCBPM30CSJ060, PM30RSF060, PM50RSK060,PM10RSH120, PM15RSH120

PM50RSA060, PM75RSA060, PM100CSA060, 31 Position 2mm Inverse HeaderPM100RSA060, PM150CSA060, PM150RSA060, ReceptaclePM200CSA060, PM25RSB120, PM50RSA120, Hirose P/N: DF10-31S-2DSA (59)PM75CSA120, PM100CSA120

PM200DSA060, PM300DSA060, PM400DSA060, 5 Position 2.54mm (0.1") InversePM600DSA060, PM75DSA120, PM100DSA120, Header ReceptaclePM150DSA120, PM200DSA120, PM300DSA120, Method P/N: 1000-205-2105PM400HSA120, PM600HSA120 Hirose P/N: MDF7-5S-2.54DSA



Sep.1998

6.6.5 Dead Time (t dead)

In order to prevent arm shootthrough a dead time between highand low side input ON signals isrequired to be included in the sys-tem control logic. Two different val-ues are specified on the datasheet:

A. tdead measured directly onthe IPM input terminals

B. tdead related to optocouplerinput signals using therecommended applicationcircuit

The specified type B dead time isrelated to standard high speedoptocouplers. (See Section 6.6.2)By using specially selected

optocouplers with narrow distribu-tion of switching timesthe required type B dead timecould be reduced.

6.6.6 Using the Fault Signal

In order to keep the interface cir-cuits simple the IPM usesa single on/off output to alert thesystem controller of all fault condi-tions. The system controller caneasily determine whether the faultsignal was caused by an over tem-perature or over current/short cir-cuit by examining its duration.Short circuit and over current con-dition fault signals will be tFO(nominal 1.5ms) in duration. Anover temperature fault signal will bemuch longer. The over temperature

Figure 6.45 PCB Layout for V-Series Connector

fault starts when the base platetemperature exceeds the OT leveland does not reset until the baseplate cools below the OTr level.Typically this takes tens of sec-onds.

Note:Unused fault outputs must be prop-erly terminated by connecting themto the +15V on the local controlpower supply. Failure to properlyterminate unused fault outputs mayresult in unexpected tripping of themodules internal protection.

3 ± 0.05 3 ± 0.053 ± 0.05

3 ± 0.053 ± 0.05

43.57 ± 0.1

19 - ø1.2 +0.1 0

19 - ø0.9 +0.1 0

4 - ø3.2 +0.1 -0.07

14.1 ± 0.0514.1 ± 0.052.54 ± 0.05

2.54 ± 0.05

14.1 ± 0.05

14.6 ± 0.1

Table 6.8 V-Series IPM Connection Methods

V-Series Intelligent Power Module Type Connection Method

PM75RVA060, PM100CVA060, PM150CVA060, 19 Position, 0.1" CompoundPM200CVA060, PM300CVA060, PM50RVA120, Inverse Header Receptacle,PM75CVA120, PM100CVA120, PM150CVA120 Hirose Part # MDF92-19S-2.54DSA

PM400DVA060, PM600DVA060, 5 Position, 0.1" (2.54mm)PM200DVA120, PM300DVA120 Inverse Header Receptacle,

Hirose Part # MDF7-5S-2.54DSA



Sep.1998

6.7 IPM Inverter Example

The IPMs integrated intelligencegreatly simplifies inverter design.The built in protection circuits allowmaximum utilization of power de-vice capability without compromis-ing reliability. Figure 6.46 shows acomplete inverter constructed us-ing dual type IPMs. Input commonmode noise filtering and MOVsurge suppression helps to protectthe input rectifier and IPMs fromline transients. The main powerbus is constructed using laminatedplates in order to minimize parasiticinductance. Low inductance busdesigns are covered in more detailin Sections 3.2 and 3.3. An ex-ample of the mechanical layout ofthe inverter is shown in Figure6.47. The IPMs must be mountedon a heatsink with suitable coolingcapabilities. Thermal design andpower loss estimation is covered inSection 3.4. Mitsubishi offers acomplete line-up of diode modulesthat are ideal for use as the inputbridge in inverter applications.

Figure 6.46 IPM Inverter System

+

–

RECTIFIER BRIDGE

A

C

B

C

C

C

HEAT SINK GROUND

IPM

+

IPM IPM

PRINTED CIRCUIT BOARD CONTAINING INTERFACE CIRCUITS AND ISOLATED POWER SUPPLIES

MICRO-CONTROLLER PWM GENERATOR

INPUT COMMON MODE NOISE FILTER AND MOV SURGE PROTECTION C ≈ 470pF STYLE 2 & 3 C ≈ 2200pF STYLE 1

MAIN FILTER

3-PHASE INPUTLAMINATED BUS STRUCTURE

U V W

TO LOAD (3-PHASE MOTOR)

S

SNUBBER

S S S

Figure 6.47 Power Circuit Layout for IPMs

CONTROL

PRINTED CIRCUIT

BOARD

SNUBBER CIRCUIT

HEAT SINK

COPPER-INSULATOR-COPPER

SANDWICH

CAPACITOR



Sep.1998

6.8 Handling Precautions forIntelligent Power Modules

Electrical Considerations:

I. Apply proper control voltagesand input signals before statictesting.

II. Carefully check wiring of con-trol voltage sources and inputsignals. Miswiring may destroythe integrated gate control cir-cuit.

III. When measuring leakage cur-rent always ramp the curvetracer voltage up from zero.Ramp voltage back down be-fore disconnecting the device.Never apply a voltage greaterthan the VCES ratingof the device.

IV. When measuring saturationvoltage low inductance test fix-tures must be used. Inductivesurge voltages can exceed de-vice ratings.

Mechanical Considerations:

I. Avoid mechanical shock. Themodule uses ceramic isolationthat can be cracked if the mod-ule is dropped.

II. Do not bend the power termi-nals. Lifting or twisting thepower terminals may causestress cracks in the copper.

III. Do not over torque terminal ormounting screws. Maximumtorque specifications are pro-vided in device data sheets.

IV. Avoid uneven mounting stress.A heatsink with a flatness of0.001"/1" or better is recom-mended. Avoid one sided tight-ening stress. Figure 6.48shows the recommendedtorquing order for mountingscrews. Uneven mounting cancause the modules ceramicisolation to crack.

Thermal Considerations:

I. Do not put the module on a hotplate. Externally heating themodule's base plate at a rategreater than 15°C/min. willcause thermal stress that maydamage the module.

II. When soldering to the signalpins and fast on terminalsavoid excessive heat. The sol-dering time and temperatureshould not exceed 230°C for5 seconds.

III. Maximize base plate toheatsink contact area for goodheat transfer. Use a thermal in-terface compound such aswhite silicon grease. Theheatsink should have a surfacefinish of 64 microinches orless.

Figure 6.48 Mounting Screws Torque Order

2

1

4

1

2

3



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