Mixed Logic Circuit DesignMixed Logic Circuit Design

Benjamin SuanBenjamin Suan

Presentation forPresentation for

High-Speed and Low Power VLSIHigh-Speed and Low Power VLSI

Course: 97.575Course: 97.575

Instructor: Dr. Maitham ShamsInstructor: Dr. Maitham Shams

ContentsContents

IntroductionIntroduction– Background InformationBackground Information

DiscussionDiscussion– Logic style sample comparisonsLogic style sample comparisons– Mixed logic circuit designMixed logic circuit design

Project ProposalProject Proposal– Project time-lineProject time-line

IntroductionIntroduction

Mixed Logic CircuitsMixed Logic Circuits– Relatively new area of researchRelatively new area of research– Circuits composed of more than one logic typeCircuits composed of more than one logic type

Reason to UseReason to Use– Each logic type has different advantages / Each logic type has different advantages /

disadvantagesdisadvantages– By implementing two logics, gain advantages of bothBy implementing two logics, gain advantages of both

Current TrendsCurrent Trends

Industry TrendIndustry TrendLower powerLower power

Higher speedHigher speed

Smaller areaSmaller area

Research TrendResearch TrendRecent papers published in mixed logic designRecent papers published in mixed logic design

Papers focused on PTL / CMOS circuitsPapers focused on PTL / CMOS circuits

BackgroundBackground

Standard CMOS CharacteristicsStandard CMOS CharacteristicsMost commonly used logic in VLSI designMost commonly used logic in VLSI design

Ease of use, well developed synthesis methodsEase of use, well developed synthesis methods

High noise marginsHigh noise margins

Low power consumptionLow power consumption

No static power dissipationNo static power dissipation

Good current driving capabilitiesGood current driving capabilities

Background cont’dBackground cont’d

Pass Transistor Logic CharacteristicsPass Transistor Logic CharacteristicsWidely used alternative to complementary CMOSWidely used alternative to complementary CMOS

Fewer transistors are required for a given functionFewer transistors are required for a given function

Reduced number of transistors means there is Reduced number of transistors means there is lower capacitancelower capacitance

Dedicated buffers need to be inserted to boost Dedicated buffers need to be inserted to boost driving strengthdriving strength

Logic ComparisonLogic Comparison

M. Kontiala, M. Kuulusa and J. Nurmi, “Comparison of Static M. Kontiala, M. Kuulusa and J. Nurmi, “Comparison of Static Logic Styles for Low-Voltage Design” Electronics, Circuits and Logic Styles for Low-Voltage Design” Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Systems, 2001. ICECS 2001. The 8th IEEE International Conference on , Volume: 3 , 2001 Conference on , Volume: 3 , 2001

Logic Comparison cont’dLogic Comparison cont’d

Full Adder ImplementationFull Adder Implementation

Propagation Delay ResultsPropagation Delay Results

Power Dissipation ResultsPower Dissipation Results

Power Delay ProductsPower Delay Products

Discussion of ResultsDiscussion of Results

SCMOS has the best characteristics for SCMOS has the best characteristics for low voltage speed and power dissipation low voltage speed and power dissipation

No real motivation to develop mixed No real motivation to develop mixed circuits with these other types of logiccircuits with these other types of logic

CMOS and PTLCMOS and PTL

CMOS and CPL BehaviorCMOS and CPL Behavior

Results from adder Results from adder simulationsimulation

– CPL has lower power CPL has lower power dissipation across all dissipation across all supply voltagessupply voltages

– CPL has lower delay CPL has lower delay time across all supply time across all supply voltagesvoltages

Mixed PTL/CMOS LogicMixed PTL/CMOS Logic

PTL/CMOS logic circuits will be superior PTL/CMOS logic circuits will be superior

Better area, power and delay compared to Better area, power and delay compared to conventional CMOS or PTLconventional CMOS or PTL

Low power, high performance design Low power, high performance design driven by PTL cell selection and synthesis driven by PTL cell selection and synthesis technique to produce the mixed structuretechnique to produce the mixed structure

Mixed PTL/CMOS ExampleMixed PTL/CMOS Example

Pass-transistor/CMOS Collaborated Logic: The Best Of Both Pass-transistor/CMOS Collaborated Logic: The Best Of Both WorldsWorlds Yamashita, S.; Yano, K.; Sasaki, Y.; Akita, Y.; Chikata, H.; Rikino, Yamashita, S.; Yano, K.; Sasaki, Y.; Akita, Y.; Chikata, H.; Rikino, K.; Seki, K.;K.; Seki, K.; VLSI Circuits, 1997. Digest of Technical Papers., 1997 VLSI Circuits, 1997. Digest of Technical Papers., 1997 Symposium on , 12-14 Jun 1997 Page(s): 31 -32Symposium on , 12-14 Jun 1997 Page(s): 31 -32

Design assigned selector functions to PTLDesign assigned selector functions to PTL

AND/OR logic functions mapped to CMOSAND/OR logic functions mapped to CMOS

Design ExampleDesign Example

Design based on this Boolean equation:Design based on this Boolean equation:

Out1 = B * A’ + C * A ( I’ * F’ + D’ ) *Out1 = B * A’ + C * A ( I’ * F’ + D’ ) * ( D + ( H + E’) * ( E + G ))( D + ( H + E’) * ( E + G ))

Out2 = B’ + ( I’ + F’ + D’ ) *Out2 = B’ + ( I’ + F’ + D’ ) * ( D + ( H + E’) * ( E + G )))’( D + ( H + E’) * ( E + G )))’

Design Example cont’dDesign Example cont’d

Design Example cont’d iiDesign Example cont’d ii

Experimental ResultsExperimental Results

Experimental Results cont’dExperimental Results cont’d

Benchmark simulations show Benchmark simulations show the mixed circuits have better the mixed circuits have better characteristics than pure PTL characteristics than pure PTL or CMOSor CMOS– 20% in area vs. CMOS20% in area vs. CMOS– 40% in power vs. CMOS40% in power vs. CMOS

Design flexibilityDesign flexibility– ↑↑% of PTL, ↓ power but ↑ area% of PTL, ↓ power but ↑ area

Design Project PlanDesign Project Plan

Implement an algorithm in PTLImplement an algorithm in PTL

For mixed logic design, implement MUX For mixed logic design, implement MUX and XOR/XNOR type logic functions in and XOR/XNOR type logic functions in PTL and the remaining functions in Static PTL and the remaining functions in Static CMOSCMOS

Compare and discuss power consumption Compare and discuss power consumption and delayand delay

Design Project Plan cont’dDesign Project Plan cont’d

ScheduleScheduleApril 1 - 12April 1 - 12

Logic Synthesis Technique / Background ResearchLogic Synthesis Technique / Background Research

April 13 – 19April 13 – 19Design Phase / Schematic CaptureDesign Phase / Schematic Capture

April 20 – 30April 20 – 30Simulation / Project PresentationSimulation / Project Presentation

May 1 – 5May 1 – 5Report / DocumentationReport / Documentation

ReferencesReferencesYamashita, S.; Yano, K.; Sasaki, Y.; Akita, Y.; Chikata, H.; Rikino, K.; Seki, K.,Yamashita, S.; Yano, K.; Sasaki, Y.; Akita, Y.; Chikata, H.; Rikino, K.; Seki, K., “Pass- “Pass-transistor/CMOS Collaborated Logic: The Best Of Both Worlds” VLSI Circuits, 1997. transistor/CMOS Collaborated Logic: The Best Of Both Worlds” VLSI Circuits, 1997. Digest of Technical Papers., 1997 Symposium on , 12-14 Jun 1997 Page(s): 31 -32Digest of Technical Papers., 1997 Symposium on , 12-14 Jun 1997 Page(s): 31 -32Geun Rae Cho; Chen, T., “Geun Rae Cho; Chen, T., “On the impact of technology scaling on mixed PTL/static On the impact of technology scaling on mixed PTL/static circuits”circuits” Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on , 2002 IEEE International Conference on , 2002 Page(s): 322 -326Page(s): 322 -326M. Kontiala, M. Kuulusa and J. NurmiM. Kontiala, M. Kuulusa and J. Nurmi, “Comparison of Static Logic Styles for Low-, “Comparison of Static Logic Styles for Low-Voltage Design” Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE Voltage Design” Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on , Volume: 3 , 2001 International Conference on , Volume: 3 , 2001 Geun Rae Cho; Chen, T.; “ Geun Rae Cho; Chen, T.; “ Mixed. PTL/static logic synthesis using genetic algorithms for Mixed. PTL/static logic synthesis using genetic algorithms for low-power applications” low-power applications” Quality Electronic Design, 2002. Proceedings. International Quality Electronic Design, 2002. Proceedings. International Symposium on , 2002 Symposium on , 2002 Page(s): 458 -463Page(s): 458 -463Congguang Yang; Ciesielski, M.,Congguang Yang; Ciesielski, M., “Synthesis for mixed CMOS/PTL logic” “Synthesis for mixed CMOS/PTL logic” Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings , Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings , 2000 Page(s): 750 2000 Page(s): 750 Yano, K.; Yamanaka, T.; Nishida, T.; Saitoh, M.; Shimohigashi, K.; Shimizu, A., “Yano, K.; Yamanaka, T.; Nishida, T.; Saitoh, M.; Shimohigashi, K.; Shimizu, A., “A 3.8 ns A 3.8 ns CMOS 16×16 multiplier using complementary pass transistor logic” Custom Integrated CMOS 16×16 multiplier using complementary pass transistor logic” Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989 , 15-18 May 1989 Page(s): Circuits Conference, 1989., Proceedings of the IEEE 1989 , 15-18 May 1989 Page(s): 10.4/1 -10.4/410.4/1 -10.4/4