mixed-signal vlsi design course code: ee719 department
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Mixed-Signal VLSI DesignCourse Code: EE719
Department: Electrical EngineeringLecture 25: March 08, 2018
Instructor Name: M. Shojaei BaghiniE-Mail ID: [email protected]
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IIT-Bombay Lecture 25 M. Shojaei Baghini
Module 33Two Examples of Subranging ADC
Reference: A16-mW8-Bit1-GS/sDigital-Subranging ADCin55-nmCMOS,Y.Chung,etal.,IEEETrans.onVLSISystems,2015.
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IIT-Bombay Lecture 25 M. Shojaei Baghini
Nyquist ADCs (Clock-based Classification)
Source:B.Murmann 2013
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IIT-Bombay Lecture 25 M. Shojaei Baghini
Example of 8-bit Traditional Subranging ADCNumberofcomparators:31+15=46
NumberofAMUXswitches:16× 31=496496× 2=992forthedifferentialcase
AMUXroutingisthecriticalpathoftheADC.
A16-mW8-Bit1-GS/sDigital-Subranging ADCin55-nmCMOS,Y.Chung,etal.,IEEETrans.onVLSISystems,2015.
1bitRedundancytoimprovetheaccuracy
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IIT-Bombay Lecture 25 M. Shojaei Baghini
8-bit Digital Subranging (Partially Active Flash) ADCA 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS, Y. Chung, et al., IEEE Trans. on VLSI Systems, 2015.
Numberofcomparators:15× 16+16=256
Eachbank:1coarsecomparator15finecomparators
1. 16CCMPSareactivated.2. Onefinebankisactivated.
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IIT-Bombay Lecture 25 M. Shojaei Baghini
Comparator Bank Arrangement with 1-bit Over-range Protection
• TheCADCdeterminesthesubrangeinwhichthesampledinputislocated.
• 1-bitredundancy:TwoFCMPbanks
(32or24FCMPs)areenabledeachtime.
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IIT-Bombay Lecture 25 M. Shojaei Baghini
8-bit Digital Subranging (Partially Active Flash) ADC• Area is compromised.
OnlytheinputneighborhoodCCMPoutputsactivatetheinput-neighborhoodbankcontrollerswhichthenactivatetwoFCMPbanks.
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IIT-Bombay Lecture 25 M. Shojaei Baghini
Module 34Introduction to Successive
Approximation Register (SAR) ADC
Reference: Section 17.2AnalogIntegratedCircuitDesignT.C.Caruson,D.A.JohnsandK.W.Martin,2012
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IIT-Bombay Lecture 25 M. Shojaei Baghini
Nyquist ADCs (Clock-based Classification)
Source:B.Murmann 2013
Performance of Data Converters, 2017Power, Speed, SNDR
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• SAR-basedInterleaving
• SAR-basedpipelining
• CTdelta-sigmawithpipelining
Source:ISSCC2017
IIT-Bombay Lecture 25 M. Shojaei Baghini
Performance of Data Converters, 2017Signal BW and SNDR
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• SAR-basedInterleaving
• SAR-basedpipelining
• CTdelta-sigmawithpipelining
Source:ISSCC2017
IIT-Bombay Lecture 25 M. Shojaei Baghini
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SuccessiveApproximationRegisterADC– BinarySearch
Source:Tutorial1080,UnderstandingSARADCs,MaximIntegrated,2010
IIT-Bombay Lecture 25 M. Shojaei Baghini
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ChargeRedistributionSARADC
• Bitbybitchargeredistribution(orchargescaling)A-to-Dconversion
KenMartin’sbook,2012edition
• SharingcapacitorsforT&H,chargescalingDACandestablishingVin – Vout,DACSmallsignalanalysis
IIT-Bombay Lecture 25 M. Shojaei Baghini
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SuccessiveApproximationRegisterADC(Holdmode,Establishingthefirstcomponentof
subtraction)
KenMartin’sbook,2012edition
Smallsignalanalysis
IIT-Bombay Lecture 25 M. Shojaei Baghini
Prof. Maryam S. Baghini, Department of Electrical Engineering, IIT-Bombay 9
SuccessiveApproximationRegisterADC(Subtraction)
KenMartin’sbook,2012edition
Smallsignalanalysis
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FactorsAffectingSpeedandAccuracyinSARADC• Slow(bitatatime)
• Delayofeachconversioncycle- SettlingtimeoftheDAC,delayofthecomparatorandcontrollogicdelay(it’sasimplelogic)• Comparatorresolution• ComparatoroffsetcontributestotheADCoffset.• DACnonlinearityisthemainfactorindeterminingtheSARADCnonlinearity.• DACandcomparatornoisecontributetotheADCnoise.
IIT-Bombay Lecture 25 M. Shojaei Baghini
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IIT-Bombay Lecture 25 M. Shojaei Baghini
End of Lecture 25