[VIDYARTHIPLUS.COM] February 16, 2013

B.E./B.Tech. DEGREE EXAMINATION, MAY/JUNE 2012

Sixth Semester

Electronics and Communication Engineering

EC 2354/EC 64 VLSI DESIGN

(common to PTEC 2354 VLSI DESIGN for B.E. (part time) fifth semester

electronics and communication engineering regulation 2009 )

(regulation 2008)

TIME : THREE HOURS MAX:100 MARKS

ANSWER ALL QUESTIONS

PART-A (10 X 2 = 20)

1. DRAW THE IV CHARACTERISTICS OF MOS TRANSISTOR.

2. BREIF THE DIFFERENT OPERATING REGIONS OF MOS SYSTEM.

3. DRAW THE EQUIVALENT CIRCUIT STRUCTURE OF LEVEL 1 MOSFET MODEL

IN SPICE.

4. BRIEF ABOUT THE VARIATION OF FRINGING FIELD FACTOR WITH THE

INTERCONNECT GEOMETRY.

5. COMPARE CMOS COMBINATIONAL LOGIC GATES WITH REFERENCE TO THE

EQUIVALENT N-MOS DEPLETION LOAD LOGIC WITH REFERENCE TO THE

AREA REQUIREMENT.

6. WHAT ARE THE ADVANTAGE OF USING A PSEUDO N-MOS GATE INSTEAD

OF A FULL CMOS GATE

7. WHAT ARE THE FACTORS THAT CAUSE TIMING FAILURES?

8. WHAT ARE THE ADVANTAGE OF A SINGLE STUCK AT FAULT?

9. WITH COMPONENT INSTANTITATION, WRITE A VHDL PROGRAM FOR A

BUFFER.

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10. WRITE A NOTE ON TRANSPORT DELAY

PART-B (10 X 2 = 20) 11. (a) DISCUSS IN DETAIL ABOUT:

(1) FULL-CUSTOM MASK LAYOUT DESIGN (8)

(2) CMOS INVERTER LAYOUT DESIGN (8)

[OR]

(b) (I) WITH A NEAT DIAGRAM DISCUSS IN DETAIL ABOUT DC TRANSFER

CHARACTERISTICS OF CMOS. (8)

(II) WRITE A SHORT NOTES ON THE FOLLOWING ALONG WITH THE MASK

VIEW

(i) OXIDE RELATED CAPACITANCE (4)

(ii) JUNCTION CAPACITANCE (4)

12. (a) (i) OBTAIN AN EXPRESSION FOR LEVEL 2 MODEL EQUATION OF MOSFET

IN SPICE. (8)

(ii) DISCUSS IN DETAIL ABOUT:

(1) VARIATION OF MOBILITY WITH ELECTRIC FIELD.

(2) VARIATION OF CHANNEL LENGTH IN SATURATION MODES.

(3) SATURATION OF CARRIER VELOCITY. (8)

[OR]

(b)(i) HOW DO THE SPICE MOSFET MODEL ACCOUNT FOR THE PARASITIC

DEVICE CAPACITANCES?(8)

(ii) EXPLAIN THE CHARECTERIZATION OF CIRCUITS.(8)

13. (a) (i)FOR A TWO INPUT NAND GATE DERIVE AN EXPRESSION FOR THE DRAIN

CURRENT. (8)

(ii) DRAW A CMOS NOR2 GATE AND ITS COMPLEMENTARY OPERATION

WITH NECESSARY EQUATIONS. (4)

(iii) OBTAIN A CMOS LOGIC DESIGN REALIZING THE BOOLEAN FUNCTION

Z=A(D+E)+BC (8)

[OR]

(b) (i) DRAW A CIRCUIT DIAGRAM OF THE CMOS SR LATCH AND EXPLAIN

IN DETAIL. (8)

(ii) ALONG WITH THE NECESSARY INPUT AND OUTPUT WAVEFORMS

OF THE CMOS DFF NEGATIVE EDGE TRIGGERED MASTER SLAVE D FLIP

FLOP. (8)

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14. (a) (i) EXPLAIN INDETAIL ABOUT PARTITION AND MUX TESTING WITH

NECESSARY EXAMPLE AND DIAGRAM. (8)

(ii) EXPLAIN THE PRINCIPLE OF SILICON DEBUG. (8)

[OR]

(b) (i) ELABORATE THE SCAN BASED TECHNIQUES. (8)

(ii) DISCUSS IN DETAIL ABOUT:

(I) PSEUDO RANDOM PATTERN GENERATOR. (4)

(II) OUTPUT RESPONSE ANALYSER. (4)

15. (a) USING MIXED LEVEL MODE WRITE A VHDL PROGRAM FOR A

(i) COMPARATOR. (8)

(ii) D FLIP FLOP. (8)

[OR]

(b) WITH ALL THE THREE TYPES OF MODELING WRITE A VHDL

PROGRAM FOR A

(i) DECODER (8)

(ii) FULL ADDER. (8)

[VIDYARTHIPLUS.COM] February 16, 2013

ANSWER KEY:

PART A:

1. Vgs

Vgs=constant

Ids (ms)

2.

Ans : Cut-off region , linear region , saturation region .

3.

Ans :

+ + + +

n+ P+ P+

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4.

Ans : Capacitance due to fringing field effects is the major component of the overall capacitance of inter connect wires. For the final line metallization, the value of fringing field capacitance will be the same order as that of the area capacitance.

5.

Ans : For CMOS, the area required is 533 m2 , for pseudo Nmos the area required is 288 m2.

6.

Ans : Ratioed circuits dissipate power continually in certain states and have poor noise margin than complementary circuits.

Ratioed circuits used in situations where smaller area is needed.

7.

Ans : Temperature , large of interconneccts.

8.

Ans : Faults are modeled at transistor level. At this level only , the complete circuit structure is known.

9.

Ans : These are having one input and more outputs

Buf

Not

Syntax :

gate type [instance na,e] (out1 , out2 , .outN , input)

eg:

buf buffer(out1 , out2 , clk)

[VIDYARTHIPLUS.COM] February 16, 2013

out1 clk

buf out2

10.

Ans : It models the delays in hardware that do not exhibit any inertial delay. It represents pure propagation delay.