ml506 dsp hardware co-simulation · 2008-10-05 · ml506 dsp hardware co-simulation with xilinx...
TRANSCRIPT
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ML506 DSP Hardware Co-Simulationwith Xilinx System Generator for DSP 10.1i SP2
August 2008
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ML506 Overview• ML506 Board• Setup
– Software Requirements– Network Setup– Hardware Setup– CompactFlash Setup
• System Generator Hardware Co-Simulation• Available Documentation
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ML506 Board
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Additional Setup Details• Refer to ml505_overview_setup document for details on:
– Software Requirements– ML505 Board Setup
• Equipment and Cables• Software• Network
– Terminal Programs• This presentation requires the
9600-8-N-1 Baud terminal setup
Note: The ML505 overview presentation covers the ML506 board
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ISE Software Requirement• Xilinx ISE 10.1i SP2 software
Note: Presentation applies to the ML505, ML506, and ML507
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CORE Generator Requirement• Xilinx CORE Generator 10.1i IP Update 2
Note: Presentation applies to the ML506
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Sysgen Software Requirement• Xilinx Sysgen 10.1i
Note: Presentation applies to the ML506
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Matlab Software Requirement• Matlab is a third party software, available from Mathworks
– Matlab R2008a
Note: Presentation applies to the ML506
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WinPcap Software Requirement• As stated in the System Generator User’s Guide, pg. 215,
WinPcap is required for Co-simulation– www.winpcap.org Version 4.0 or higher
Note: Presentation applies to the ML506
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Network Setup• A Gigabit Ethernet Adapter on your PC is required• In the Network Connections, right-click on the Ethernet
Adapter and select Properties (1)
1
Note: Presentation applies to the ML506
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Network Setup• Set your host (PC) to this IP Address:
Note: Presentation applies to the ML506
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Network Setup• Click Configure (1)
– Set the Flow Control to Auto
1
Note: Presentation applies to the ML506
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Network Setup• Set Speed & Duplex to Auto
Note: Presentation applies to the ML506
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Network Setup• Set the Ethernet PHY jumper settings
– This presentation requires GMII/MII– Set J22, J23 to positions 1-2 (as shown)– Refer to the ML505/506 User Guide – UG347, page 28-29 for details
Note: Presentation applies to the ML506
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Network Setup• Connect an Ethernet cable from the ML506 to the PC’s
Ethernet Adapter
Note: Presentation applies to the ML506
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Software Setup• Select Start → All Programs → Xilinx ISE Design Suite 10.1 → DSP_Tools → Select MATLAB version for Xilinx System Generator
• Select Matlab version R2008a
Note: Presentation applies to the ML506
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Software Setup• Select Start → All Programs → Xilinx ISE Design Suite 10.1 → DSP_Tools → Xilinx System Generator 10.1
Note: Presentation applies to the ML506
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Hardware Setup• Use a CompactFlash reader to mount a
CompactFlash as a disk drive• Delete all files in this CompactFlash
Note: Presentation applies to the ML506
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Hardware Setup• Open Matlab and type this command to update the CompactFlash:
unzip(fullfile(xlFindSysgenRoot,'plugins/bin/ML506_sysace_cf.zip'), '<CF Drive Letter>:\')
Note: Presentation applies to the ML506
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Hardware Setup• These files should appear on your CompactFlash• Eject the CompactFlash from your PC
Note: Presentation applies to the ML506
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CompactFlash Setup• Insert the CompactFlash fully into the CompactFlash slot on
the ML506 board
Note: Presentation applies to the ML506
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Hardware Setup• Set Front DIP Switches
to 10010101• Power on the ML506
Note: In some cases, you may need to press the CPU reset if the network doesn’t connect
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Open DSP Example• From Matlab R2006b, select Help → Demos
Note: Presentation applies to the ML506
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Open DSP Example• Select Blocksets → Xilinx → More demos and Examples → Local
Examples (1) and click on the User’s Guide link (2)
2
1
Note: Presentation applies to the ML506
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Open DSP Example• Scroll down to the DSP section and select the FIR filter using
the DSP48 Macro block and click on “Open this model” (1)
1
Note: Presentation applies to the ML506
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DSP48 Macro• Model appears as seen below
Note: If this file is write protected, save as a new name or make it writable
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Move the input• Click once on the net marked “Input” and press the delete key
Note: Presentation applies to the ML506
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Move the input• The net from the Sine wave to the adder input should still be connected
Note: Presentation applies to the ML506
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Move the input• Drag a connection from the scope (1) to the net after the adder (2)
1
2
Note: Presentation applies to the ML506
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Move the input• Double click this new net and name it “Input_with_Noise” (1)
Note: Presentation applies to the ML506
1
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Generate Block• Right click the System Generator Block and select Open Block (1)
1
Note: Presentation applies to the ML506
1
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Generate Block• Select Compilation : Hardware Co-
simulation > ML506 > Ethernet > Point-to-point (1)
1
Note: Presentation applies to the ML506
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Generate Block• Click Generate (1)
1
Note: Presentation applies to the ML506
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Generated DSP48 Block• After compilation, a new window with the generated DSP
Hardware block appears– Note: The order of the output pins varies from the top to bottom
order in the model; pay attention to this when making connections
Note: Presentation applies to the ML506
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Add DSP48 Block• Drag block from library window to original dsp48 window
Note: Presentation applies to the ML506
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Add DSP48 Block• Click on the Simulink button in Matlab
Note: Presentation applies to the ML506
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Add DSP48 Block• In the Simulink Library Browser under Simulink → Discrete, right click on the
Discrete filter and add it to the dsp48macro_macfir• Also add an Integer Delay, a Scope, and two Sum blocks
Note: The Scope and Sum blocks can be fond under Commonly Used Blocks
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Configure Scope• Double-click on Scope1, click the parameters button (1) and set the number
of Axes to 6 (2)
Note: The Scope and Sum blocks can be fond under Commonly Used Blocks
1
2
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Configure Scope• Double-click on Discrete Filter1, set the numerator coefficient to fir1(15,0.5),
and the Denominator coefficient to 1
Note: Presentation applies to the ML506
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Configure Scope• Double-click on Sum3 and Sum4 blocks, and set the list of signs to |+-
Note: Presentation applies to the ML506
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Connect as Shown
Note: Presentation applies to the ML506
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Run Hardware Co-simulation• Double click on the dsp48macro_macfir hwcosim block
Note: Presentation applies to the ML506
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Run Hardware Co-simulation• Under the Ethernet tab, select the desired Ethernet
Connection
Note: Presentation applies to the ML506
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Run Hardware Co-simulation• Under the Configuration tab, select Point-to-point Ethernet
– Click OK
Note: Presentation applies to the ML506
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Output Waveforms• Right Click on Scope and
select Open Block• Repeat for Scope1• Both should show no waveforms• Click Dock Scope (small down
arrow) on both (1)
1
Note: Presentation applies to the ML506
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Output Waveforms• In the Matlab window, click Undock Figures (small up arrow) (1)
1
Note: Presentation applies to the ML506
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Output Waveforms• Figures Window set to
side-by-side display
Note: Presentation applies to the ML506
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Simulate the FIR Filter
Note: Presentation applies to the ML506
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Output Waveforms• Click Autoscale for
both scopes (1)• The waveforms
should be identical
1
Note: Presentation applies to the ML506
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Documentation• Virtex-5
– Silicon Deviceshttp://www.xilinx.com/products/silicon_solutions
– Virtex-5 Multi-Platform FPGAhttp://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5
– Virtex-5 Family Overview: LX, LXT, SXT, and FXT Platformshttp://www.xilinx.com/support/documentation/data_sheets/ds100.pdf
– Virtex-5 FPGA DC and Switching Characteristics Data Sheethttp://www.xilinx.com/support/documentation/data_sheets/ds202.pdf
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Documentation• Virtex-5
– Virtex-5 FPGA User Guidehttp://www.xilinx.com/support/documentation/user_guides/ug190.pdf
– Virtex-5 FPGA Configuration User Guidehttp://www.xilinx.com/support/documentation/user_guides/ug191.pdf
– Virtex-5 System Monitor User Guidehttp://www.xilinx.com/support/documentation/user_guides/ug192.pdf
– Virtex-5 Packaging and Pinout Specificationhttp://www.xilinx.com/support/documentation/user_guides/ug195.pdf
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Documentation• Virtex-5 RocketIO
– RocketIO GTP Transceivershttp://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/RocketIO_GTP.htm
– RocketIO GTX Transceivers http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/RocketIO_GTX.htm
– RocketIO GTP Transceiver User Guide – UG196http://www.xilinx.com/support/documentation/user_guides/ug196.pdf
– RocketIO GTX Transceiver User Guide – UG198http://www.xilinx.com/support/documentation/user_guides/ug198.pdf
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Documentation• Design Resources
– ISE Development Tools and IPhttp://www.xilinx.com/ise
– Integrated Software Environment (ISE) Foundation Resourceshttp://www.xilinx.com/ise/logic_design_prod/foundation.htm
– ISE Manualshttp://www.xilinx.com/support/software_manuals.htm
– ISE Development System Reference Guidehttp://toolbox.xilinx.com/docsan/xilinx10/books/docs/dev/dev.pdf
– ISE Development System Libraries Guidehttp://toolbox.xilinx.com/docsan/xilinx10/books/docs/virtex5_hdl/virtex5_hdl.pdf
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Documentation• Additional Design Resources
– Customer Supporthttp://www.xilinx.com/support
– Xilinx Design Services: http://www.xilinx.com/xds
– Titanium Dedicated Engineering: http://www.xilinx.com/titanium
– Education Services: http://www.xilinx.com/education
– Xilinx On Board (Board and kit locator): http://www.xilinx.com/xob
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Documentation• Platform Studio
– Embedded Development Kit (EDK) Resourceshttp://www.xilinx.com/edk
– Embedded System Tools Reference Manualhttp://www.xilinx.com/support/documentation/sw_manuals/edk10_est_rm.pdf
– EDK Concepts, Tools, and Techniqueshttp://www.xilinx.com/ise/embedded/edk92i_docs/edk_ctt.pdf
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Documentation• PowerPC 440
– PowerPC 440 Processorhttp://www.xilinx.com/powerpc
– Embedded Processor Block in Virtex-5 FPGAs Reference Guide – UG200http://www.xilinx.com/support/documentation/user_guides/ug200.pdf
– PPC440 Virtex-5 Wrapper – DS621http://www.xilinx.com/support/documentation/ip_documentation/ppc440_virtex5.pdf
– DDR2 Memory Controller for PowerPC 440 Processors – DS567http://www.xilinx.com/support/documentation/data_sheets/ds567.pdf
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Documentation• MicroBlaze
– MicroBlaze Processorhttp://www.xilinx.com/microblaze
– MicroBlaze Processor Reference Guide – UG081http://www.xilinx.com/support/documentation/sw_manuals/mb_ref_guide.pdf
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Documentation• ChipScope Pro
– ChipScope Pro 10.1i Serial IO Toolkit User Manualhttp://www.xilinx.com/ise/verification/chipscope_pro_siotk_10_1_ug213.pdf
– ChipScope Pro 10.1i ChipScope Pro Software and Cores User Guidehttp://www.xilinx.com/ise/verification/chipscope_pro_sw_cores_10_1_ug029.pdf
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Documentation• Memory Solutions
– Demos on Demand – Memory Interface Solutions with Xilinx FPGAs http://www.demosondemand.com/clients/xilinx/001/page_new2/index.asp#35
– Xilinx Memory Cornerhttp://www.xilinx.com/products/design_resources/mem_corner
– Additional Memory Resourceshttp://www.xilinx.com/support/software/memory/protected/index.htm
– Xilinx Memory Interface Generator (MIG) 2.1 User Guidehttp://www.xilinx.com/support/software/memory/protected/ug086.pdf
– Memory Interfaces Made Easy with Xilinx FPGAs and the Memory Interface Generatorhttp://www.xilinx.com/support/documentation/white_papers/wp260.pdf
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Documentation• Ethernet
– Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper Data Sheethttp://www.xilinx.com/support/documentation/ip_documentation/v5_emac_ds550.pdf
– Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper Getting Started Guidehttp://www.xilinx.com/support/documentation/ip_documentation/v5_emac_gsg340.pdf
– Virtex-5 Tri-Mode Ethernet Media Access Controller User Guidehttp://www.xilinx.com/support/documentation/user_guides/ug194.pdf
– LightWeight IP (lwIP) Application Examples – XAPP1026http://www.xilinx.com/support/documentation/application_notes/xapp1026.pdf
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Documentation• PCIe
– LogiCORE Endpoint Block Plus for PCI Express Data Sheethttp://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_ds551.pdf
– LogiCORE Endpoint Block Plus for PCI Express Designshttp://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_ug341.pdf
– LogiCORE Endpoint Block Plus Getting Started Guide for PCI Express Designshttp://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_gsg343.pdf
– Virtex-5 Integrated Endpoint Block User Guide for PCI Express Designshttp://www.xilinx.com/support/documentation/user_guides/ug197.pdf
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Documentation• System Generator
– System Generator for DSPhttp://www.xilinx.com/sysgen
– Xilinx System Generator for DSP User Guideshttp://www.xilinx.com/support/documentation/sw_manuals/sysgen_bklist.pdf
– XtremeDSP Design Considerationshttp://www.xilinx.com/support/documentation/user_guides/ug193.pdf
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Documentation• PLB v4.6 IP
– Processor Local Bus (PLB) v4.6 Data Sheet – DS531http://www.xilinx.com/support/documentation/ip_documentation/plb_v46.pdf
– Multi-Port Memory Controller (MPMC) – DS643http://www.xilinx.com/support/documentation/ip_documentation/mpmc.pdf
– XPS Multi-CHannel External Memory Controller (XPS MCH EMC) – DS575http://www.xilinx.com/support/documentation/ip_documentation/xps_mch_emc.pdf
– XPS LocalLink TEMAC – DS537http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf
– XPS LocalLink FIFO – DS568http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_fifo.pdf
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Documentation• PLB v4.6 IP
– XPS IIC Bus Interface – DS606http://www.xilinx.com/support/documentation/ip_documentation/xps_iic.pdf
– XPS SYSACE (System ACE) Interface Controller – DS583http://www.xilinx.com/support/documentation/ip_documentation/xps_sysace.pdf
– XPS Timer/Counter – DS573http://www.xilinx.com/support/documentation/ip_documentation/xps_timer.pdf
– XPS Interrupt Controller – DS572http://www.xilinx.com/support/documentation/ip_documentation/xps_intc.pdf
– Using and Creating Interrupt-Based Systems Application Notehttp://www.xilinx.com/support/documentation/application_notes/xapp778.pdf
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Documentation• PLB v4.6 IP
– XPS General Purpose Input/Output (GPIO) – DS569http://www.xilinx.com/support/documentation/ip_documentation/xps_gpio.pdf
– XPS External Peripheral Controller (EPC) – DS581http://www.xilinx.com/support/documentation/ip_documentation/xps_epc.pdf
– XPS 16550 UART – DS577http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdf
– PLBV46 to DCR Bridge Data Sheet – DS578http://www.xilinx.com/support/documentation/ip_documentation/plbv46_dcr_bridge.pdf
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Documentation• IP
– Local Memory Bus Data Sheet – DS445http://www.xilinx.com/support/documentation/ip_documentation/lmb_v10.pdf
– Block RAM Block Data Sheet – DS444http://www.xilinx.com/support/documentation/ip_documentation/bram_block.pdf
– Microprocessor Debug Module Data Sheet – DS641http://www.xilinx.com/support/documentation/ip_documentation/mdm.pdf
– LMB Block RAM Interface Controller Data Sheet – DS452http://www.xilinx.com/support/documentation/ip_documentation/lmb_bram_if_cntlr.pdf
– Device Control Register Bus (DCR) v2.9 Data Sheet – DS406http://www.xilinx.com/support/documentation/ip_documentation/dcr_v29.pdf
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Documentation• IP
– JTAGPPC Controller Data Sheet – DS298http://www.xilinx.com/support/documentation/ip_documentation/jtagppc_cntlr.pdf
– Processor System Reset Module Data Sheet – DS402http://www.xilinx.com/support/documentation/ip_documentation/proc_sys_reset.pdf
– Clock Generator v2.0 Data Sheet – DS614http://www.xilinx.com/support/documentation/ip_documentation/clock_generator.pdf
– Util Bus Split Operation Data Sheet – DS484http://www.xilinx.com/support/documentation/ip_documentation/util_bus_split.pdf
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Documentation• ML505/506/507
– ML505 Overviewhttp://www.xilinx.com/ml505
– ML506 Overviewhttp://www.xilinx.com/ml506
– ML507 Overviewhttp://www.xilinx.com/ml507
– ML505/506/507 Evaluation Platform User Guide – UG347http://www.xilinx.com/support/documentation/boards_and_kits/ug347.pdf
– ML505/506/507 Getting Started Tutorial – UG348http://www.xilinx.com/support/documentation/boards_and_kits/ug348.pdf
– ML505/506/507 Reference Design User Guide – UG349http://www.xilinx.com/support/documentation/boards_and_kits/ug349.pdf
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Documentation• ML505/506/507
– ML505/506/507 Schematicshttp://www.xilinx.com/support/documentation/boards_and_kits/ml50x_schematics.pdf
– ML505/506/507 Bill of Materialhttp://www.xilinx.com/support/documentation/boards_and_kits/ml505_501_bom.xls