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MNRL and MNCaRTAn Open-Source, Multi-Architecture State Machine Research and Execution Ecosystem
Kevin Angstadt† Jack Wadden‡ Vinh Dang‡ Ted Xie‡ Dan Kramp‡
Westley Weimer† Mircea Stan‡ Kevin Skadron‡
†University of Michigan ‡University of Virginia{angstadt, weimerw}@ umich.edu {wadden, vqd8a, ted.xie, dankramp, mircea, skadron}@ virginia.edu
What is Automata Processing?
I Finite automata are state machines thatmatch patterns of data within an inputdata stream
I Theoretical model used to model andprocess regular expressions
I Able to accelerate a broad range ofapplications: natural languageprocessing, network security, graphanalytics, high-energy physics,bioinformatics, pseudo-random numbergeneration and simulation, data-mining,and machine learning.
The MNCaRT Philosophy
I Previous research and tools werefractured by different file formats andrestrictive licenses
I The MNRL Network Computation andResearch Testbed aims to open-sourcethe end-to-end toolchain
I All tools operate on common file formatI Languages, Compilers, and RuntimesI Support for all major architectures
MNRL: A Unified Representation
I MNRL Network Representation LanguageI Flexible, JSON-based language for
representing state machinesI MNRL file defines a collection of state
machines (network) consisting of one ormore nodes
I Direct support for validation of filesI APIs for both C++ and PythonI Easy to extend for experimental
automata node types
MNCaRT Ecosystem
PCRE RAPIDHigh-Level
Languages ANMLZoo
Benchmarks
MNRL ANMLState Machine
Representations
hscompile AutomataLab VASim ATR REAPR apcompile
AnalysisCompilation
Transformation
HyperscanCPU
Engine
VASimCPU
EngineDFAGE iNFAnt2
GPU Engines
FPGAEngine
MicronD480 AP
Execution
Engines
CPU Engines
I Hyperscan: state-of-the-art regularexpression processing engine, extendedto support MNRL networks
I VASim: supports execution of customautomata designs with experimentalnode types and collection of runtimestatistics and profiles
GPU Engines
I Support for both DFA(DFAGE) and NFA(iNFAnt2) executionon Cuda-enabled graphics cards
I Supports the study of trade-offs betweenthe two execution models
REAPR FPGA Engine
I MNRL networks arecompiled to a custommodule for execution onFPGAs (logic-basedfabrics of LUTs and memory)
I Input/Output handled by Xilinx’s SDAccelFramework
Micron D480 AP
I Prototype architecturefor execution ofautomata
I Memory arrays used as computationalmedium
I Supported by converting MNRL to ANMLrepresentation
Automata Lab
Languages and Benchmarks
I Perl Compatible Regular ExpressionsI RAPID: High-level language for defining
inexact pattern matchesI ANMLZoo: Benchmark suite of diverse
automata and regular expressions withassociated input workloads
VASim & Automata-to-Routing
I Supports transformation, optimization,and execution of finite automata
I Prototype and test new automatadesigns and computational styles
I Experiment with place and routealgorithms for customspatial-reconfigurable architectures
Acknowledgements
This work was supported in part by grants from the NSF (CCF-1116673,CCF-1629450, CCF-1619123, CNS-1619098), AFRL (FA8750-15-2-0075),Jefferson Scholars Foundation, Achievement Rewards for College Scientists(ARCS) Foundation, a grant from Xilinx, and support from C-FAR, one of sixcenters of STARnet, a Semiconductor Research Corporation programsponsored by MARCO and DARPA. Any opinions, findings and conclusions orrecommendations expressed in this material are those of the authors and donot necessarily reflect the views of AFRL.
https://bit.ly/CAP-MNCaRT