mobile web processor

DATASHEET

NVIDIA® TEGRA™ 200 Series Mobile Web Processor Description The NVIDIA® Tegra™ 200 Series Mobile Web Processor (MWP) introduces a new generation of performance for desktop like browsing and 1080p full HD media playback in sleek mobile devices that also offer cell-phone like battery life. An extensive set of peripheral interfaces enables communication with all necessary external devices, minimizes system BOM and enables compact form factor design.

The Tegra 200 series MWP couples best in class processing and multimedia capabilities with advanced power management technology to provide an uncompromised mobile experience. Dedicated 2D, 3D, audio and high definition video processing capabilities enable unobstructed access to the content that mobile users desire while using only a fraction of the power previously required. The high level of integration enables system level tuning that unleashes high-end computing and processing power when needed, and is able to reduce power consumption and maximize battery life by turning off un-used blocks.

TEGRA | 200 SERIES | DATASHEET | DP-04508-001_v05 | ADVANCE INFORMATION – SUBJECT TO CHANGE | NVIDIA CONFIDENTIAL

Tegra 200 Series Mobile Web Processor

TEGRA | 200 SERIES | DATASHEET | DP-04508-001_v05 | ADVANCE INFORMATION – SUBJECT TO CHANGE | NVIDIA CONFIDENTIAL 2

FeaturesDual-core ARM® Cortex -A9 MPCore™ Processor, up to 1.0 GHz > L1 caches

Core 0 32KB L1 I-cache Core 0 32KB L1 D-cache Core 1 32KB L1 I-cache Core 1 32KB L1 D-cache

> 1MB L2 unified cache > TrustZone technology support

Memory Subsystem > 32-bit LPDDR2-600 > 32-bit DDR2-667 without termination > Supports Up to 1 GB > Secure external memory access using TrustZone technology

HD Video Decode > H.264

Baseline Profile (B frames) – 1080p Main Profile (B Frames, CAVLC) – 1080p Main Profile (B Frames, CABAC, no weighted prediction) – 1080p High Profile (B Frames, CABAC, no weighted prediction) – 1080p

> WMV9/VC-1 (Simple, Main and Advanced Profiles) – 1080p > MPEG-4 (Simple, B frames and ASP Profiles) – 1080p > H.263 (Profile 0) – D1 > DiVX (DiVX 4/5) – 1080p > XviD (XviD Home Theater) – 1080p > MPEG-2 (MP @ ML) – D1 > JPEG – up to 80 Mpixel per second

HD Video Encode > H.264 (Baseline Profile) – 1080p > MPEG-4 (Simple Profile) – 720p > H.263 (Profile 0) – D1 > JPEG – up to 80 Mpixel per second

Audio Processor > Audio Formats Supported (decode)

AAC-LC, AAC+, eAAC+ AMR-WB, AMR-NB WMA7, WMA8, WMA9, and WMA10 MP3 PCM/WAV SBC

> Audio Formats Supported (encode) AAC-LC AMR-WB, AMR-NB PCM/WAV SBC

Ultra-low Power NVIDIA® GeForce® GPU > OpenGL® ES 2.0 > Peak Triangle Rate: 71 million triangles per second > Peak Fill Rate (with Z-reject): 1200 million pixels per second > Programmable pixel shader > Programmable vertex and lighting > CSAA support > 2K x 2K texture and 4K x 4K render resolutions supported > Advanced 2D and vector engine Display Controller Subsystem > Two independent display controllers > Supports LCD interfaces up to WSXGA+ (1680 x 1050) > Supports HDMI 1.3 (HDTV) output up to 1080p > Supports CRT (Analog RGB) output up to UXGA (1600 x 1200) > SPI-based smart-panel interface > MIPI DSI interface with 2-lane support

Imaging System > Integrated ISP > Raw (Bayer) input up to 12 Mpixels > 2 MIPI CSI interfaces (1 with 2-lane support) > 8-bit/10-bit/12-bit digital video input port

Clocks > System clock: 12, 13, 19.2, or 26 MHz > Sleep clock: 32 KHz > Dynamic clock scaling > Dynamic clock source selection

Boot Sources > Raw SLC or MLC NAND (ONFI 2.1, Asynchronous mode only) > eMMC > eSD > MuxOneNAND / Flex-MuxOneNAND > LBA/mobile LBA > Sync-NOR > SPI serial flash > USB (Recovery Mode)

Security > Secure memories to store 2x8 keys > Hardware acceleration for AES encryption and decryption to be used for secure boot

and multimedia Digital Rights Management (DRM) > 128-bit eFuse

Storage Interfaces > Enhanced IDE (EIDE) > NAND flash:

Support for up to eight chip selects ECC corrections

> NOR flash > 4 SD/MMC controllers (supporting SD, MMC, HS-MMC, and SDIO)

Peripheral Interfaces > 2 USB 2.0 OTG interfaces with integrated PHY > 1 USB 2.0 interface

Support for ULPI and HSIC > 5 High-speed UART interfaces > 4 SPI interfaces > 4 I2C controllers:

3 generic 1 dedicated power management

> 2 enhanced audio controllers supporting I2S, left-justified, right-justified PCM TDM (multi-slot mode)

> S/PDIF (Sony-Philips Digital Interface I/O) > 5 DAP ports

Physical interface to external audio device Crossbar switch between the different DAPs and internal controllers

> PCI Express (PCIe) 4 lanes (1x4, 2x2, 2x1) > AC’97 controller > PWM Controllers (4 channels and up to 8 bits) > TWC (three-wire controller) > One-wire interface > Keypad scan matrix (up to 16 x 8)

Baseband Interfaces > HSIC > HS-UART > MIPI-HSI > PCM support > SPI (master and slave) > ULPI

Package > Tegra 250

664 Ball FCBGA, 23x23 mm, 0.8 mm pitch Process: 40 nm LPG TSMC

> HF and RoHS Compliant

Applications > Smartbooks, Tablets, Potable Media Players, Portable Navigation Devices, Internet

TV, and more


Revision History Version Date Description

v01 JUN 12, 2009 Initial Release

v02 JUL 31, 2009 Power Management section updated Display Controller section obsoleted and removed

v03 SEP 8, 2009 Display Controller section reviewed and updated Keyboard Controller: added minimum allowable configuration requires at least 2 rows be used NAND Flash Controller: updated LL_PTR size USB Complex: B-Host Enable (BHEN) obsoleted and removed I2C Controller: updated Programming repeat_start/stop and Error Handling

v04 NOV 17, 2009 GMI section added AHB: updated Memory Pre-Fetcher description APB:

> APB_MISC_PP_STRAPPING_OPT_A_0: updated strapping options > APB_MISC_PP_PIN_MUX_CTL_H_0: register obsolete and removed CPU: added CPU Timer GPIO Controller: added details on controllers, ports, and pins SD/MMC Controller: added programming guidelines Minor edits to the following section: CSI, I2C Controller, PWFM Controller

v05 MAR 03, 2010 DC Characteristics updated Thermal Specification added Pin name changes to comply with USB certification requirements: AE14 changed from USB1_ID to ACC1_DETECT; AF15 changed from USB3_ID to ACC3_DETECT; AH15 USB3_VBUS changed to DNC. General description and feature list brought to front Added part numbering information to Package Marking



Terms and Definitions

Term Definition Term Definition A/D Analog-to-Digital NB Narrow Band

AAC Advanced Audio Coding NTSC National Television System Committee, defines a television standard used in the USA and elsewhere.

AC’97 AC’97 Audio Codec

OTG On The Go, an extension of USB enabling USB peripherals to communicate directly with one another without intervention by a PC.

ADC Analog-to-Digital Converter PAL Phase Alternating Line, defines a television standard common in Europe

AMR Adaptive Multi-rate PCM Pulse-code Modulation

AVP Audio-video Processor PD Pull-down

BIST Built-in Self test PHY Physical Layer

BOM Bill of Materials PIO Programmed Input Output

BSE Bit Stream Engine PLL Phase-lock Loop

CODEC Coder-Decoder PMU Power Management Unit

D/A Digital-to-Analog POR Power-on Reset

DAP Digital Audio Port Pro LBR Pro Low Bit-rate (for WMA)

DDR Double Data Rate PU Pull-up

DMA Direct Memory Access RTC Real Time Clock

DVC Dynamic Voltage Control SBC Sub-band Coding

DVFS Dynamic Voltage and Frequency Scaling SDIO Secure Digital Input Output

EMC External Memory Controller SDRAM Synchronous Dynamic Random Access Memory

eMMC Embedded MMC (embedded storage solution with MMC interface, and flash memory and controller)

SDTV Standard Definition Television

FWVGA Full Wide VGA (854 x 480 resolution SFIO Special Function I/O

GPIO General Purpose Input/Output SLC Single Level Cell

GPU Graphics Processor Unit SoC System on a Chip

HD AVP High-Definition Audio-video Processor S/PDIF SONY/Philips Digital Interconnect Format

HDMI High-Definition Multimedia Interface SPI Serial Peripheral Interface

HS-MMC High-Speed Multimedia Card TFE Transform Function Engine

HSYNC Horizontal Sync Pulse TWC Three-wire Controller

I2C Philips Inter-IC multimaster bus ULP Ultra-low Power

I2S Philips Inter-IC sound bus USB Universal Serial Bus

iRAM Internal Random Access Memory VCP Vector Coprocessor

ISDB-T Integrated Services Digital Broadcasting-Terrestrial, the Japanese format for digital TV broadcast.

VFIR Very Fast Infrared

JTAG Joint Test Action Group VI Video Input

LPDDR Low Power DDR VSYNC Vertical Sync Pulse

MC Memory Controller WAV Waveform Audio Format

MCE Motion Compensation Engine WB Wide Band

MIDI Musical Instrument Digital Interface WMA Windows Media Audio

MLC Multiple Level Cell XBAR Cross Bar

MMC Multimedia Card XMB External Memory Bus

MSelect Memory Select XTAL Crystal



Table of Contents 1.0 Functional Description....................................................................................................................................................................................... 7

1.1 Power Management Overview ..................................................................................................................................................................... 8

1.1.1 Power Domains/Islands ........................................................................................................................................................... 8

1.1.2 Power Management Controller (PMC) and Real Time Clock (RTC) Block ..................................................................................... 9

1.2 Clock Overview ............................................................................................................................................................................................ 9

1.3 High-definition Audio-video Processing (HD AVP) Subsystem .................................................................................................................... 9

1.4 Display Controller ....................................................................................................................................................................................... 10

1.5 Ultra Low-power (ULP) GeForce® Graphics Processing ........................................................................................................................... 10

1.6 Video Input (VI) .......................................................................................................................................................................................... 10

1.7 Baseband Interfaces .................................................................................................................................................................................. 11

1.8 PCIe Bridge ................................................................................................................................................................................................ 11

1.9 Peripherals ................................................................................................................................................................................................. 11

1.9.1 I2C ....................................................................................................................................................................................... 11

1.9.2 I2S/PCM Audio ...................................................................................................................................................................... 11

1.9.3 Keyboard Controller (KBC) ..................................................................................................................................................... 11

1.9.4 PWFM .................................................................................................................................................................................. 12

1.9.5 Sony/Philips Digital Interconnect Format (SPDIF) .................................................................................................................... 12

1.9.6 SPI ...................................................................................................................................................................................... 12

1.9.7 UART ................................................................................................................................................................................... 12

1.9.8 USB ..................................................................................................................................................................................... 13

2.0 Device Compliance ......................................................................................................................................................................................... 14

3.0 Signal Pinout ................................................................................................................................................................................................... 15

3.1 Ball Map ..................................................................................................................................................................................................... 15

3.2 Signal List and Multiplexing Functions ....................................................................................................................................................... 23

3.3 Signal Description ...................................................................................................................................................................................... 45

3.3.1 Clock, Power & Reset Signals ................................................................................................................................................. 45

3.3.2 Memory Signals .................................................................................................................................................................... 45

3.3.3 Display Signals ..................................................................................................................................................................... 47

3.3.4 Audio Interfaces ................................................................................................................................................................... 48

3.3.5 Storage Interface Signals ...................................................................................................................................................... 49

3.3.6 USB and Baseband Interfaces ................................................................................................................................................ 50

3.3.7 Inter-chip Interfaces ............................................................................................................................................................. 51

3.3.8 Video Input Interfaces .......................................................................................................................................................... 53

3.3.9 Miscellaneous Interfaces ....................................................................................................................................................... 53

3.3.10 Power, Ground and Reserved............................................................................................................................................... 54

4.0 DC Characteristics .......................................................................................................................................................................................... 57

4.1 Absolute Maximum Ratings ....................................................................................................................................................................... 57

4.2 Recommended Operating Conditions ........................................................................................................................................................ 58

4.3 DC Characteristics ..................................................................................................................................................................................... 59

4.4 Power-up Ramp Time Requirement ........................................................................................................................................................... 59




5.0 AC Characteristics .......................................................................................................................................................................................... 61

5.1 Clocking Specifications .............................................................................................................................................................................. 61

5.1.1 32KHz Clock Input Timing ..................................................................................................................................................... 61

5.1.2 External Reference Clock Input Timing ................................................................................................................................... 61

5.1.3 Crystal Connection & Selection .............................................................................................................................................. 62

5.2 Display Controller ....................................................................................................................................................................................... 63

5.2.1 RGB Interface ....................................................................................................................................................................... 63

5.2.2 Parallel CPU Type Interface ................................................................................................................................................... 64

5.2.3 Serial CPU Type Interface ...................................................................................................................................................... 66

5.3 Video Input ................................................................................................................................................................................................. 68

5.3.1 Parallel Interface .................................................................................................................................................................. 68

5.3.2 Reference Clock Output ......................................................................................................................................................... 69

5.4 Audio .......................................................................................................................................................................................................... 70

5.4.1 I2S, PCM and TDM Timing ..................................................................................................................................................... 70

5.4.2 AC97 Timing ......................................................................................................................................................................... 71

5.5 Memory Cards and SDIO Peripherals Timing ............................................................................................................................................ 72

5.5.1 HS-MMC Controller ................................................................................................................................................................ 72

5.5.2 SDIO .................................................................................................................................................................................... 73

5.6 HSI ............................................................................................................................................................................................................. 74

5.7 I2C Interface ............................................................................................................................................................................................... 75

5.8 Serial Peripheral Interface (SPI) ................................................................................................................................................................ 76

5.9 JTAG .......................................................................................................................................................................................................... 78

6.0 Power Sequencing .......................................................................................................................................................................................... 79

6.1 Power-up Sequence ................................................................................................................................................................................... 79

6.2 Deep Sleep Entry Sequence ...................................................................................................................................................................... 81

6.3 Deep Sleep Exit Sequence ........................................................................................................................................................................ 81

6.4 Power-down Sequence .............................................................................................................................................................................. 81

7.0 Package Description ....................................................................................................................................................................................... 83

7.1 Thermal Specification ................................................................................................................................................................................. 83

7.2 Package Marking ....................................................................................................................................................................................... 84

7.3 Package Drawing & Dimensions ................................................................................................................................................................ 85

Tegra 200 Series Mobile web Processor


1.0 Functional Description The NVIDIA® Tegra™ 200 Series Mobile web Processor (MWP) is a complete applications and digital media system built around the following processing elements:

Dual-core ARM® Cortex-A9 MPCore™ processor

HD AVP (2.0) High-definition Audio-video processor The HD AVP Processor handles audio-video processing and supports H.264, VC-1, and MPEG-4 video standards. High definition video playback and capture are accelerated with dedicated hardware. Baseline JPEG encoding and decoding are also supported.

Ultra Low-power NVIDIA® GeForce® Graphics Processing (ULP GeForce GPU) The ULP GeForce GPU handles 2D graphics rendering and 3D pixel and vertex shading.

Imaging System Accepts still images in Bayer and YUV formats, converts the various input formats, and writes the data to memory as indicated by software.

Display Controller Complex The Display Controller Complex contains dual display controllers with various external interface options for LCD panels, CRTs, and televisions, including HDMI output at 1080p.

In addition to its processing elements, an extensive set of peripheral interfaces enables communication with all necessary external devices. This high level of integration minimizes system BOM and enables compact form factor design.

Figure 1 Block Diagram

PWFM

AHB Data

Bridge

SPDIF

VCP

iRAMMEMORY

AVPARM7

DDR2 / LP-DDR2

MULTI-MASTER, AMBA HIGHSPEED BUS (AHB)

NAND Flash Controller

MIPI HSI

TWC (Three-wire)

LCDout

8 NAND devices

VI

LCDout

AHB DMA Controller

Camera Sensor(Serial)

CSI (x2)

Display Display

CRTout

Serialdisplay

RGBMIPI DSI

Camera Sensor

(Parallel) HDMIport

Graphics Memory Interface

I2S/PCM Audio (x2)

PMC

RTC

KBC

ISP2D3DVideo

EncoderEPP

AC’97

NOR Flash Controller

HOST

32-bit

CPU 0Cortex-A9

D-cache I-cache

CPU 1Cortex-A9

D-cache I-cache

SCU (Snoop Control), BIU (Bus Interface)

L2 Cache

AD muxed sync NOR

Video Decoder

EMC

Real Time ClockPower Block

DAS

UART (x5)(VFIR)

SPI Master/Slave (x4)

I2C Master/Slave (x4)

OWR (One-wire)

AM

BA

PER

IPH

ER

IAL B

US

(AP

B)

HDMI

Interrupt Controller

SD/MMCController

(x4)

APB BridgeAPB DMA Controller

USB2USB2 PHY

SD/SDIO/MMC bus

SPI Flash mem/Serial TSSPI Flash / DTV

SPI Peripherals

Cache

AXI cif

CR

OS

SB

AR

PR

OC

ES

SO

R D

ATA

BU

S

AXI/Xbar Bus Bridge

Color Legend:

AVP Subsystem

Display Processor

VI & Associated modules

ULP GPU

Peripherals/External Devices

CPU Blocks

MEMORY Controller

PCIeRoot Portx4 Lane

MSelect

EIDE Hard Disk

DAP(x5)

USB2

Host/device

USB2

IC-USB

ULPIHSIC

USB2 PHY

Host/device

Tegra 200 Series Mobile Web Processor Functional Description


1.1 Power Management Overview The Tegra 200 series MWP utilizes various means to provide an efficient power management solution for a complex environment. Hardware and software work together to deliver an optimized system to monitor and control power use: raising voltages or clock frequencies when demand requires, lowering them when less is sufficient, and removing them when none is needed.

1.1.1 Power Domains/Islands The Tegra 200 series MWP is partitioned into power domains and power islands to optimize mobile device standby time (by limiting leakage current) and to reduce power consumption for different use cases.

Figure 2 Power Domains Diagram

The Tegra 200 series MWP has three power domains (RTC/CORE/CPU) which can be turned on and off. The CORE power domain contains 6 power-gated islands (TD/VE/MPE/VDE/L2/PCX) and 1 Non-Power-Gated island (NPG). The NPG modules are clock-gated (Off) when not used, to reduce unnecessary power consumption.

Table 1 Power Domains

Power Domain Power Island in Domain Modules in Power Island

RTC N/A

PMC (Power Management Controller)

KBC (Keyboard Controller)

RTC (Real Time Clock)

CORE

NPG (Non-Power-Gated) AVP, 2D, Display, IRAM, Memory Controller (MC/EMC), L1 Cache

TD 3D

VE ISP, VI, CSI

MPE Video Encode

VDE Video Decode

L2 L2 Cache

PCX PCI Express

CPU CPU MPCore, MSelect



1.1.2 Power Management Controller (PMC) and Real Time Clock (RTC) Block The PMC provides an interface to an external power manager IC or PMU. It incorporates power management features that enable both high speed operation and very low-power standby states. The PMC primarily acts as a controller, transitioning the Tegra MWP to/from different low power modes; it also acts as a slave receiving commands via an I2C interface as well as dedicated power/clock request signals. Other power-management functions, such as power gating, are inherent to the Tegra 200 series MWP and are not controlled by the PMC.

The RTC power block includes an embedded real-time clock and can wake the system based on either a timer event or an external trigger (e.g., key press or USB attach). The PMC integrates specific logic to maintain defined states and control power domains (including signaling the external PMU to provide power) during sleep and deep sleep modes.

1.2 Clock Overview The Tegra 200 series MWP supports a large number of internal functional blocks and external interfaces. To accommodate all clocking requirements, the clock generation block requires two clock sources as inputs:

32 KHz external clock: Required by the Real Time Clock (RTC) and Power Management Controller (PMC), typically provided by the Power Management Unit (PMU).

Oscillator (OSC) clock: This higher frequency reference clock feeds several integrated PLLs that provide a variety of clocking options for the many core and I/O blocks.

Oscillator Clock

Two methods of generating the internal Oscillator clock are supported. Normal Oscillation Mode (on-chip oscillator) with crystal connected to XTAL_IN and XTAL_OUT, and Bypass Mode (external clock source). In both modes, the frequencies supported are 12MHz, 13MHz, 19.2MHz, or 26MHz.

1.3 High-definition Audio-video Processing (HD AVP) Subsystem The HD AVP module uses a dedicated ARM7 processor to off-load audio and video processing activities from the Cortex-A9 CPUs resulting in faster, more efficient AVP.

Video Decoder

The Video Decoder extends the ARM7 processing power by adding support for low resolution mobile content, and by including Standard Definition (SD) and High Definition (HD) profiles. The Video Decoder is also capable of baseline JPEG decoding and encoding.

Video Encoder

The Video Encoder works in conjunction with a host interface to perform high-quality video encoding operations for mobile applications such as video recording and video conferencing. The encode engine is designed to be extremely power-efficient without sacrificing performance.

Audio

Audio processing was designed to accelerate multiple audio standards. It also supports other audio applications like re-sampling, reverberation, FFT computations, and 3D audio. A DMA engine transfers input, coefficient data, and output data from memory; and performs vector addition, subtraction and multiplication. Audio processing supports several new features, such as command parsing and better DMA control that together release the HD AVP from almost any intervention during normal audio playback.



1.4 Display Controller The Tegra 200 series MWP integrates two independent display controllers. Each display controller is capable of providing an interface to external devices such as LCDs, CRTs, or HDTV. Each controller supports a cursor and three windows (Window A, B, and C).

The display controller reads rendered graphics or video frame buffers in memory, blends them and sends them to the display. Support for direct TFT or TFT-like interfaces enable connection to most LCD displays.

Display Serial Interface (DSI)

DSI support enables both display controllers to connect to an external display(s) with a MIPI DSI receiver. The DSI transfers pixel data from the internal display controller to an external third-party LCD module.

High-Definition Multimedia Interface (HDMI)

HDMI support provides a unified method of transferring both video and audio data over a TMDS-compatible physical link to an audio/visual display device.

1.5 Ultra Low-power (ULP) GeForce® Graphics Processing The NVIDIA ULP GeForce module accelerates 2D graphics rendering, and 3D pixel and vertex shading.

2D

The 2D Engine provides all relevant low-level 2D composition functionality including alpha blending, a StretchBlt function, video scaling, anti-aliasing and image rotation.

3D

The 3D Engine is a fully programmable 3D graphics core supporting the OpenGL ES 2.0 rendering model. Its geometry and pixel processing performance make it highly suitable for rendering advanced user interfaces and complex gaming applications.

1.6 Video Input (VI) The Video Input receives raw signals from CMOS sensors and converts these to YUV data; removes common artifacts of digital CMOS image sensors and lenses from these signals; and interpolates alternating, one-color-per-pixel Bayer-formatted data into full RGB color signals. VI supports advanced processing features at all stages, from lens correction through color-space conversion. The imaging system is comprised of the following major components:

Image Signal Processing (ISP)

Video Input processing (VI)

MIPI CSI Controller (CSI)

ISP includes a two-level (horizontal and vertical) low-pass filtering scheme that is used to reduce color artifacts and the effects of image sampling. A down-scaler enables the ability to receive images which would not normally show completely given the resolution of the display panel in use.



1.7 Baseband Interfaces The Tegra 200 series MWP supports multiple interfaces for baseband interconnections:

MIPI-HSI

HS-UART

HSIC

SPI (master and slave)

ULPI

PCM to Baseband Digital Audio Port (DAP)

MIPI Baseband High Speed Synchronous Serial Interface

The Mobile Industry Processor Interface High-Speed Synchronous Serial Interface (MIPI HSI) is an interface that connects the Tegra 200 series MWP to a cellular modem ASIC. It is fundamentally a point-to-point interface providing peer-to-peer communication between the two devices. Both devices can independently send data to the other peer.

1.8 PCIe Bridge The Tegra 200 series MWP integrates a x4 lane PCIe bridge to enable a control path from the Tegra chip to external PCIe devices. It supports PCIe 2.0 in single (x4 lane) or dual (x2 lane) mode enabling connections to one or two endpoints. When connecting to two endpoints (dual mode), the PCIe bridge requires the PCIe lanes to be split between two controllers, each controlling half of the PCIe lanes (x2). The PCIe bridge also enables peer-to-peer transactions between both endpoints.

1.9 Peripherals

1.9.1 I2C The Tegra 200 series MWP supports a subset of I2C features. A general purpose I2C controller allows system expansion for I2C-based devices, such as AM/FM radio, remote LCD display, serial ADC/DAC, and serial EPROMs, as defined in the Philips inter-IC-bus (I2C) specification. The I2C bus supports serial device communications to multiple devices. The I2C controller handles bus mastership with arbitration, clock source negotiation, speed negotiation for standard and fast devices, and 7-bit and 10-bit slave address support according to the I2C protocol.

1.9.2 I2S/PCM Audio The I2S Controller transports streaming audio data between system memory and an audio codec. The controller supports I2S format, Left-justified Mode format, Right-justified Mode format, and DSP mode format, as defined in the Philips inter-IC-sound (I2S) bus specification.

The I2S controller supports point-to-point serial interfaces for the I2S digital audio streams. I2S-compatible products, such as compact disc players, digital audio tape devices, digital sound processors, and those with digital TV sound may be directly connected to the I2S controller. The controller also supports the PCM and telephony mode of data-transfer. Pulse-Code-Modulation (PCM) is a standard method used to digitize audio (particularly voice) patterns for transmission over digital communication channels. The Telephony mode is used to transmit and receive data to and from an external mono CODEC in a slot-based scheme of time-division multiplexing. The Tegra 200 series I2S controller supports bidirectional audio streams. It can operate in half-duplex or full-duplex mode.

1.9.3 Keyboard Controller (KBC) The KBC is used to interface with an external keypad; the number of pins used in KBC depends on the external keypad row and column count. KBC lowers the burden of software and reduces the power consumption in keypad associated operations by supporting keypad scan, debounce and wake-up on any key-press in hardware. Any unused KBC pins can be used as GPIO. This module is a slave on AMBA Peripheral Bus (APB).



1.9.4 PWFM The Pulse Width Frequency Modulator (PWFM) is a frequency divider with a varying pulse width. The PWFM runs at 24 MHz, getting divided by 256 before being subdivided based on a programmable value. The PWFM has 4 pulse width frequency generators. An APB interface transports the PWFM’s register logic to the APB bus.

1.9.5 Sony/Philips Digital Interconnect Format (SPDIF) The SPDIF interface supports both professional and consumer applications. When used in a professional application, the interface is primarily intended to carry monophonic or stereophonic programs, at a 48 kHz sampling frequency and with a resolution of up to 24-bits per sample; it may alternatively be used to carry signals sampled at 32 kHz or 44.1 kHz. When used in a consumer application, the interface primarily carries stereophonic programs with a resolution of up to 20-bits per sample. If used for other purposes, the interface normally carries audio data coded as other than linear PCM-coded audio samples. The interface may also carry data related to computer software or signals coded using non-linear PCM.

The Tegra 200 series SPDIF implementation supports:

Five data formats: 16-bit, 20-bit, 24-bit, Raw, 16-bit packed

Flexible clock divisor for use to generate different "spdifout" data rate

Autolock Mode to automatically detect the "spdifin" sample rate and lock onto the data stream

Override Mode to provide a manual control to sample the "spdifin" data stream

Loopback Mode to route the "spdifout" back to "spdifin" for self-testing

SPDIFIN (Rx) / SPDIFOUT (Tx)

- 16-word data FIFO for storage of incoming/outgoing audio data

- 4-word user FIFO for storage of incoming/outgoing user data

- 6-word page buffer for storage of incoming/outgoing channel status

1.9.6 SPI The SPI Controller provides an interface to SPI-capable devices such as Flash memories and ADC/DAC devices. The SPI Controller works as a master on the SPI bus. It has independent transmit and receive FIFOs that are used by software to generate commands on the SPI bus. Software programs the controller to generate transactions of required packet length on the SPI bus. It can use APB DMA to read and write from the FIFOs as required. At the end of each transaction, an interrupt is generated (if enabled).

The Tegra 200 series supports SPI master/slave controllers operating up to 33 Mbps. It allows a duplex, synchronous, serial communication between the controller and external peripheral devices. It consists of 4 signals, SS_N (Chip select), SCK (clock), MOSI (Master data out and Slave data in) and MISO (Slave data out and master data in). The data is transferred on MOSI or MISO based on the data transfer direction on every SCK edge. The receiver always receives the data on the other edge of SCK.

1.9.7 UART The UART performs the main tasks in serial communications with either peripherals or other processors by converting parallel information to serial data for sending on a communication line.

Start and stop bits in the transmit data provide a data character for synchronizing serial data streams. A parity bit attached to the data character supports data integrity. The receiver checks the parity bit for any transmission bit errors.

The COM-HOST interface is fully programmable through an 8-bit CPU interface which supports word lengths from five to eight bits, an optional parity bit, and one or two stop bits. If enabled, parity can be odd, even, or forced to a defined state. Interrupts can be generated from any of ten sources.



The UARTs support both 16450 (default) and 16550-compatible modes. This mode provides independent 16-byte FIFOs for transmit and receive, selectable by means of a FIFO control register, and includes a 16-bit programmable baud rate generator, an 8-bit scratch register, eight modem control lines, and two DMA handshake lines that are used to indicate when the FIFOs are ready to transfer data to the CPU.

1.9.8 USB USB is a popular mechanism for accessing external peripherals and transferring power to charge a mobile device’s battery. The Tegra 200 series USB module utilizes plug-type detection and either provides access to external peripherals (MOSI) or allows an external PC to communicate with the Tegra device (MISO).



2.0 Device Compliance Tegra 200 series devices comply with the following specifications:

USB Specification, version 2.0, plus the following:

- USB Battery Charging Specification, version 1.0

- Modes: Host and Device

- Speeds: Low, Full, and High

High-Definition Multimedia Interface (HDMI) Specification, version 1.3a

Macrovision Revision 7.1L1 specification for NTSC and PAL B/D/G/H/I standards for composite and Y/C video output applications.1

High-bandwidth Digital Content Protection (HDCP System Specification, version 1.3

DSI Specification: D-PHY v1.00; DSI v1.01; DCS v1.01

- MIPI Alliance Standard for Display Serial Interface, Version 1.01.00

- MIPI Alliance Standard for Display Command Set, Version 1.01.00

- MIPI Alliance Specification for D-PHY, Version 1.00.00

CSI Specification: D-PHY v1.00; CSI-2 v1.01

- MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2), Version 1.01.00

- MIPI Alliance Specification for D-PHY, Version 1.00.00

ITU-R BT. 601/656 specification

MMC Specification, version 4.3 (for HS-MMC)

SD/SDIO 2.1 Card Product Specification

Open NAND Flash Interface (ONFI)Specification, Revision 2.1 (Asyncronous mode only)

RoHS Specification

1 Macrovision enabled devices can only be sold or distributed to buyers with a valid and existing authorization from Macrovision to purchase and incorporate Macrovision enabled devices into buyers’ products. Macrovision enabled devices are protected by U.S. patent numbers 5,583,936; 6,516,132; 6,836,549; and 7,050,698 and other intellectual property rights. The use of Macrovision’s copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited.


3.0 Signal Pinout This section details each signal location, multiplexing functions (if applicable), and provides a brief signal description.

3.1 Ball Map

Ball Map Legend

Power (VDD_ , VDDIO_ , AVDD_ ) Keyboard, Power, System (VDDIO_SYS)

Ground (GND) NAND (VDDIO_NAND)

Do Not Connect (DNC) UART (VDDIO_UART)

Baseband (VDDIO_BB)

Video Input (VDDIO_VI)

Audio (VDDIO_AUDIO)

LCD (VDDIO_LCD)

DDR, JTAG, SPI Flash (VDDIO_DDR)

SDIO (VDDIO_SDIO)

PCIE (AVDD_PEX, VDD_PEX)

MIPI (AVDD_MIPI)

HDMI (AVDD_HDMI)

VDAC (AVDD_VDAC)

HSIC (AVDD_HSIC)

USB (AVDD_USB)

Crystal Oscillater (AVDD_OSC)


Tegra 200 Series Mobile Web Processor Signal Pinout

Table 2 Ball Map

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

A GND GND KB_COL6 KB_COL2 KB_COL0 KB_ROW11 KB_ROW9 KB_ROW4 KB_ROW2 TEST_MODE_EN JTAG_TRST_N JTAG_RTCK DDR_QUSE2 DDR_A0 DDR_CKE0 DDR_A9 DDR_BA1 DDR_A8 GND GND A

B GND GND KB_COL5 GND KB_COL3 KB_ROW15 GND KB_ROW12 KB_ROW8 GND KB_ROW5 KB_ROW1 GND CLK_32K_IN JTAG_TDI GND JTAG_TCK DDR_QUSE3 GND DDR_A3 DDR_ODT0 GND DDR_RAS_N DDR_BA2 GND DDR_BA0 GND GND B

C PWR_I2C_SCL PWR_I2C_SDA KB_COL7 KB_COL4 KB_ROW14 KB_ROW13 KB_ROW7 KB_ROW6 KB_ROW0 CPU_PWR_REQ JTAG_TDO JTAG_TMS DDR_A12 DDR_A11 DDR_CKE1 DDR_CS1_N DDR_A1 DDR_A5 DDR_A6 DDR_A14 C

D GND GND CLK_32K_OUT KB_COL1 SYS_CLK_REQ KB_ROW10 DDR_DM3 DDR_DQS3P KB_ROW3 DDR_DQ14 DDR_DQ15 PWR_INT_N DDR_DQ9 DDR_DQ13 SYS_RESET_N DDR_DQ2 DDR_DQS0N DDR_A2 DDR_DQ6 DNC DDR_A10 DDR_DQ21 GND GND D

E GPIO_PU2 XTAL_OUT XTAL_IN UART3_CTS_N GPIO_PU4 THERMD_N GND DDR_COMP_PU DDR_DQ27 GND DDR_DQS3N DDR_DQ26 GND DDR_DQ11 DDR_DM1 GND DDR_DQ8 DDR_DQ1 GND DDR_DQS0P DDR_DQ5 GND DDR_DQ23 DDR_DQS2N DDR_CS0_N DDR_CLK DDR_CLK_N DDR_A13 E

F UART3_RTS_N UART3_RXD UART3_TXD UART2_RXD UART2_CTS_N GPIO_PU3 THERMD_P DDR_COMP_PD DDR_DQ24 DDR_DQ28 DDR_DQ30 DDR_DQ25 DDR_DQ12 DDR_DQS1N DDR_DQS1P DDR_DQ10 DDR_DQ4 DDR_DQ3 DDR_DM0 DDR_DQ0 DDR_DQ7 DDR_DQ20 DDR_DQ16 DDR_DQS2P DDR_DQ17 DDR_A4 DDR_WE_N DDR_A7 F

G GND GPIO_PU1 GND UART2_RTS_N DDR_DQ29 DDR_DQ31 OWR PLL_S_PLL_LF CORE_PWR_REQ DDR_QUSE0 DDR_QUSE1 VDDIO_SYS DNC DNC DDR_DM2 GND DDR_DQ19 GND G

H DAP4_DIN DAP4_SCLK DAP4_FS GPIO_PU5 GEN1_I2C_SDA GEN1_I2C_SCL UART2_TXD GND VDD_CPU GND VDDIO_UART AVDD_OSC GND AVDD_PLLA_P_C AVDD_PLLM GND VDD_DDR_RX GND GND VDDIO_DDR GND DDR_DQ18 VI_D0 DDR_DQ22 VI_D1 DDR_CAS_N CAM_I2C_SDA CAM_I2C_SCL H

J GPIO_PU0 GPIO_PU6 DAP3_FS DAP4_DOUT SDIO1_CMD GPIO_PV3 GPIO_PV1 VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDDIO_DDR VDDIO_DDR VDDIO_DDR VDDIO_DDR VDDIO_DDR VDDIO_DDR VDDIO_DDR VDDIO_DDR VDDIO_DDR VDDIO_DDR VI_GP4 VI_D2 VI_D4 VI_D6 VI_D7 VI_D5 VI_D3 J

K GND SDIO1_DAT1 GND SDIO1_DAT0 GND VDD_CPU VDDIO_DDR GND VI_D8 GND VI_VSYNC GND K

L DAP3_DOUT DAP3_DIN ULPI_DATA3 ULPI_DATA4 SDIO1_DAT3 ULPI_DATA5 AVDD_PLLX GND VDD_CPU GND GND GND GND GND VDDIO_DDR VDDIO_DDR GND VDDIO_DDR VDDIO_VI VI_GP0 VI_D10 VI_MCLK VI_HSYNC VI_D9 VI_GP5 VI_PCLK L

M ULPI_NXT ULPI_CLK ULPI_DIR DAP3_SCLK SDIO1_DAT2 SDIO1_CLK DNC VDDIO_BB VDD_CPU VDD_CPU GND VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDDIO_DDR VDDIO_DDR VDDIO_DDR DNC VI_D11 VI_GP3 VI_GP6 SPI2_MISO SPI1_MOSI SPI1_CS0_N SPI1_SCK M

N GND ULPI_DATA2 GND ULPI_DATA7 GND VDD_CPU_SENSE VDD_CPU VDD_CPU GND GND VDD_CORE GND GND VDDIO_DDR VDDIO_DDR GND SPDIF_OUT GND SPI2_MOSI GND N

P VDDIO_SDIO GPIO_PV0 ULPI_STP ULPI_DATA0 ULPI_DATA6 ULPI_DATA1 GPIO_PV4 AVDD_PEX_PLL GND_CPU_SENSE VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CORE VDD_CORE GND GND VDDIO_DDR VDDIO_AUDIO SPI2_CS1_N SPI2_CS0_N SPI2_SCK DAP1_SCLK SPI1_MISO DAP_MCLK1 SPI2_CS2_N P

R SDIO3_CMD SDIO3_CLK SDIO3_DAT0 SDIO3_DAT3 SDIO3_DAT6 GPIO_PV6 GPIO_PV5 AVDD_PEX AVDD_PEX GND VDD_CPU VDD_CPU GND GND VDD_CORE GND GND VDDIO_DDR DNC DAP2_FS DAP2_SCLK DAP_MCLK2 SPDIF_IN DAP1_DIN DAP1_FS DAP1_DOUT R

T GND SDIO3_DAT4 GND SDIO3_DAT5 GND AVDD_PEX GND GND VDD_CORE GND VDD_CORE VDD_CORE GND GND VDDIO_DDR GND DAP2_DOUT GND DAP2_DIN GND T

U PEX_REFCLKN PEX_REFCLKP SDIO3_DAT1 SDIO3_DAT2 DNC GPIO_PV2 SDIO3_DAT7 VDD_PEX VDD_PEX GND GND VDD_CORE VDD_CORE GND VDD_CORE VDD_CORE GND VDDIO_DDR GND VDDIO_LCD LCD_DE LCD_PWR1 LCD_D12 LCD_D15 LCD_D14 LCD_D13 U

V PEX_TSTCLKN PEX_TSTCLKP PEX_L2_RXP PEX_L2_RXN PEX_L3_RXP PEX_L3_RXN DNC VDDIO_PEX_CLK VDD_PEX GND VDD_RTC VDD_RTC GND GND GND VDD_CORE VDD_CORE VDDIO_DDR GND VDDIO_LCD HDMI_INT_N LCD_CS0_N LCD_D22 LCD_D17 LCD_D16 LCD_PCLK V

W GND DNC GND PEX_TERMP GND VDD_TP VDD_CORE GND DDC_SCL GND LCD_SDIN GND W

Y AVDD_PLLE PEX_L3_TXP PEX_L3_TXN PEX_CLK_OUT2_N PEX_CLK_OUT2_P DNC VDDIO_NAND VDDIO_NAND VDDIO_NAND GND_TP GND GND GND AVDD_USB AVDD_HDMI AVDD_DSI_CSI GND_CORE_SENSE VDD_CORE_SENSE VDD_CORE VDD_CORE VDD_CORE CRT_HSYNC DDC_SDA LCD_M1 LCD_D9 LCD_D6 LCD_D7 LCD_D8 Y

AA PEX_L2_TXN PEX_L2_TXP DNC PEX_L0_RXP PEX_L0_RXN PEX_L1_RXP PEX_L1_RXN GND GND GND VGND_TP AVDD_HDMI_PLL GND AVDD_USB AVDD_HDMI GND AVDD_DSI_CSI AVDD_PLLU GND VDD_CORE GND LCD_D21 LCD_D19 LCD_PWR2 LCD_SDOUT LCD_D0 LCD_D11 LCD_D10 AA

AB GND DNC GND DNC VDDIO_HSIC AVDD_IC_USB AVDD_USB_PLL GMI_CS5_N VPP_KFUSE VPP_FUSE VDAC_R VDAC_G CSI_CLKBN LCD_SCK LCD_D20 GND LCD_D18 GND AB

AC PEX_L1_TXP PEX_L1_TXN DNC PEX_CLK_OUT1_N GMI_AD22 GMI_CS3_N GMI_RST_N GMI_AD27 GMI_DPD GMI_IORDY GMI_AD25 GMI_CS4_N DNC USB1_DN HSIC_DATA USB_REXT VDAC_VREF HDMI_TXD1N GND CSI_CLKBP DSI_CLKAP LCD_D23 CRT_VSYNC LCD_DC1 LCD_CS1_N LCD_D1 LCD_D2 LCD_D3 AC

AD PEX_L0_TXN PEX_L0_TXP GMI_AD17 PEX_CLK_OUT1_P GMI_CS6_N GEN2_I2C_SDA GND GMI_AD20 GMI_CS7_N GND GEN2_I2C_SCL GMI_CS2_N GND USB1_DP HSIC_STROBE GND USB1_VBUS HDMI_TXD1P GND CSI_D1AN DSI_CLKAN GND LCD_DC0 LCD_PWR0 LCD_D4 LCD_VSYNC LCD_HSYNC LCD_D5 AD

AE GND GND GMI_AD18 GMI_AD8 GMI_AD21 GMI_AD24 GMI_AD1 GMI_AD26 GMI_AD23 GMI_AD9 IC_REXT ACC1_DETECT HSIC_REXT HDMI_TXD0N HDMI_TXD0P VDAC_RSET VDAC_B CSI_D1AP DNC DNC DNC LCD_WR_N GND GND AE

AF GMI_WAIT GMI_WP_N GMI_CLK GMI_CS0_N GMI_WR_N GMI_AD7 GMI_AD6 GMI_AD2 GMI_CS1_N IC_DN ACC3_DETECT HDMI_TXCN HDMI_RSET DSI_D1AN DSI_CSI_RUP DNC DNC DNC DNC DNC AF

AG GND GND GMI_AD13 GND GMI_AD0 GMI_AD3 GND GMI_AD19 GMI_OE_N GND GMI_AD5 GMI_AD16 GND IC_DP USB3_DP GND HDMI_TXCP HDMI_TXD2P GND DSI_D1AP DSI_D2AP GND CSI_D2AP CSI_D1BP GND CSI_CLKAP GND GND AG

AH GND GND GMI_ADV_N GMI_AD15 GMI_AD11 GMI_AD4 GMI_AD14 GMI_AD12 GMI_AD10 DNC USB3_DN AVDD_VDAC HDMI_TXD2N DSI_CSI_RDN DSI_D2AN CSI_D2AN CSI_D1BN CSI_CLKAN GND GND AH

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28



Table 3 provides a reference list of signal names sorted by ball number.

Table 3 Signal List (by Ball Number)

Ball # Signal Name

A1 GND

A2 GND

A3 KB_COL6

A5 KB_COL2

A6 KB_COL0

A8 KB_ROW11

A9 KB_ROW9

A11 KB_ROW4

A12 KB_ROW2

A14 TEST_MODE_EN

A15 JTAG_TRST_N

A17 JTAG_RTCK

A18 DDR_QUSE2

A20 DDR_A0

A21 DDR_CKE0

A23 DDR_A9

A24 DDR_BA1

A26 DDR_A8

A27 GND

A28 GND

B1 GND

B2 GND

B3 KB_COL5

B4 GND

B5 KB_COL3

B6 KB_ROW15

B7 GND

B8 KB_ROW12

B9 KB_ROW8

B10 GND

B11 KB_ROW5

B12 KB_ROW1

B13 GND

B14 CLK_32K_IN

B15 JTAG_TDI

B16 GND

B17 JTAG_TCK

Ball # Signal Name

B18 DDR_QUSE3

B19 GND

B20 DDR_A3

B21 DDR_ODT0

B22 GND

B23 DDR_RAS_N

B24 DDR_BA2

B25 GND

B26 DDR_BA0

B27 GND

B28 GND

C1 PWR_I2C_SCL

C2 PWR_I2C_SDA

C3 KB_COL7

C5 KB_COL4

C6 KB_ROW14

C8 KB_ROW13

C9 KB_ROW7

C11 KB_ROW6

C12 KB_ROW0

C14 CPU_PWR_REQ

C15 JTAG_TDO

C17 JTAG_TMS

C18 DDR_A12

C20 DDR_A11

C21 DDR_CKE1

C23 DDR_CS1_N

C24 DDR_A1

C26 DDR_A5

C27 DDR_A6

C28 DDR_A14

D2 GND

D4 GND

D5 CLK_32K_OUT

D6 KB_COL1

D7 SYS_CLK_REQ

D8 KB_ROW10

Ball # Signal Name

D9 DDR_DM3

D10 DDR_DQS3P

D11 KB_ROW3

D12 DDR_DQ14

D13 DDR_DQ15

D14 PWR_INT_N

D15 DDR_DQ9

D16 DDR_DQ13

D17 SYS_RESET_N

D18 DDR_DQ2

D19 DDR_DQS0N

D20 DDR_A2

D21 DDR_DQ6

D22 DNC

D23 DDR_A10

D24 DDR_DQ21

D25 GND

D27 GND

E1 GPIO_PU2

E2 XTAL_OUT

E3 XTAL_IN

E4 UART3_CTS_N

E5 GPIO_PU4

E6 THERMD_N

E7 GND

E8 DDR_COMP_PU

E9 DDR_DQ27

E10 GND

E11 DDR_DQS3N

E12 DDR_DQ26

E13 GND

E14 DDR_DQ11

E15 DDR_DM1

E16 GND

E17 DDR_DQ8

E18 DDR_DQ1

E19 GND



Ball # Signal Name

E20 DDR_DQS0P

E21 DDR_DQ5

E22 GND

E23 DDR_DQ23

E24 DDR_DQS2N

E25 DDR_CS0_N

E26 DDR_CLK

E27 DDR_CLK_N

E28 DDR_A13

F1 UART3_RTS_N

F2 UART3_RXD

F3 UART3_TXD

F4 UART2_RXD

F5 UART2_CTS_N

F6 GPIO_PU3

F7 THERMD_P

F8 DDR_COMP_PD

F9 DDR_DQ24

F10 DDR_DQ28

F11 DDR_DQ30

F12 DDR_DQ25

F13 DDR_DQ12

F14 DDR_DQS1N

F15 DDR_DQS1P

F16 DDR_DQ10

F17 DDR_DQ4

F18 DDR_DQ3

F19 DDR_DM0

F20 DDR_DQ0

F21 DDR_DQ7

F22 DDR_DQ20

F23 DDR_DQ16

F24 DDR_DQS2P

F25 DDR_DQ17

F26 DDR_A4

F27 DDR_WE_N

F28 DDR_A7

G2 GND

G4 GPIO_PU1

G5 GND

Ball # Signal Name

G6 UART2_RTS_N

G8 DDR_DQ29

G9 DDR_DQ31

G11 OWR

G12 PLL_S_PLL_LF

G14 CORE_PWR_REQ

G15 DDR_QUSE0

G17 DDR_QUSE1

G18 VDDIO_SYS

G20 DNC

G21 DNC

G23 DDR_DM2

G24 GND

G25 DDR_DQ19

G27 GND

H1 DAP4_DIN

H2 DAP4_SCLK

H3 DAP4_FS

H4 GPIO_PU5

H5 GEN1_I2C_SDA

H6 GEN1_I2C_SCL

H7 UART2_TXD

H8 GND

H9 VDD_CPU

H10 GND

H11 VDDIO_UART

H12 AVDD_OSC

H13 GND

H14 AVDD_PLLA_P_C

H15 AVDD_PLLM

H16 GND

H17 VDD_DDR_RX

H18 GND

H19 GND

H20 VDDIO_DDR

H21 GND

H22 DDR_DQ18

H23 VI_D0

H24 DDR_DQ22

H25 VI_D1

Ball # Signal Name

H26 DDR_CAS_N

H27 CAM_I2C_SDA

H28 CAM_I2C_SCL

J1 GPIO_PU0

J2 GPIO_PU6

J3 DAP3_FS

J4 DAP4_DOUT

J5 SDIO1_CMD

J6 GPIO_PV3

J7 GPIO_PV1

J8 VDD_CPU

J9 VDD_CPU

J10 VDD_CPU

J11 VDD_CPU

J12 VDDIO_DDR

J13 VDDIO_DDR

J14 VDDIO_DDR

J15 VDDIO_DDR

J16 VDDIO_DDR

J17 VDDIO_DDR

J18 VDDIO_DDR

J19 VDDIO_DDR

J20 VDDIO_DDR

J21 VDDIO_DDR

J22 VI_GP4

J23 VI_D2

J24 VI_D4

J25 VI_D6

J26 VI_D7

J27 VI_D5

J28 VI_D3

K2 GND

K4 SDIO1_DAT1

K5 GND

K6 SDIO1_DAT0

K8 GND

K9 VDD_CPU

K20 VDDIO_DDR

K21 GND

K23 VI_D8




Ball # Signal Name

K24 GND

K25 VI_VSYNC

K27 GND

L1 DAP3_DOUT

L2 DAP3_DIN

L3 ULPI_DATA3

L4 ULPI_DATA4

L5 SDIO1_DAT3

L6 ULPI_DATA5

L7 AVDD_PLLX

L8 GND

L9 VDD_CPU

L11 GND

L12 GND

L13 GND

L14 GND

L15 GND

L16 VDDIO_DDR

L17 VDDIO_DDR

L18 GND

L20 VDDIO_DDR

L21 VDDIO_VI

L22 VI_GP0

L23 VI_D10

L24 VI_MCLK

L25 VI_HSYNC

L26 VI_D9

L27 VI_GP5

L28 VI_PCLK

M1 ULPI_NXT

M2 ULPI_CLK

M3 ULPI_DIR

M4 DAP3_SCLK

M5 SDIO1_DAT2

M6 SDIO1_CLK

M7 DNC

M8 VDDIO_BB

M9 VDD_CPU

M11 VDD_CPU

M12 GND

Ball # Signal Name

M13 VDD_CORE

M14 VDD_CORE

M15 VDD_CORE

M16 VDD_CORE

M17 VDDIO_DDR

M18 VDDIO_DDR

M20 VDDIO_DDR

M21 DNC

M22 VI_D11

M23 VI_GP3

M24 VI_GP6

M25 SPI2_MISO

M26 SPI1_MOSI

M27 SPI1_CS0_N

M28 SPI1_SCK

N2 GND

N4 ULPI_DATA2

N5 GND

N6 ULPI_DATA7

N8 GND

N9 VDD_CPU_SENSE

N11 VDD_CPU

N12 VDD_CPU

N13 GND

N14 GND

N15 VDD_CORE

N16 GND

N17 GND

N18 VDDIO_DDR

N20 VDDIO_DDR

N21 GND

N23 SPDIF_OUT

N24 GND

N25 SPI2_MOSI

N27 GND

P1 VDDIO_SDIO

P2 GPIO_PV0

P3 ULPI_STP

P4 ULPI_DATA0

P5 ULPI_DATA6

Ball # Signal Name

P6 ULPI_DATA1

P7 GPIO_PV4

P8 AVDD_PEX_PLL

P9 GND_CPU_SENSE

P11 VDD_CPU

P12 VDD_CPU

P13 VDD_CPU

P14 VDD_CPU

P15 VDD_CORE

P16 VDD_CORE

P17 GND

P18 GND

P20 VDDIO_DDR

P21 VDDIO_AUDIO

P22 SPI2_CS1_N

P23 SPI2_CS0_N

P24 SPI2_SCK

P25 DAP1_SCLK

P26 SPI1_MISO

P27 DAP_MCLK1

P28 SPI2_CS2_N

R1 SDIO3_CMD

R2 SDIO3_CLK

R3 SDIO3_DAT0

R4 SDIO3_DAT3

R5 SDIO3_DAT6

R6 GPIO_PV6

R7 GPIO_PV5

R8 AVDD_PEX

R9 AVDD_PEX

R11 GND

R12 VDD_CPU

R13 VDD_CPU

R14 GND

R15 GND

R16 VDD_CORE

R17 GND

R18 GND

R20 VDDIO_DDR

R21 DNC



Ball # Signal Name

R22 DAP2_FS

R23 DAP2_SCLK

R24 DAP_MCLK2

R25 SPDIF_IN

R26 DAP1_DIN

R27 DAP1_FS

R28 DAP1_DOUT

T2 GND

T4 SDIO3_DAT4

T5 GND

T6 SDIO3_DAT5

T8 GND

T9 AVDD_PEX

T11 GND

T12 GND

T13 VDD_CORE

T14 GND

T15 VDD_CORE

T16 VDD_CORE

T17 GND

T18 GND

T20 VDDIO_DDR

T21 GND

T23 DAP2_DOUT

T24 GND

T25 DAP2_DIN

T27 GND

U1 PEX_REFCLKN

U2 PEX_REFCLKP

U3 SDIO3_DAT1

U4 SDIO3_DAT2

U5 DNC

U6 GPIO_PV2

U7 SDIO3_DAT7

U8 VDD_PEX

U9 VDD_PEX

U11 GND

U12 GND

U13 VDD_CORE

U14 VDD_CORE

Ball # Signal Name

U15 GND

U16 VDD_CORE

U17 VDD_CORE

U18 GND

U20 VDDIO_DDR

U21 GND

U22 VDDIO_LCD

U23 LCD_DE

U24 LCD_PWR1

U25 LCD_D12

U26 LCD_D15

U27 LCD_D14

U28 LCD_D13

V1 PEX_TSTCLKN

V2 PEX_TSTCLKP

V3 PEX_L2_RXP

V4 PEX_L2_RXN

V5 PEX_L3_RXP

V6 PEX_L3_RXN

V7 DNC

V8 VDDIO_PEX_CLK

V9 VDD_PEX

V11 GND

V12 VDD_RTC

V13 VDD_RTC

V14 GND

V15 GND

V16 GND

V17 VDD_CORE

V18 VDD_CORE

V20 VDDIO_DDR

V21 GND

V22 VDDIO_LCD

V23 HDMI_INT_N

V24 LCD_CS0_N

V25 LCD_D22

V26 LCD_D17

V27 LCD_D16

V28 LCD_PCLK

W2 GND

Ball # Signal Name

W4 DNC

W5 GND

W6 PEX_TERMP

W8 GND

W9 VDD_TP

W20 VDD_CORE

W21 GND

W23 DDC_SCL

W24 GND

W25 LCD_SDIN

W27 GND

Y1 AVDD_PLLE

Y2 PEX_L3_TXP

Y3 PEX_L3_TXN

Y4 PEX_CLK_OUT2_N

Y5 PEX_CLK_OUT2_P

Y6 DNC

Y7 VDDIO_NAND

Y8 VDDIO_NAND

Y9 VDDIO_NAND

Y10 GND_TP

Y11 GND

Y12 GND

Y13 GND

Y14 AVDD_USB

Y15 AVDD_HDMI

Y16 AVDD_DSI_CSI

Y17 GND_CORE_SENSE

Y18 VDD_CORE_SENSE

Y19 VDD_CORE

Y20 VDD_CORE

Y21 VDD_CORE

Y22 CRT_HSYNC

Y23 DDC_SDA

Y24 LCD_M1

Y25 LCD_D9

Y26 LCD_D6

Y27 LCD_D7

Y28 LCD_D8

AA1 PEX_L2_TXN



Ball # Signal Name

AA2 PEX_L2_TXP

AA3 DNC

AA4 PEX_L0_RXP

AA5 PEX_L0_RXN

AA6 PEX_L1_RXP

AA7 PEX_L1_RXN

AA8 GND

AA9 GND

AA10 GND

AA11 VGND_TP

AA12 AVDD_HDMI_PLL

AA13 GND

AA14 AVDD_USB

AA15 AVDD_HDMI

AA16 GND

AA17 AVDD_DSI_CSI

AA18 AVDD_PLLU

AA19 GND

AA20 VDD_CORE

AA21 GND

AA22 LCD_D21

AA23 LCD_D19

AA24 LCD_PWR2

AA25 LCD_SDOUT

AA26 LCD_D0

AA27 LCD_D11

AA28 LCD_D10

AB2 GND

AB4 DNC

AB5 GND

AB6 DNC

AB8 VDDIO_HSIC

AB9 AVDD_IC_USB

AB11 AVDD_USB_PLL

AB12 GMI_CS5_N

AB14 VPP_KFUSE

AB15 VPP_FUSE

AB17 VDAC_R

AB18 VDAC_G

AB20 CSI_CLKBN

Ball # Signal Name

AB21 LCD_SCK

AB23 LCD_D20

AB24 GND

AB25 LCD_D18

AB27 GND

AC1 PEX_L1_TXP

AC2 PEX_L1_TXN

AC3 DNC

AC4 PEX_CLK_OUT1_N

AC5 GMI_AD22

AC6 GMI_CS3_N

AC7 GMI_RST_N

AC8 GMI_AD27

AC9 GMI_DPD

AC10 GMI_IORDY

AC11 GMI_AD25

AC12 GMI_CS4_N

AC13 DNC

AC14 USB1_DN

AC15 HSIC_DATA

AC16 USB_REXT

AC17 VDAC_VREF

AC18 HDMI_TXD1N

AC19 GND

AC20 CSI_CLKBP

AC21 DSI_CLKAP

AC22 LCD_D23

AC23 CRT_VSYNC

AC24 LCD_DC1

AC25 LCD_CS1_N

AC26 LCD_D1

AC27 LCD_D2

AC28 LCD_D3

AD1 PEX_L0_TXN

AD2 PEX_L0_TXP

AD3 GMI_AD17

AD4 PEX_CLK_OUT1_P

AD5 GMI_CS6_N

AD6 GEN2_I2C_SDA

AD7 GND

Ball # Signal Name

AD8 GMI_AD20

AD9 GMI_CS7_N

AD10 GND

AD11 GEN2_I2C_SCL

AD12 GMI_CS2_N

AD13 GND

AD14 USB1_DP

AD15 HSIC_STROBE

AD16 GND

AD17 USB1_VBUS

AD18 HDMI_TXD1P

AD19 GND

AD20 CSI_D1AN

AD21 DSI_CLKAN

AD22 GND

AD23 LCD_DC0

AD24 LCD_PWR0

AD25 LCD_D4

AD26 LCD_VSYNC

AD27 LCD_HSYNC

AD28 LCD_D5

AE2 GND

AE4 GND

AE5 GMI_AD18

AE6 GMI_AD8

AE7 GMI_AD21

AE8 GMI_AD24

AE9 GMI_AD1

AE10 GMI_AD26

AE11 GMI_AD23

AE12 GMI_AD9

AE13 IC_REXT

AE14 ACC1_DETECT

AE15 HSIC_REXT

AE16 HDMI_TXD0N

AE17 HDMI_TXD0P

AE18 VDAC_RSET

AE19 VDAC_B

AE20 CSI_D1AP

AE21 DNC



Ball # Signal Name

AE22 DNC

AE23 DNC

AE24 LCD_WR_N

AE25 GND

AE27 GND

AF1 GMI_WAIT

AF2 GMI_WP_N

AF3 GMI_CLK

AF5 GMI_CS0_N

AF6 GMI_WR_N

AF8 GMI_AD7

AF9 GMI_AD6

AF11 GMI_AD2

AF12 GMI_CS1_N

AF14 IC_DN

AF15 ACC3_DETECT

AF17 HDMI_TXCN

AF18 HDMI_RSET

AF20 DSI_D1AN

AF21 DSI_CSI_RUP

AF23 DNC

AF24 DNC

AF26 DNC

AF27 DNC

AF28 DNC

AG1 GND

AG2 GND

AG3 GMI_AD13

AG4 GND

AG5 GMI_AD0

AG6 GMI_AD3

AG7 GND

AG8 GMI_AD19

AG9 GMI_OE_N

AG10 GND

AG11 GMI_AD5

AG12 GMI_AD16

AG13 GND

AG14 IC_DP

AG15 USB3_DP

Ball # Signal Name

AG16 GND

AG17 HDMI_TXCP

AG18 HDMI_TXD2P

AG19 GND

AG20 DSI_D1AP

AG21 DSI_D2AP

AG22 GND

AG23 CSI_D2AP

AG24 CSI_D1BP

AG25 GND

AG26 CSI_CLKAP

AG27 GND

AG28 GND

AH1 GND

AH2 GND

AH3 GMI_ADV_N

AH5 GMI_AD15

AH6 GMI_AD11

AH8 GMI_AD4

AH9 GMI_AD14

AH11 GMI_AD12

AH12 GMI_AD10

AH14 DNC

AH15 USB3_DN

AH17 AVDD_VDAC

AH18 HDMI_TXD2N

AH20 DSI_CSI_RDN

AH21 DSI_D2AN

AH23 CSI_D2AN

AH24 CSI_D1BN

AH26 CSI_CLKAN

AH27 GND

AH28 GND


3.2 Signal List and Multiplexing Functions The tables in this section that include multiplexing functions list only signal pins. Power, ground, and reserved pins are listed separately in Table 24.

Each table in this section represents a Pin Multiplexing Block. Each block has a unique I/O power rail the signal pins are associated with. Pin Multiplexing Positions refer to the 4 columns; Primary, Alternate 1, Alternate 2 and Alternate 3.

Table 7 Keyboard, Power, System (VDDIO_SYS) Signal Pinout with Multiplexing Functions

Table 8 NAND (VDDIO_NAND) Signal Pinout with Multiplexing Functions

Table 9 UART (VDDIO_UART) Signal Pinout with Multiplexing Functions

Table 10 Baseband (VDDIO_BB) Signal Pinout with Multiplexing Functions

Table 11 Video Input (VDDIO_VI) Signal Pinout with Multiplexing Functions

Table 12 Audio (VDDIO_AUDIO) Signal Pinout with Multiplexing Functions

Table 13 LCD (VDDIO_LCD) Signal Pinout with Multiplexing Functions

Table 14 DDR (VDDIO_DDR) Signal Pinout with Multiplexing Functions

Table 15 SDIO (VDDIO_SDIO) Signal Pinout with Multiplexing Functions

Table 16 MIPI (AVDD_DSI_CSI) Signal Pinout with Multiplexing Functions

Table 17 HDMI (AVDD_HDMI) Signal Pinout with Multiplexing Functions

Table 18 USB (USB_AVDD33) Signal Pinout with Multiplexing Functions

Table 19 PCIE (AVDD_PEX) Signal Pinout with Multiplexing Functions

Table 20 HSIC (AVDD_HSIC, AVDD_IC) Signal Pinout with Multiplexing Functions

Table 21 VDAC (AVDD_VDAC) Signal Pinout with Multiplexing Functions

Table 22 Crystal Oscillator (AVDD_OSC) Signal Pinout with Multiplexing Functions

Table 4 defines the pad types used in these tables.

Table 4 Pad Type Definitions

Pad Type Description Tristate Control Pullup/down Control Drive Slew Control Schmidt Control

A, B, Analog (MIPI D-Phy, MIPI D-Phy Bias) NA NA NA NA

E, F Analog (USB, USB Bias) NA NA NA NA

C CMOS Yes Yes Yes Yes

D CMOS Bidirectional Yes Yes Yes Yes

G CMOS (SYS_RESET_N input) NA No NA Yes1

H CMOS input NA No NA Yes

J XTAL_OUT input NA NA NA Yes1

K Fuse Burning Power

1 SYS_RESET_N and XTAL_OUT inputs are always Schmidt Trigger.




Table 5 lists the default reset states or power on reset (POR) values used in the following tables.

Table 5 POR—Default Reset States

POR Type Description

High

Low

PU Pulled Up

PD Pulled Down

T Toggle

Z High impedance state

S Inputs used to read the state of the external strapping resistors.

Table 6 provides a list of pin assignments used for wake-up events.

Table 6 Wake-up

Ball # Ball Name I/O Rail Wake Event

L4 ULPI_DATA4 VDDIO_BB Wake_event[0]

J6 GPIO_PV3 VDDIO_BB Wake_event[1]

J28 VI_D3 VDDIO_VI Wake_event[2]

U3 SDIO3_DAT1 VDDIO_SDIO Wake_event[3]

V23 HDMI_INT_N VDDIO_LCD Wake_event[4]

M24 VI_GP6 VDDIO_VI Wake_event[5]

H4 GPIO_PU5 VDDIO_UART Wake_event[6]

J2 GPIO_PU6 VDDIO_UART Wake_event[7]

AF2 GMI_WP_N VDDIO_NAND Wake_event[8]

D8 KB_ROW10 VDDIO_SYS Wake_event[9]

AE7 GMI_AD21 VDDIO_NAND Wake_event[10]

P28 SPI2_CS2_N VDDIO_AUDIO Wake_event[11]

P22 SPI2_CS1_N VDDIO_AUDIO Wake_event[12]

K4 SDIO1_DAT1 VDDIO_BB Wake_event[13]

R6 GPIO_PV6 VDDIO_SDIO Wake_event[14]

AG12 GMI_AD16 VDDIO_NAND Wake_event[15]

D14 PWR_INT_N VDDIO_SYS Wake_event[18]

AD17 USB1_VBUS AVDD_USB Wake_event[19]

AH14 DNC AVDD_USB Wake_event[20]



Ball # Ball Name I/O Rail Wake Event

AE14 ACC1_DETECT AVDD_USB Wake_event[21]

AF15 ACC3_DETECT AVDD_USB Wake_event[22]

AC10 GMI_IORDY VDDIO_NAND Wake_event[23]

U6 GPIO_PV2 VDDIO_BB Wake_event[24]

B8 KB_ROW12 VDDIO_SYS Wake_event[25]

C8 KB_ROW13 VDDIO_SYS Wake_event[26]

B9 KB_ROW8 VDDIO_SYS Wake_event[27]

A3 KB_COL6 VDDIO_SYS Wake_event[28]

C3 KB_COL7 VDDIO_SYS Wake_event[29]

R28 DAP1_DOUT VDDIO_AUDIO Wake_event[30]


Table 7 Keyboard, Power, System (VDDIO_SYS) Signal Pinout with Multiplexing Functions

Ball # Ball Name SFIO Primary

SFIO Alternate 1

SFIO Alternate 2

SFIO Alternate 3 GPIO Pin

Group Pin Config. POR1 Pad

Type2

C12 KB_ROW0 KB_ROW0 NAND_D0 GPIO_PR0 kbca aocfg1 pd C

B12 KB_ROW1 KB_ROW1 NAND_D1 SDIO2_DAT4 GPIO_PR1 kbca aocfg1 pd C

A12 KB_ROW2 KB_ROW2 NAND_D2 SDIO2_DAT5 GPIO_PR2 kbca aocfg1 pd C

D11 KB_ROW3 KB_ROW3 NAND_D3 SDIO2_DAT6 GPIO_PR3 kbcd aocfg1 pd C

A11 KB_ROW4 KB_ROW4 NAND_D4 SDIO2_DAT7 GPIO_PR4 kbcd aocfg1 pd C

B11 KB_ROW5 KB_ROW5 NAND_D5 SDIO2_CLK GPIO_PR5 kbcd aocfg1 pd C

C11 KB_ROW6 KB_ROW6 NAND_D6 SDIO2_CMD GPIO_PR6 kbcd aocfg1 pd C

C9 KB_ROW7 KB_ROW7 NAND_D7 SDIO2_DAT0 GPIO_PR7 kbcb aocfg1 pd C

B9 KB_ROW8 KB_ROW8 NAND_D8 SDIO2_DAT1 GPIO_PS0 kbcb aocfg2 pd C

A9 KB_ROW9 KB_ROW9 NAND_D9 SDIO2_DAT2 GPIO_PS1 kbcb aocfg2 pd C

D8 KB_ROW10 KB_ROW10 NAND_D10 SDIO2_DAT3 GPIO_PS2 kbcb aocfg2 pd C

A8 KB_ROW11 KB_ROW11 NAND_D11 GPIO_PS3 kbcb aocfg2 pd C

B8 KB_ROW12 KB_ROW12 NAND_D12 GPIO_PS4 kbcb aocfg2 pd C

C8 KB_ROW13 KB_ROW13 NAND_D13 GPIO_PS5 kbcb aocfg2 pd C

C6 KB_ROW14 KB_ROW14 NAND_D14 GPIO_PS6 kbcb aocfg2 pd C

B6 KB_ROW15 KB_ROW15 NAND_D15 GPIO_PS7 kbcb aocfg2 pd C

A6 KB_COL0 KB_COL0 NAND_BSY0 GPIO_PQ0 kbcc aocfg2 pu C

D6 KB_COL1 KB_COL1 NAND_ALE GPIO_PQ1 kbcc aocfg2 pu C

A5 KB_COL2 KB_COL2 NAND_CLE GPIO_PQ2 kbcf aocfg2 pu C

B5 KB_COL3 KB_COL3 NAND_WE _N GPIO_PQ3 kbcf aocfg2 pu C

C5 KB_COL4 KB_COL4 NAND_RE _N GPIO_PQ4 kbcf aocfg2 pu C

B3 KB_COL5 KB_COL5 NAND_CE0 _N GPIO_PQ5 kbcf aocfg2 pu C

A3 KB_COL6 KB_COL6 NAND_CE1_N GPIO_PQ6 kbcf aocfg2 pu C

C3 KB_COL7 KB_COL7 NAND_CE2_N GPIO_PQ7 kbce aocfg2 pu C

D5 CLK_32K_OUT CLK_32K_OUT GPIO_PBB0 pmc aocfg2 low C

D7 SYS_CLK_REQ SYS_CLK_REQ GPIO_PZ5 pmc aocfg2 z C

G14 CORE_PWR_REQ CORE_PWR_REQ pmc aocfg2 z C

C14 CPU_PWR_REQ CPU_PWR_REQ pmc aocfg2 z C



SFIO SFIO SFIO SFIO Pin Pin Pad POR1 Ball # Ball Name GPIO Primary Alternate 1 Alternate 2 Alternate 3 Group Config. Type2

D14 PWR_INT_N PWR_INT_N pmc aocfg2 z C

G11 OWR OWR owc owrcfg z

B14 CLK_32K_IN CLK_32K_IN rtc aocfg2 z C

A14 TEST_MODE_EN TEST_MODE_EN tst dbgcfg H

D17 SYS_RESET_N SYS_RESET_N rst aocfg1 z G

C1 PWR_I2C_SCL PWR_I2C_SCL GPIO_PZ6 i2cp aocfg1 pu C

C2 PWR_I2C_SDA PWR_I2C_SDA GPIO_PZ7 i2cp aocfg1 pu C

A17 JTAG_RTCK JTAG_RTCK GPIO_PU7 gpu7 dbgcfg T D

A15 JTAG_TRST_N JTAG_TRST_N dbg dbgcfg pd H

C15 JTAG_TDO JTAG_TDO dbg dbgcfg z D

C17 JTAG_TMS JTAG_TMS dbg dbgcfg pu H

B17 JTAG_TCK JTAG_TCK dbg dbgcfg H

B15 JTAG_TDI JTAG_TDI dbg dbgcfg pu H

1. Default reset state. High; Low; PU: Pulled up; PD: Pulled down; T: Toggle; Z: High impedance state.

2. Pad types are described in Table 4

Table 8 NAND (VDDIO_NAND) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO Alternate 2



Type2

AC10 GMI_IORDY IDE_IRQ NAND_CE3_N GMI_IORDY GPIO_PI5 atc atcfg1 pu D

AF1 GMI_WAIT IDE_IORDY NAND_BSY0 GMI_WAIT HSMMC_CMD GPIO_PI7 atc atcfg2 pu D

AH3 GMI_ADV_N IDE_A0 NAND_ALE GMI_ADV_N GPIO_PK0 atc atcfg2 s D

AF3 GMI_CLK IDE_A1 NAND_CLE GMI_CLK HSMMC_CLK GPIO_PK1 atc atcfg2 s D

AF5 GMI_CS0_N NAND_CE6 _N GMI_CS0_N SFLASH_CS0_N GPIO_PJ0 gmd gmdcfg high D

AF12 GMI_CS1_N NAND_CE7_N GMI_CS1_N SFLASH_CLK GPIO_PJ2 gmd gmdcfg high D

AD12 GMI_CS2_N IDE_CS0 NAND_CE0 _N GMI_CS2_N GPIO_PK3 atc atcfg2 pu D

AC6 GMI_CS3_N IDE_CS1 NAND_CE1_N GMI_CS3_N GPIO_PK4 atc atcfg2 pu D

AC12 GMI_CS4_N IDE_A2 NAND_CE2_N GMI_CS4_N GPIO_PK2 atc atcfg2 pu D

AB12 GMI_CS5_N IDE_DMARQ NAND_CE5 _N GMI_CS5_N HSMMC_CLK GPIO_PI2 atb atcfg2 pu D

AD5 GMI_CS6_N NAND_CE4_N GMI_CS6_N GPIO_PI3 ata atcfg2 pu D




AD9 GMI_CS7_N NAND_CE6 _N GMI_CS7_N GPIO_PI6 ata atcfg1 pu D

AG5 GMI_AD0 IDE_D0 NAND_D0 GMI_AD0 HSMMC_DAT1 GPIO_PG0 atc atcfg2 pu D

AE9 GMI_AD1 IDE_D1 NAND_D1 GMI_AD1 HSMMC_DAT3 GPIO_PG1 atc atcfg2 pu D

AF11 GMI_AD2 IDE_D2 NAND_D2 GMI_AD2 HSMMC_DAT5 GPIO_PG2 atc atcfg2 pu D

AG6 GMI_AD3 IDE_D3 NAND_D3 GMI_AD3 HSMMC_DAT7 GPIO_PG3 atc atcfg2 pu D

AH8 GMI_AD4 IDE_D4 NAND_D4 GMI_AD4 GPIO_PG4 atc atcfg2 s D

AG11 GMI_AD5 IDE_D5 NAND_D5 GMI_AD5 GPIO_PG5 atc atcfg2 s D

AF9 GMI_AD6 IDE_D6 NAND_D6 GMI_AD6 GPIO_PG6 atc atcfg2 s D

AF8 GMI_AD7 IDE_D7 NAND_D7 GMI_AD7 GPIO_PG7 atc atcfg2 s D

AE6 GMI_AD8 IDE_D8 NAND_D8 GMI_AD8 HSMMC_DAT0 GPIO_PH0 atd atcfg1 pu D

AE12 GMI_AD9 IDE_D9 NAND_D9 GMI_AD9 HSMMC_DAT2 GPIO_PH1 atd atcfg1 pu D

AH12 GMI_AD10 IDE_D10 NAND_D10 GMI_AD10 HSMMC_DAT4 GPIO_PH2 atd atcfg1 pu D

AH6 GMI_AD11 IDE_D11 NAND_D11 GMI_AD11 HSMMC_DAT6 GPIO_PH3 atd atcfg1 pu D

AH11 GMI_AD12 IDE_D12 NAND_D12 GMI_AD12 GPIO_PH4 ate atcfg1 s (pu) D

AG3 GMI_AD13 IDE_D13 NAND_D13 GMI_AD13 GPIO_PH5 ate atcfg1 s (pu) D



AG12 GMI_AD16 UART4_TXD SPI4_SCK GMI_AD16 GMI_INT2 GPIO_PJ7 gmc gmccfg z D

AD3 GMI_AD17 UART4_RXD SPI4_MOSI GMI_AD17 SFLASH_DOUT GPIO_PB0 gmc gmccfg z D

AE5 GMI_AD18 UART4_CTS_N SPI4_MISO GMI_AD18 SFLASH_DIN GPIO_PB1 gmc gmccfg z D

AG8 GMI_AD19 UART4_RTS_N SPI4_CS1_N GMI_AD19 GPIO_PK7 gmc gmccfg z D

AD8 GMI_AD20 UART5_TXD SPI3_SCK GMI_AD20 HSMMC_DAT0 GPIO_PAA0 gma gmacfg z D

AE7 GMI_AD21 UART5_RXD SPI3_MOSI GMI_AD21 HSMMC_DAT1 GPIO_PAA1 gma gmacfg z D

AC5 GMI_AD22 UART5_CTS_N SPI3_MISO GMI_AD22 HSMMC_DAT2 GPIO_PAA2 gma gmacfg z D

AE11 GMI_AD23 UART5_RTS_N SPI3_CS0_N GMI_AD23 HSMMC_DAT3 GPIO_PAA3 gma gmacfg z D

AE8 GMI_AD24 DAP5_FS GMI_AD24 HSMMC_DAT4 GPIO_PAA4 gme gmecfg z D

AC11 GMI_AD25 DAP5_DIN GMI_AD25 HSMMC_DAT5 GPIO_PAA5 gme gmecfg z D

AE10 GMI_AD26 DAP5_DOUT GMI_AD26 HSMMC_DAT6 GPIO_PAA6 gme gmecfg z D

AC8 GMI_AD27 DAP5_SCLK GMI_AD27 HSMMC_DAT7 GPIO_PAA7 gme gmecfg z D




AF6 GMI_WR_N IDE_WR_N NAND_WE _N GMI_WR_N GPIO_PI0 atc atcfg2 s D

AG9 GMI_OE_N IDE_OE_N NAND_RE _N GMI_OE_N GPIO_PI1 atc atcfg2 s D

AC7 GMI_RST_N IDE_RESET NAND_CLE GMI_RST_N GPIO_PI4 ata atcfg2 low D

AD11 GEN2_I2C_SCL GEN2_I2C_SCL GMI_CS6_N GPIO_PT5 pta atcfg1 pu D

AD6 GEN2_I2C_SDA GEN2_I2C_SDA GMI_CS7_N GPIO_PT6 pta atcfg1 pu D

AC9 GMI_DPD IDE_HDMACK NAND_CLE GMI_DPD HSMMC_CMD GPIO_PT7 atb atcfg1 low D

AF2 GMI_WP_N IDE_HIRQ NAND_CE5_N GMI_WP_N GMI_INT1 GPIO_PC7 gmb gmbcfg low



3. GMI_AD[15:12] are the Boot Select stapping pins. These pins do have internal pull-ups enabled, stronger external pull-downs will be needed where necessary to select desired boot device (use 10K pulldown on these pins)

Table 9 UART (VDDIO_UART) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO Alternate 2



Type2

H7 UART2_TXD UART2_TXD SPDIF_IN UART1_RTS_N SPI4_SCK GPIO_PC2 uad uart2cfg pu D

F4 UART2_RXD UART2_RXD SPDIF_OUT UART1_CTS_N SPI4_MOSI GPIO_PC3 uad uart2cfg pu D

G6 UART2_RTS_N UART1_TXD UART2_RTS_N GMI_A0 SPI4_MISO GPIO_PJ6 irrx uart2cfg pu D

F5 UART2_CTS_N UART1_RXD UART2_CTS_N GMI_A1 SPI4_CS1_N GPIO_PJ5 irtx uart2cfg pu D

F3 UART3_TXD UART3_TXD GMI_A2 GPIO_PW6 uca uart3cfg pu D

F2 UART3_RXD UART3_RXD GMI_A3 GPIO_PW7 uca uart3cfg pu D

F1 UART3_RTS_N UART3_RTS_N PMFM_PWM0 GMI_A4 GPIO_PC0 ucb uart3cfg pu D

E4 UART3_CTS_N UART3_CTS_N GMI_A5 GPIO_PA1 ucb uart3cfg pu D

J1 GPIO_PU0 UART1_TXD GMI_A6 GPIO_PU0 gpu dbgcfg z D

G4 GPIO_PU1 UART1_RXD GMI_A7 GPIO_PU1 gpu dbgcfg z D

E1 GPIO_PU2 UART1_CTS_N GMI_A8 GPIO_PU2 gpu dbgcfg z D

F6 GPIO_PU3 PMFM_PWM0 UART1_RTS_N GMI_A9 GPIO_PU3 gpu dbgcfg z D

E5 GPIO_PU4 PMFM_PWM1 UART1_DTR_N GMI_A10 GPIO_PU4 gpu dbgcfg z D

H4 GPIO_PU5 PMFM_PWM2 UART1_RI_N GMI_A11 GPIO_PU5 gpu dbgcfg z D

J2 GPIO_PU6 PMFM_PWM3 UART1_DSR_N GMI_A12 GPIO_PU6 gpu dbgcfg z D

H5 GEN1_I2C_SDA GEN1_I2C_SDA GPIO_PC5 rm dbgcfg pu D




H6 GEN1_I2C_SCL GEN1_I2C_SCL GPIO_PC4 rm dbgcfg pu D

H3 DAP4_FS DAP4_FS GMI_A13 GPIO_PP4 dap4 dap4cfg pd D

H1 DAP4_DIN DAP4_DIN GMI_A14 GPIO_PP5 dap4 dap4cfg pd D

J4 DAP4_DOUT DA _DOUT GMI_A15 GPIO_PP6 dap4 dap4cfg pd D

H2 DAP4_SCLK DAP4_SCLK GMI_A16 GPIO_PP7 dap4 dap4cfg pd D



Table 10 Baseband (VDDIO_BB) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO Alternate 2



Type2

P4 ULPI_DATA0 SPI3_MOSI HSI_TX_DATA UART1_TXD ULPI_DATA0 GPIO_PO1 uaa uaacfg pu D

P6 ULPI_DATA1 SPI3_MISO HSI_RX_DATA UART1_RXD ULPI_DATA1 GPIO_PO2 uaa uaacfg pu D

N4 ULPI_DATA2 SPI3_SCK HSI_TX_READY UART1_CTS_N ULPI_DATA2 GPIO_PO3 uaa uaacfg pu D

L3 ULPI_DATA3 SPI3_CS1_N HSI_RX_READY UART1_RTS_N ULPI_DATA3 GPIO_PO4 uaa uaacfg pu D

L4 ULPI_DATA4 SPI2_MOSI HSI_RX_WAKE UART1_RI_N ULPI_DATA4 GPIO_PO5 uab uabcfg pu D

L6 ULPI_DATA5 SPI2_MISO HSI_TX_WAKE UART1_DCD_N ULPI_DATA5 GPIO_PO6 uab uabcfg pu D

P5 ULPI_DATA6 SPI2_SCK HSI_RX_FLAG UART1_DSR_N ULPI_DATA6 GPIO_PO7 uab uabcfg pu D

N6 ULPI_DATA7 SPI2_CS1_N HSI_TX_FLAG UART1_DTR_N ULPI_DATA7 GPIO_PO0 uab uabcfg pu D

M2 ULPI_CLK SPI1_MOSI UART4_TXD ULPI_CLK GPIO_PY0 uda udacfg z D

M3 ULPI_DIR SPI1_MISO UART4_RXD ULPI_DIR GPIO_PY1 uda udacfg z D

M1 ULPI_NXT SPI1_SCK UART4_CTS_N ULPI_NXT GPIO_PY2 uda udacfg z D

P3 ULPI_STP SPI1_CS0_N UART4_RTS_N ULPI_STP GPIO_PY3 uda udacfg z D

J3 DAP3_FS DAP3_FS GPIO_PP0 dap3 dap3cfg pd D

L2 DAP3_DIN DAP3_DIN GPIO_PP1 dap3 dap3cfg pd D

L1 DAP3_DOUT DAP3_DOUT GPIO_PP2 dap3 dap3cfg pd D

M4 DAP3_SCLK DAP3_SCLK GPIO_PP3 dap3 dap3cfg pd D

M6 SDIO1_CLK SDIO1_CLK UART1_DTR_N GPIO_PZ0 sdio1 sdio1cfg pu D

J5 SDIO1_CMD SDIO1_CMD UART1_CTS_N GPIO_PZ1 sdio1 sdio1cfg pu D

K6 SDIO1_DAT0 SDIO1_DAT0 UART5_RTS_N UART1_RTS_N GPIO_PY7 sdio1 sdio1cfg pu D




K4 SDIO1_DAT1 SDIO1_DAT1 UART5_CTS_N UART1_RI_N GPIO_PY6 sdio1 sdio1cfg pu D

M5 SDIO1_DAT2 SDIO1_DAT2 UART5_RXD UART1_RXD GPIO_PY5 sdio1 sdio1cfg pu D

L5 SDIO1_DAT3 SDIO1_DAT3 UART5_TXD UART1_TXD GPIO_PY4 sdio1 sdio1cfg pu D

P2 GPIO_PV0 GPIO_PV0 uac uabcfg z D

J7 GPIO_PV1 GPIO_PV1 uac uabcfg z D

U6 GPIO_PV2 GPIO_PV2 uac uabcfg z D

J6 GPIO_PV3 CLK12M_OUT GPIO_PV3 uac uabcfg z D



Table 11 Video Input (VDDIO_VI) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO Alternate 2



Type2

L28 VI_PCLK SDIO2_SCLK VI_CLK GPIO_PT0 dtd vicfg1 pd D

L24 VI_MCLK PLLC_OUT1 PLLP_OUT2 PLLP_OUT3 VI_SENSOR_CLK GPIO_PT1 csus csuscfg pd D

H23 VI_D0 VI_D0 GPIO_PT4 dta vicfg1 pd D

H25 VI_D1 SDIO2_CMD VI_D1 GPIO_PD5 dta vicfg1 pd D

J23 VI_D2 SDIO2_DAT0 VI_D2 GPIO_PL0 dtd vicfg1 pd D






K23 VI_D8 SDIO2_DAT6 VI_D8 GPIO_PL6 dtd vicfg1 pd D

L26 VI_D9 SDIO2_DAT7 VI_D9 GPIO_PL7 dtd vicfg1 pd D

L23 VI_D10 VI_D10 SPI1_MOSI GPIO_PT2 dtb vicfg1 pd D

M22 VI_D11 VI_D11 SPI1_MISO GPIO_PT3 dtb vicfg1 pd D

K25 VI_VSYNC VI_VSYNC GPIO_PD6 dtc vicfg1 pd D

L25 VI_HSYNC VI_HSYNC GPIO_PD7 dtc vicfg1 pd D

H28 CAM_I2C_SCL CAM_I2C_SCL VI_GP1 GPIO_PBB2 dtf vicfg2 pu D




H27 CAM_I2C_SDA CAM_I2C_SDA VI_GP2 GPIO_PBB3 dtf vicfg2 pu D

L22 VI_GP0 VI_GP0 GPIO_PBB1 dte vicfg2 z D

M23 VI_GP3 VI_GP3 SPI1_SCK GPIO_PBB4 dte vicfg2 z D

J22 VI_GP4 VI_GP4 SPI1_CS0_N GPIO_PBB5 dte vicfg2 z D

L27 VI_GP5 VI_GP5 GPIO_PD2 dte vicfg2 z D

M24 VI_GP6 VI_GP6 GPIO_PA0 dte vicfg2 z D

1. Default reset state. High; Low; PU: Pulled up; PD: Pulled down; T: Toggle; Z: High impedance state. 2. Pad types are described in Table 4

Table 12 Audio (VDDIO_AUDIO) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO Alternate 2



Type2

R27 DAP1_FS DAP1_FS GMI_D28 SDIO2_CMD GPIO_PN0 dap1 dap1cfg pd D

R26 DAP1_DIN DAP1_DIN GMI_D29 SDIO2_DAT0 GPIO_PN1 dap1 dap1cfg pd D

R28 DAP1_DOUT DAP1_DOUT GMI_D30 SDIO2_DAT1 GPIO_PN2 dap1 dap1cfg pd D

P25 DAP1_SCLK DAP1_SCLK GMI_D31 SDIO2_SCLK GPIO_PN3 dap1 dap1cfg pd D

P27 DAP_MCLK1 OSC PLLA_OUT PLLM_OUT1 AUDIO_SYNC GPIO_PW4 cdev1 cdev1cfg pd D

N23 SPDIF_OUT SPDIF_OUT I2C_CLK SDIO2_DAT2 GPIO_PK5 spdo dap1cfg pu D

R25 SPDIF_IN SPDIF_IN I2C_SDA SDIO2_DAT3 GPIO_PK6 spdi dap1cfg pu D

R24 DAP_MCLK2 OSC AHB_CLK APB_CLK PLLP_OUT4 GPIO_PW5 cdev2 cdev2cfg pd D

R22 DAP2_FS DAP2_FS TWC_CS_N GMI_A17 GPIO_PA2 dap2 dap2cfg pd D

R23 DAP2_SCLK DAP2_SCLK TWC_CLK GMI_A18 GPIO_PA3 dap2 dap2cfg pd D

T25 DAP2_DIN DAP2_DIN TWC_DIN GMI_A19 GPIO_PA4 dap2 dap2cfg pd D

T23 DAP2_DOUT DAP2_DOUT TWC_DO GMI_A20 GPIO_PA5 dap2 dap2cfg pd D

N25 SPI2_MOSI SPI1_MOSI SPI2_MOSI SPI3_MOSI GMI_A21 GPIO_PX0 spia spicfg pd D

M25 SPI2_MISO SPI1_MISO SPI2_MISO SPI3_MISO GMI_A22 GPIO_PX1 spib spicfg pd D

P24 SPI2_SCK SPI1_SCK SPI2_SCK SPI3_SCK GMI_A23 GPIO_PX2 spic spicfg low D

P23 SPI2_CS0_N SPI1_CS0_N SPI2_CS0_N SPI3_CS1_N GMI_A24 GPIO_PX3 spic spicfg low D

M26 SPI1_MOSI SPI2_MOSI SPI1_MOSI SPI2_MOSI GMI_A25 GPIO_PX4 spid spicfg pd D

M28 SPI1_SCK SPI2_SCK SPI1_SCK SPI2_SCK GMI_A26 GPIO_PX5 spie spicfg pu D




SFIO Alternate 1



Type2 SFIO Alternate 2

M27 SPI1_CS0_N SPI2_CS1_N SPI1_CS0_N SPI2_CS1_N GMI_A27 GPIO_PX6 spie spicfg pu D

P26 SPI1_MISO SPI3_MISO SPI1_MISO SPI2_MISO GPIO_PX7 spif spicfg pd D

P22 SPI2_CS1_N SPI3_SCK SPI2_CS1_N SPI2_CS2_N I2C_CLK GPIO_PW2 spig spicfg pu D

P28 SPI2_CS2_N SPI3_CS0_N SPI2_CS2_N SPI2_CS3_N I2C_SDA GPIO_PW3 spih spicfg pu D



Table 13 LCD (VDDIO_LCD) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO Alternate 2



Type2

AD24 LCD_PWR0 LCD1_LPW0 LCD2_LPW0 SPI3_MOSI GPIO_PB2 lpw0 lcdcfg2 pu D

U24 LCD_PWR1 LCD1_LPW1 LCD2_LPW1 GPIO_PC1 lpw1 lcdcfg1 pu D

AA24 LCD_PWR2 LCD1_LPW2 LCD2_LPW2 SPI3_MISO GPIO_PC6 lpw2 lcdcfg1 pu D

W25 LCD_SDIN LCD1_LSDI LCD2_LSDI SPI3_MISO GPIO_PZ2 lsdi lcdcfg1 pu D

AA25 LCD_SDOUT LCD1_LSDA LCD2_LSDA SPI3_MOSI GPIO_PN5 lsda lcdcfg1 pu D

V24 LCD_CS0_N LCD1_LCSN LCD2_LCSN SPI3_CS2_N GPIO_PN4 lcsn lcdcfg1 pu D

AD23 LCD_DC0 LCD1_LDC LCD2_LDC GPIO_PN6 ldc lcdcfg1 pu D

AB21 LCD_SCK LCD1_LSCK LCD2_LSCK SPI3_SCK GPIO_PZ4 lsck lcdcfg1 pu D

AC25 LCD_CS1_N LCD1_LM0 LCD2_LM0 SPI3_CS3_N GPIO_PW0 lm0 lcdcfg2 pu D

AC24 LCD_DC1 LCD1_LVP0 LCD2_LVP0 GPIO_PV7 lvp0 lcdcfg2 pu D

AE24 LCD_WR_N LCD1_LSC1 LCD2_LSC1 SPI3_SCK GPIO_PZ3 lsc1 lcdcfg1 pu D

Y24 LCD_M1 LCD1_LM1 LCD2_LM1 GPIO_PW1 lm1 lcdcfg2 pu D

U23 LCD_DE LCD1_LSPI LCD2_LSPI GPIO_PJ1 lspi lcdcfg2 pu D

V28 LCD_PCLK LCD1_LSC0 LCD2_LSC0 GPIO_PB3 lsc0 lcdcfg2 pu D

AD27 LCD_HSYNC LCD1_LHS LCD2_LHS GPIO_PJ3 lhs lcdcfg2 pu D

AD26 LCD_VSYNC LCD1_LVS LCD2_LVS GPIO_PJ4 lvs lcdcfg2 pu D

AA26 LCD_D0 LCD1_LD0 LCD2_LD0 GPIO_PE0 ld0 lcdcfg2 pd D

AC26 LCD_D1 LCD1_LD1 LCD2_LD1 GPIO_PE1 ld1 lcdcfg2 pd D






AD25 LCD_D4 LCD1_LD4 LCD2_LD4 GPIO_PE4 ld4 lcdcfg2 pd D

AD28 LCD_D5 LCD1_LD5 LCD2_LD5 GPIO_PE5 ld5 lcdcfg2 pd D

Y26 LCD_D6 LCD1_LD6 LCD2_LD6 GPIO_PE6 ld6 lcdcfg2 pd D

Y27 LCD_D7 LCD1_LD7 LCD2_LD7 GPIO_PE7 ld7 lcdcfg2 pd D

Y28 LCD_D8 LCD1_LD8 LCD2_LD8 GPIO_PF0 ld8 lcdcfg2 pd D

Y25 LCD_D9 LCD1_LD9 LCD2_LD9 GPIO_PF1 ld9 lcdcfg2 pd D

AA28 LCD_D10 LCD1_LD10 LCD2_LD10 GPIO_PF2 ld10 lcdcfg2 pd D

AA27 LCD_D11 LCD1_LD11 LCD2_LD11 GPIO_PF3 ld11 lcdcfg2 pd D

U25 LCD_D12 LCD1_LD12 LCD2_LD12 GPIO_PF4 ld12 lcdcfg2 pd D




V27 LCD_D16 LCD1_LD16 LCD2_LD16 GPIO_PM0 ld16 lcdcfg2 pd D

V26 LCD_D17 LCD1_LD17 LCD2_LD17 GPIO_PM1 ld17 lcdcfg2 pd D

AB25 LCD_D18 LCD1_LHP1 LCD2_LHP1 GPIO_PM2 lhp1 lcdcfg2 pd D

AA23 LCD_D19 LCD1_LHP2 LCD2_LHP2 GPIO_PM3 lhp2 lcdcfg2 pd D

AB23 LCD_D20 LCD1_LVP1 LCD2_LVP1 GPIO_PM4 lvp1 lcdcfg2 pd D

AA22 LCD_D21 LCD1_LHP0 LCD2_LHP0 GPIO_PM5 lhp0 lcdcfg2 pd D

V25 LCD_D22 LCD1_LDI LCD2_LDI GPIO_PM6 ldi lcdcfg2 pd D

AC22 LCD_D23 LCD1_LPP LCD2_LPP GPIO_PM7 lpp lcdcfg2 pd D

V23 HDMI_INT_N HDMI_INT_N GPIO_PN7 hdint lcdcfg2 z D

W23 DDC_SCL GEN2_I2C_SCL ddc ddccfg z D

Y23 DDC_SDA GEN2_I2C_SDA ddc ddccfg z D

Y22 CRT_HSYNC CRT_HSYNC crtp crtcfg pu D

AC23 CRT_VSYNC CRT_VSYNC crtp crtcfg pu D





Table 14 DDR (VDDIO_DDR) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO Alternate 2



Type2

A20 DDR_A0 DDR_A0 xm2c xm2cfga low D

C24 DDR_A1 DDR_A1 xm2c xm2cfga low D

D20 DDR_A2 DDR_A2 xm2c xm2cfga low D

B20 DDR_A3 DDR_A3 xm2c xm2cfga low D

F26 DDR_A4 DDR_A4 xm2c xm2cfga low D



F28 DDR_A7 DDR_A7 xm2c xm2cfga low D



D23 DDR_A10 DDR_A10 xm2c xm2cfga low D



E28 DDR_A13 DDR_A13 xm2c xm2cfga low D


B26 DDR_BA0 DDR_BA0 xm2c xm2cfga low D

A24 DDR_BA1 DDR_BA1 xm2c xm2cfga low D

B24 DDR_BA2 DDR_BA2 xm2c xm2cfga low D

E20 DDR_DQS0P DDR_DQS0P xm2c xm2cfgc low D

D19 DDR_DQS0N DDR_DQS0N xm2c xm2cfgc low D

F15 DDR_DQS1P DDR_DQS1P xm2c xm2cfgc low D

F14 DDR_DQS1N DDR_DQS1N xm2c xm2cfgc low D

F24 DDR_DQS2P DDR_DQS2P xm2c xm2cfgc low D

E24 DDR_DQS2N DDR_DQS2N xm2c xm2cfgc low D

D10 DDR_DQS3P DDR_DQS3P xm2s xm2cfgc low D

E11 DDR_DQS3N DDR_DQS3N xm2s xm2cfgc low D

E25 DDR_CS0_N DDR_CS0_N xm2s xm2cfga low D

C23 DDR_CS1_N DDR_CS1_N xm2s xm2cfga low D




A21 DDR_CKE0 DDR_CKE0 xm2c xm2cfga low D

C21 DDR_CKE1 DDR_CKE1 xm2c xm2cfga low D

E26 DDR_CLK DDR_CLK xm2c xm2clkcfg low D

E27 DDR_CLK_N DDR_CLK_N xm2c xm2clkcfg high D

B21 DDR_ODT0 DDR_ODT0 xm2c xm2cfga D

B23 DDR_RAS_N DDR_RAS_N xm2c xm2cfga D

H26 DDR_CAS_N DDR_CAS_N xm2c xm2cfga D

F27 DDR_WE_N DDR_WE_N xm2c xm2cfga high D

F20 DDR_DQ0 DDR_DQ0 xm2d xm2cfgd z D

E18 DDR_DQ1 DDR_DQ1 xm2d xm2cfgd z D

D18 DDR_DQ2 DDR_DQ2 xm2d xm2cfgd z D
















H22 DDR_DQ18 DDR_DQ18 xm2d xm2cfgd z D

G25 DDR_DQ19 DDR_DQ19 xm2d xm2cfgd z D






H24 DDR_DQ22 DDR_DQ22 xm2d xm2cfgd z D










E8 DDR_COMP_PU DDR_COMP_PU ddrc xm2comp

F8 DDR_COMP_PD DDR_COMP_PD ddrc xm2comp

F19 DDR_DM0 DDR_DM0 xm2c xm2cfgd low D

E15 DDR_DM1 DDR_DM1 xm2c xm2cfgd low D

G23 DDR_DM2 DDR_DM2 xm2c xm2cfgd low D

D9 DDR_DM3 DDR_DM3 xm2c xm2cfgd low D

G15 DDR_QUSE0 DDR_QUSE0 xm2c xm2cfga D

G17 DDR_QUSE1 DDR_QUSE1 xm2c xm2cfga D

A18 DDR_QUSE2 DDR_QUSE2 xm2c xm2cfga D

B18 DDR_QUSE3 DDR_QUSE3 xm2c xm2cfga D



Table 15 SDIO (VDDIO_SDIO) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO Alternate 2



Type2

R2 SDIO3_CLK UART1_TXD PMFM_PWM2 SDIO3_CLK SPI3_SCK GPIO_PA6 sdd sdio3cfg pu D

R1 SDIO3_CMD UART1_RXD PMFM_PWM3 SDIO3_CMD SPI2_SCK GPIO_PA7 sdb sdio3cfg pu D

R3 SDIO3_DAT0 PEX_CLKREQ1_N TWC_DO SDIO3_DAT0 SPI3_MISO GPIO_PB7 sdc sdio3cfg pu D




U3 SDIO3_DAT1 PEX_WAKE_N TWC_DIN SDIO3_DAT1 SPI3_MOSI GPIO_PB6 sdc sdio3cfg pu D

U4 SDIO3_DAT2 PMFM_PWM1 TWC_CLK SDIO3_DAT2 SPI3_CS0_N GPIO_PB5 sdc sdio3cfg pu D

R4 SDIO3_DAT3 PMFM_PWM0 TWC_CS_N SDIO3_DAT3 SPI3_CS1_N GPIO_PB4 sdc sdio3cfg pu D

T4 SDIO3_DAT4 PEX_RST1_N SPI4_MISO SDIO3_DAT4 SPI2_MISO GPIO_PD1 slxa sdio2cfg pu D

T6 SDIO3_DAT5 PEX_PRSNT1_N SPI4_SCK SDIO3_DAT5 SPI2_MOSI GPIO_PD0 slxk sdio2cfg pd D

R5 SDIO3_DAT6 SPDIF_IN SPI4_CS0_N SDIO3_DAT6 SPI2_CS0_N GPIO_PD3 slxc sdio2cfg pu D

U7 SDIO3_DAT7 SPDIF_OUT SPI4_MOSI SDIO3_DAT7 SPI2_CS1_N GPIO_PD4 slxd sdio2cfg pu D

P7 GPIO_PV4 PEX_PRSNT0_N GPIO_PV4 gpv sdio3cfg z D

R7 GPIO_PV5 PEX_RST0_N GPIO_PV5 gpv sdio3cfg z D

R6 GPIO_PV6 PEX_CLKREQ0_N GPIO_PV6 gpv sdio3cfg z D



Table 16 MIPI (AVDD_DSI_CSI) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO Alternate 2



Type2

AH20 DSI_CSI_RDN DSI_CSI_RDN mipi mipicfg B

AF21 DSI_CSI_RUP DSI_CSI_RUP mipi mipicfg B

AG26 CSI_CLKAP CSI_CLKAP csi mipicfg A

AH26 CSI_CLKAN CSI_CLKAN csi mipicfg A

AC20 CSI_CLKBP CSI_CLKBP csi mipicfg A

AB20 CSI_CLKBN CSI_CLKBN csi mipicfg A

AE20 CSI_D1AP CSI_D1AP csi mipicfg A

AD20 CSI_D1AN CSI_D1AN csi mipicfg A

AG23 CSI_D2AP CSI_D2AP csi mipicfg A

AH23 CSI_D2AN CSI_D2AN csi mipicfg A

AG24 CSI_D1BP CSI_D1BP csi mipicfg A

AH24 CSI_D1BN CSI_D1BN csi mipicfg A

AD21 DSI_CLKAN DSI_CLKAN dsi mipicfg A

AC21 DSI_CLKAP DSI_CLKAP dsi mipicfg A




AF20 DSI_D1AN DSI_D1AN dsi mipicfg A

AG20 DSI_D1AP DSI_D1AP dsi mipicfg A

AH21 DSI_D2AN DSI_D2AN dsi mipicfg A

AG21 DSI_D2AP DSI_D2AP dsi mipicfg A



Table 17 HDMI (AVDD_HDMI) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO Alternate 2



Type2

AF18 HDMI_RSET HDMI_RSET hdmi hdmicfg

AE17 HDMI_TXD0P HDMI_TXD0P hdmi hdmicfg

AE16 HDMI_TXD0N HDMI_TXD0N hdmi hdmicfg

AD18 HDMI_TXD1P HDMI_TXD1P hdmi hdmicfg

AC18 HDMI_TXD1N HDMI_TXD1N hdmi hdmicfg

AG18 HDMI_TXD2P HDMI_TXD2P hdmi hdmicfg

AH18 HDMI_TXD2N HDMI_TXD2N hdmi hdmicfg

AG17 HDMI_TXCP HDMI_TXCP hdmi hdmicfg

AF17 HDMI_TXCN HDMI_TXCN hdmi hdmicfg



Table 18 USB (USB_AVDD33) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO Alternate 2



Type2

AD17 USB1_VBUS USB1_VBUS usb usbcfg F

AD14 USB1_DP USB1_DP usb usbcfg E

AC14 USB1_DN USB1_DN usb usbcfg E

AC16 USB_REXT USB_REXT usb usbcfg F

AH14 USB3_VBUS USB3_VBUS usb usbcfg F

AG15 USB3_DP USB3_DP usb usbcfg E




AH15 USB3_DN USB3_DN usb usbcfg E



Table 19 PCIE (AVDD_PEX) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO Alternate 2



Type2

AC4 PEX_CLK_OUT1_N PEX_CLK_OUT1_N

AD4 PEX_CLK_OUT1_P PEX_CLK_OUT1_P

Y4 PEX_CLK_OUT2_N PEX_CLK_OUT2_N

Y5 PEX_CLK_OUT2_P PEX_CLK_OUT2_P

AA5 PEX_L0_RXN PEX_L0_RXN

AA4 PEX_L0_RXP PEX_L0_RXP

AD1 PEX_L0_TXN PEX_L0_TXN

AD2 PEX_L0_TXP PEX_L0_TXP

AA7 PEX_L1_RXN PEX_L1_RXN

AA6 PEX_L1_RXP PEX_L1_RXP

AC2 PEX_L1_TXN PEX_L1_TXN

AC1 PEX_L1_TXP PEX_L1_TXP

V4 PEX_L2_RXN PEX_L2_RXN

V3 PEX_L2_RXP PEX_L2_RXP

AA1 PEX_L2_TXN PEX_L2_TXN

AA2 PEX_L2_TXP PEX_L2_TXP

V6 PEX_L3_RXN PEX_L3_RXN

V5 PEX_L3_RXP PEX_L3_RXP

Y3 PEX_L3_TXN PEX_L3_TXN

Y2 PEX_L3_TXP PEX_L3_TXP

U1 PEX_REFCLKN PEX_REFCLKN

U2 PEX_REFCLKP PEX_REFCLKP

W6 PEX_TERMP PEX_TERMP




V1 PEX_TSTCLKN PEX_TSTCLKN

V2 PEX_TSTCLKP PEX_TSTCLKP



Table 20 HSIC (AVDD_HSIC, AVDD_IC) Signal Pinout with Multiplexing Functions


SFIO Alternate 1

SFIO SFIO Pin Pin Pad POR1 GPIO Alternate 2 Alternate 3 Group Config. Type2

AC15 HSIC_DATA HSIC_DATA

AD15 HSIC_STROBE HSIC_STROBE

AE15 HSIC_REXT HSIC_REXT

AG14 IC_DP IC_DP

AF14 IC_DN IC_DN

AE13 IC_REXT IC_REXT



Table 21 VDAC (AVDD_VDAC) Signal Pinout with Multiplexing Functions

Ball # Ball Name SFIO Primary Pin


Type2

AE19 VDAC_B VDAC_B tv tvcfg

AB18 VDAC_G VDAC_G tv tvcfg

AB17 VDAC_R VDAC_R tv tvcfg

AE18 VDAC_RSET VDAC_RSET tv tvcfg

AC17 VDAC_VREF VDAC_VREF tv tvcfg






Table 22 Crystal Oscillator (AVDD_OSC) Signal Pinout with Multiplexing Functions

Ball # Ball Name SFIO Primary Pin


Type2

E3 XTAL_IN XTAL_IN osc T J

E2 XTAL_OUT XTAL_OUT osc ZT J



Table 23 Other

Ball # Ball Name Pin Group

Pin Config. POR1 Pad

Type2

E6 THERMD_N

F7 THERMD_P

G12 PLL_S_PLL_LF

AE14 ACC1_DETECT usb usbcfg F

AF15 ACC3_DETECT usb usbcfg F

1. Default reset state. High; Low; PU: Pulled up; PD: Pulled down; T: Toggle; Z: High impedance state. 2. Pad types are described in Table 4


Table 24 Power, Ground, Reserved Pins

Type Ball Number Name

Core

M13, M14, M15, M16, N15, P15, P16, R16, T13, T15, T16, U13, U14, U16, U17, V17, V18, W20, Y19, Y20, Y21, AA20 VDD_CORE

Y18 VDD_CORE_SENSE

H9, J8, J9, J10, J11, K9, L9, M9, M11, N11, N12, P11, P12, P13, P14, R12, R13 VDD_CPU

N9 VDD_CPU_SENSE

V12, V13 VDD_RTC

Fuse AB15 VPP_FUSE

AB14 VPP_KFUSE

Test W9 VDD_TP

Digital I/O

P21 VDDIO_AUDIO

M8 VDDIO_BB

H20, J12, J13, J14, J15, J16, J17, J18, J19, J20, J21, K20, L16, L17, L20, M17, M18, M20, N18, N20, P20, R20, T20, U20, V20 VDDIO_DDR

H17 VDD_DDR_RX

AB8 VDDIO_HSIC

U22, V22 VDDIO_LCD

Y7, Y8, Y9 VDDIO_NAND

P1 VDDIO_SDIO

G18 VDDIO_SYS

H11 VDDIO_UART

L21 VDDIO_VI

U8, U9, V9 VDD_PEX

V8 VDDIO_PEX_CLK

Analog

R8,R9, T9 AVDD_PEX

P8 AVDD_PEX_PLL

Y16, AA17 AVDD_DSI_CSI

Y15, AA15 AVDD_HDMI

AA12 AVDD_HDMI_PLL

H12 AVDD_OSC

H14 AVDD_PLLA_P_C

Y1 AVDD_PLLE

H15 AVDD_PLLM

AA18 AVDD_PLLU

L7 AVDD_PLLX

Y14, AA14 AVDD_USB

AB9 AVDD_IC_USB

AB11 AVDD_USB_PLL

AH17 AVDD_VDAC

Ground

A1, A2, A27, A28, B1, B2, B4, B7, B10, B13, B16, B19, B22, B25, B27, B28, D2, D4, D25, D27, E7, E10, E13, E16, E19, E22, G2, G5, G24, G27, H8, H10, H13, H16, H18, H19, H21, K2, K5, K8, K21, K24, K27, L8, L11, L12, L13, L14, L15, L18, M12, N2, N5, N8, N13, N14, N16, N17, N21, N24, N27, P17, P18, R11, R14, R15, R17, R18, T2, T5, T8, T11, T12, T14, T17, T18, T21, T24, T27, U11, U12, U15, U18, U21, V11, V14, V15, V16, V21, W2, W5, W8, W21, W24, W27, Y11, Y12, Y13, AA8, AA9, AA10, AA13, AA16, AA19, AA21, AB2, AB5, AB24, AB27, AC19, AD7, AD10, AD13, AD16, AD19, AD22, AE2, AE4, AE25, AE27, AG1, AG2, AG4, AG7, AG10, AG13, AG16, AG19, AG22, AG25, AG27, AG28, AH1, AH2, AH27, AH28

GND




Type Ball Number Name

Y17 GND_CORE_SENSE

P9 GND_CPU_SENSE

Y10 GND_TP

AA11 VGND_TP

Do Not Connect

D22, G20, G21, M7, M21, R21, U5, V7, W4, Y6, AA3, AB4, AB6, AC3, AC13, AE21, AE22, AE23, AF23, AF24, AF26, AF27, AF28, AH14 DNC


3.3 Signal Description This section describes device signals. Additional alternate use signals are described in the Tegra 200 Series Technical Reference Manual.

3.3.1 Clock, Power & Reset Signals Table 25 Clock

Name Description Type

CLK_32K_IN 32-KHz clock provided by the PMU Input

XTAL_IN Crystal oscillator input. Tie to ground when using an external oscillator. Analog

XTAL_OUT Crystal oscillator output or external oscillator clock input Analog

SYS_CLK_REQ

System Clock Request. Used to enable an external oscillator or similar clock source. Tri-state when reset goes high - should be pulled up or down to ensure reference clock (input on XTAL_OUT pin) is available during power-on sequence. Polarity is programmable & toggled when going into or coming out of Deep Sleep to request external clock source to shut down or start up.

Output

Table 26 Control


CORE_PWR_REQ Core Power Request. Used to enable main Core power rail. Tri-state when reset goes high & should be pulled up or down to ensure Core power is on during power-on sequence. Polarity is programmable & toggled when going into or coming out of Deep Sleep to request PMU to remove or re-assert Core power.

Output

CPU_PWR_REQ CPU Power Request. Used to enable CPU power rail. Tri-state when reset goes high - should be pulled up or down to ensure Core power is on during power-on sequence. Polarity is programmable & toggled when going into or coming out of Idle to request PMU to remove or re-assert CPU power.

Output

PWR_I2C_SCL Power I2C Serial Clock. Bidirectional

PWR_I2C_SDA Power I2C Serial Data Bidirectional

PWR_INT_N PMU Interrupt. This is typically connected to an output on a PMU (Power Management Unit) and used to wake or otherwise inform the Tegra MWP some critical event has occured. This could be a low battery alert, a PMU RTC watchdog timer terminating, a new USB Host connection, etc.

Input

CLK_32K_OUT 32-KHz clock out Output

TEST_MODE_EN Test mode enable Input

SYS_RESET_N Power on reset Input

3.3.2 Memory Signals Table 27 DDR


DDR_A[14:0] DDR2 Address. DDR address lines. Output

DDR_DM[3:0] Data Masks. Mask signals for write data. Data is masked when DM is sampled high in the same period with the data being sent. Output

DDR_BA[2:0] Bank Select Output

DDR_CKE[1:0] Clock Enable. When high, activates DDR2 internal clocks. Low deactivates the clocks. Output

DDR_CLK Clock + Output

DDR_CLK_N Clock – Output

DDR_CS[1:0]_N Chip Selects. Active low select lines, considered part of the command code Output

DDR_DQ[31:0] Data Bus Bidirectional

DDR_DQS[3:0]P DDR_DQS[3:0]N

Data Strobes Positive & Negative. Differential pair of data strobes. Output for writes where data is edge aligned. Input for reads where data transition is centered. Bidirectional





DDR_QUSE[3:0]

DDR_ODT0 DRAM on die terminator control

DDR_COMP_PU Tied up to 1.8V wide range I/O power.

DDR_COMP_PD Tied to GND.

DDR_RAS_N Row Add Select Output

DDR_WE_N Write Enable Output

DDR_CAS_N Column Add Select Output

Table 28 GMI (General Memory Interface)


GMI_CS[7:0]_N Chip Selects Output

GMI_CLK Clock Output

GMI_A[27:0] Independent Address Bus Output

GMI_AD[27:00] Muxed Address/Data Bus Bidirectional

GMI_D[31:28] Independent Data Bus Bidirectional

GMI_ADV_N Advance

GMI_WR_N Write Strobe Output

GMI_OE_N Output Enable Output

GMI_IORDY I/O Ready Input

GMI_WAIT Wait handshake Input

GMI_INT[2:1] Interrupts Input

GMI_WP_N Write Protect Output

GMI_DPD Deep Power Down Output

GMI_RST_N Reset Output

Table 29 NAND

Signal Name Description Type

NAND_CE[7:0]_N Chip Selects Output

NAND_CLE Command Latch Enable Output

NAND_ALE Address Latch Enable Output

NAND_WE_N Write Enable Output

NAND_RE_N Read Enable Output

NAND_D[15:0] Data Bus Bidirectional

NAND_BSY0 Busy Input



Table 30 SFLASH (Serial FLASH)


SFLASH_CLK Serial FLASH Clock Output

SFLASH_CS0_N Chip Select Output

SFLASH_DIN Data Input Input

SFLASH_DOUT Data Output Output

3.3.3 Display Signals Table 31 LCD


LCD_PCLK Pixel Clock. Used by parallel RGB (simple TFT like) interfaces for latching color data. Frequency, Mode and Polarity is programmable. Output

LCD_CS[1:0]_N Chip Selects. Used for Host/CPU type interfaces. Typically used as active low signals, the polarity is programmable. Output

LCD_VSYNC Vertical Sync Output

LCD_HSYNC Horizontal Sync Output

LCD_DE Display Enable Output

LCD_DC[1:0] Data/Command select. Used for Host/CPU type interfaces, typically to select whether data is intended for commands to registers in the panel driver(s) or for RGB data to the frame buffer in the panel driver device. Output

LCD_WR_N Write Strobe. Used for Host/CPU type interfaces to latch command or other data. Polarity is programmable. Output

LCD_D[23:0] Data Bus Output

LCD_PWR[2:0] Power control. Intended for controlling external power enables where needed for some panels to sequence the power rails appropriately. Output

LCD_M1 Modulation Output

LCD_SCK Serial Clock. This signal, along with LCD_SDOUT, LCD_SDIN and LCD_CS0 or LCD_CS1, are used for serial Host/CPU type interfaces for writing/reading serial RGB data. These pins are multiplexed with one of the SPI interfaces (SPI3) which is used when command data is to be written/read instead.

Output

LCD_SDOUT Serial Data Out. Used for serial Host/CPU type interfaces for writing RGB data. See LCD_SCK description for more information. Output

LCD_SDIN Serial Data In. Used for serial Host/CPU type interfaces for reading RGB data. See LCD_SCK description for more information. Input

Table 32 DSI (MIPI Display Serial Interface)


DSI_CLKAN Clock Negative Output

DSI_CLKAP Clock Positive Output

DSI_D[2:1]AN Data Lanes 1 & 2 Negative Output

DSI_D[2:1]AP Data Lanes 1 & 2 Positive Output

DSI_CSI_RDN1 Reference Down. Provides a ground voltage reference point for the MIPI switching. A 49.9Ω, 1% resistor to Ground is required. Analog

DSI_CSI_RUP1 Reference Up. Provides a source voltage reference point for the MIPI switching. A 453Ω, 1% resistor to the AVDD_DSI_CSI power rail is required. Analog

1. The DSI_CSI_* signals are also available to the CSI signals and appear in the CSI Signal table.



Table 33 HDMI


HDMI_TXCN Transmit Clock Negative Output

HDMI_TXCP Transmit Clock Positive Output

HDMI_TXD[2:0]N Data Lanes 0, 1 & 2 Negative Output

HDMI_TXD[2:0]P Data Lanes 0, 1 & 2 Positive Output

HDMI_INT_N Interrupt. Used for Hot Plug detection. Input

HDMI_RSET Reference Set. For Current set resistor. Must be connected to external 1KΩ, 1% resistor to Ground Analog

Table 34 VDAC (Video DAC)


VDAC_R Video DAC Red. Provides Red signal for CRT or Component TV Out connections. For TV S-Video Output, this carries the Color (Chrominance) information. Analog

VDAC_G Video DAC Green. Provides Green signal for CRT or Component TV Out connections. For TV S-Video Output, this carries the Intensity (Luminance) information. Also used for Composite TV Output when this is the only TV Output interface

Analog

VDAC_B Video DAC Blue. Provides Blue signal for CRT or Component TV Out connections. Used for Composite TV Output when VGAC_R and VDAC_G are used to S-Video TV Output. Analog

VDAC_RSET Reference Set. For Current set resistor. Must be connected to external 1KΩ, 1% resistor to Ground Analog

VDAC_VREF Voltage Reference input to DAC. Must be connected to external 0.1uf capacitor to ground Analog

CRT_HSYNC Horizontal Sync for Analog RGB (VGA) Interface. This signal must be buffered/level shifted to match the CRT level which is typically 5V before going to the CRT connector pins. Output

CRT_VSYNC Vertical Sync for Analog RGB (VGA) Interface. This signal must be buffered/level shifted to match the CRT level which is typically 5V before going to the CRT connector pins. Output

Table 35 DDC (Display Data Channel)


DDC_SCL Serial Clock. Interface used for DDC for HDMI and CRT. As the pin only needs to drive low, and is 5V tolerant, it does not require a level translator. This line must be pulled up to 5V to communicate correctly with an HDMI or CRT display. Output

DDC_SDA Serial Data. See DDC_SCL description. Bidirectional

3.3.4 Audio Interfaces Table 36 DAP (Digital Audio Port)


DAP_MCLK[2:1] Master Clocks Output

DAP[5:1]_SCLK Serial Clock/Bit Clock. DAP pins support I2S/PCM and AC97 audio. Interface can be master or slave. Bidirectional

DAP[5:1]_FS Frame Sync/Word Select. DAP pins support I2S/PCM and AC97 audio. Interface can be master or slave. Bidirectional

DAP[5:1]_DOUT Data Out. DAP pins support I2S/PCM and AC97 audio. Interface can be master or slave. Output

DAP[5:1]_DIN Data In. DAP pins support I2S/PCM and AC97 audio. Interface can be master or slave. Input



Table 37 SPDIF (Sony/Philips Digital Interface)


SPDIF_IN Data In Input

SPDIF_OUT Data Out Output

3.3.5 Storage Interface Signals Table 38 SD/MMC


SDIO1_CLK SDIO2_CLK SDIO3_CLK HSMMC_CLK

SD/SDIO/MMC Clock. Supports SD, SD I/O and MMC protocol. SDIO2, SDIO3 and HSMMC interfaces support MMC up to 8-bits. All support 1 or 4-bit SD, SD I/O and MMC devices. Output

SDIO1_CMD SDIO2_CMD SDIO3_CMD HSMMC_CMD

SD/SDIO/MMC Command. See CLK description for device support. Internal pull-up resistors (~70KΩ-150KΩ) are available, but external resistors are required to meet the SD/MMC interface specifications. Bidirectional

SDIO1_DAT[3:0] SDIO2_DAT[7:0] SDIO3_DAT[7:0] HSMMC_DAT[7:0]

SD/SDIO/MMC Data bus. See CLK description for device support. Internal pull-up resistors (~70KΩ-150KΩ) are available, but external resistors are required to meet the SD/MMC interface specifications. Bidirectional

Table 39 ROM


ROM_CS[1:0]_N ROM Chip Select Output

ROM_A[22:0] ROM Address Output

ROM_BE[1:0]_N ROM Byte Enables Output

ROM_WR_N ROM Write strobe Output

ROM_RD_ ROM Read strobe Output

ROM_D[15:0] ROM Data Bidirectional

ROM_IORDY ROM I/O Ready Input

Table 40 EIDE (Enhanced IDE)


IDE_IRQ Interrupt. Interrupt request from external device Input

IDE_IORDY I/O Ready Input

IDE_A[2:0] Command/Address Output

IDE_CS[1:0] Chip Select Output

IDE_DMARQ DMA request. DMA data transfers between T20 and a drive, asserted by the drive when it is ready to transfer data to or from T20. Input

IDE_D[15:0] Data Bidirectional

IDE_WR_N Write Enable Output




IDE_OE_N Output Enable Output

IDE_RESET Reset Output

3.3.6 USB and Baseband Interfaces HSI and ULPI are only two of the interfaces available for the baseband. Other interfaces, such as SPI (Serial Peripherial Interface) and UART are described in the Inter-chip Interfaces section.

Table 41 USB


USB1_DN USB3_DN

USB 1 & 3 Data Negative. Bidirectional

USB1_DP USB3_DP

USB 1 & 3 Data Positive Bidirectional

USB_REXT Reference External. Generates an accurate bias current. Has an external precision biasing PD resistor of 1 KΩ ± 1%. Analog

USB1_VBUS

5V (typical) supply from the Host in a USB topology. When the USB interface is used in a mobile product as a Device, typically the USB interface is powered down, so the presence of USB_VBUS from a Host is detected by a PMU (Power Management Unit) which sends an interrupt or VBUS can be connected indirectly to a wake capable pin to wake the mobile device

Analog

Table 42 ULPI (Ultra Low Power Interface)


ULPI_CLK Clock. The interface can be configured as Link or PHY. The Tegra 200 Series MWP supports only single edge data transfers (only rising edge of clock). Bidirectional

ULPI_DATA[7:0] Data Bus. Driven low by the Link during idle. Bus ownership is determined by DIR. Bidirectional

ULPI_DIR Direction. Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high. When it doesn’t, it drives DIR low and monitors the bus for Link activity. The PHY also drives DIR high when it cannot accept data from the Link.

Bidirectional

ULPI_NXT Next. The PHY uses this to throttle the data from the Link. When Link is sending data, NXT indicates when current byte has been accepted. When the PHY is sending data, NXT indicates when a new byte is available for the Link. Bidirectional

ULPI_STP Stop. The Link asserts STP to stop the data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was just sent. If the PHY is sending data, STOP forces it to end it’s transfir and release control of the bus.

Bidirectional

Table 43 HSIC (High Speed Inter-Chip Interface)


HSIC_DATA Serial Data. Data is transferred when STROBE and DATA transition from IDLE to END-OF-IDLE which is defined by STROBE switching from high to low while data is low. Data is transferred for the next strobe transition and all subsequent transitions of STROBE until IDLE is again signaled.

Bidirectional

HSIC_STROBE Strobe. See Serial Data description Bidirectional

HSIC_REXT Reference External. Generates an accurate bias current. Has an external precision biasing PD resistor of 1 KΩ ± 1%. Analog



Table 44 IC-USB (Inter-Chip USB Interface)


IC_DN Data Negative Bidirectional

IC_DP Data Positive Bidirectional

IC_REXT Reference External. Generates an accurate bias current. Has an external precision biasing PD resistor of 1 KΩ ± 1%. Analog

Table 45 HSI (MIPI Host Serial Interface)


HSI_TX_DATA Transmit Data. DATA and FLAG together determine the data being sent. The DATA line always reflects the value being transmitted, while the FLAG only toggles when the bit value remains constant. A bit is transmitted when only one of these lines transitions.

Output

HSI_TX_FLAG Transmit Flag. See HSI_TX_DATA description Output

HSI_TX_READY Transmit Ready. READY indicates that the transmission of a new data frame can begin. It is negated by the receiver when the first bit of data in a frame is received and only asserted when a complete frame has been received and stored. Input

HSI_TX_WAKE Transmit Wake. WAKE is used to tell the receiver that the transmitter is ready to start a transmission. This either wakes the receiver, or prevents it from going into sleep mode. The READY signal is activated by the receiver it is ready to receive data.

Output

HSI_RX_DATA Receive Data. See description of Transmit Data. Input

HSI_RX_FLAG Receive Flag. See description of Transmit Flag Input

HSI_RX_READY Receive Ready. See description of Transmit Ready Output

HSI_RX_WAKE Receive Wake. See description of Transmit Wake Input

3.3.7 Inter-chip Interfaces Table 46 PCIe


PEX_CLK_OUT[2:1]_P PEX_CLK_OUT[2:1]_N

Clock Output

PEX_L[3:0]_RXP PEX_L[3:0]_RXN

Receive data, differential analog input for each lane Input

PEX_L[3:0]_TXP PEX_L[3:0]_TXN

Transmit data, differential analog output for each lane Output

PEX_REFCLKP PEX_REFCLKN

PCI Express Reference Clocks These signals are a differential reference clock pair. They may be mapped to be associated with any of the PCI Express controllers via software configuration.

Output

PEX_TSTCLKP PEX_TSTCLKN

Test clock Output

PEX_CLKREQ[1:0]_N PCI Express Reference Clock Request This signal is used by a PCI Express device to indicate it needs the PEX_REFCLKP and PEX_REFCLKN to actively drive reference clock. It may be mapped to any of the PCI Express controllers via software configuration

Input

PEX_WAKE_N PCI Express Wake This signal is used as the PCI Express defined WAKE# signal. When asserted by a PCI Express device, it is a request that system power be restored. No interrupt or other consequences result from the assertion of this signal.

Input

PEX_RST[1:0]_N PCI Express Reset This signal provides a reset signal to all the PCI Express links. It must be asserted 100 ms after the power to the PCI Express slots has stabilized.

Output

PEX_PRSNT[1:0]_N PCI Express hot plug detection Input

PEX_TERMP PCI Express Termination Compensation PCI Express pad termination compensation I/O. Optionally used by the PCI Express pads to calibrate their internal termination resistance.



Table 47 SPI (Serial Peripheral Interface)


SPI[4:1]_SCK Serial Clock. The SPI interfaces can be configured as Master or Slave. The master drives the clock. The clock phase and polarity is programmable. Bidirectional

SPI[4:1]_MOSI Master Out, Slave In. When configured as master, the Tegra MWP drives data (output) onto this pin. When a slave, data is received (input) on this pin. Bidirectional

SPI[4:1]_MISO Master In, Slave Out. When configured as master, the Tegra MWP receives data (input) on this pin. When a slave, data is driven (output) onto this pin. Bidirectional

SPI1_CS0_N Chip Select (SPI1). Single chip select option for SPI1 Bidirectional

SPI2_CS[3:0]_N Chip Selects (SPI2). Four chip selects potentially available for SPI2 depending on pin multiplexing. These can be used to differentiate between more than one SPI slave devices. Bidirectional

SPI3_CS[3:0]_N Chip Selects (SPI3). Four chip selects potentially available for SPI3 depending on pin multiplexing. These can be used to differentiate between more than one SPI slave devices Bidirectional

SPI4_CS[1:0]_N Chip Selects (SPI4). Two chip selects potentially available for SPI2 depending on pin multiplexing. These can be used to differentiate between two SPI slave devices Bidirectional

Table 48 I2C (Inter-Chip Communication)


GEN1_I2C_SCL GEN2_I2C_SCL

Serial Clock for General Purpose I2C interfaces 1 & 2 Bidirectional

GEN1_I2C_SDA GEN2_I2C_SDA

Serial Data for General Purpose I2C interfaces 1 & 2 Bidirectional

Table 49 UART


UART[5:1]_TXD Transmit (UARTs 1-5) Output

UART[5:1]_RXD Receive (UARTs 1-5) Input

UART[5:1]_CTS_N Clear to Send (UARTs 1-5) Input

UART[5:1]_RTS_N Request to Send (UARTs 1-5) Output

UART1_DCD_N Data Carrier Detect for UART1 only) Input

UART1_DSR_N Data Set Ready (UART1 only) Input

UART1_DTR_N Data Terminal (UART1 only) Output

UART1_RI_N Ring Indicator (UART1 only) Input

Table 50 TWC (Three-Wire Connect)


TWC_CLK Clock Output

TWC_CS_N Chip Select Output

TWC_DIN Data Input Input

TWC_DO Data Output Output



3.3.8 Video Input Interfaces Table 51 CSI (MIPI Camera Serial Interface)


CSI_CLKAN Clock Negative A interface Input

CSI_CLKAP Clock Positive A interface Input

CSI_CLKBN Clock Negative B interface Input

CSI_CLKBP Clock Positive B interface Input

CSI_D[2:1]AN Data Negative Lanes 1 & 2 for A interface Bidirectional

CSI_D[2:1]AP Data Positive Lanes 1 & 2 for A interface Bidirectional

CSI_D1BN Data Negative B interface Bidirectional

CSI_D1BP Data Positive B interface Bidirectional

Table 52 VI (Video Input)


VI_CLK Pixel Clock Input

VI_MCLK Master Clock Output

VI_VSYNC Vertical Sync Input

VI_HSYNC Horizontal Sync Input

VI_D[11:0] Data Bus Input

VI_GP[6:0]

General Purpose I/Os. VI_GP[5:3] & VI_GP0 are used as GPIOs, typically to control functions on a video input device such as Reset, Power-down, Flash Light enable, etc. VI_GP[2:1] are typically uses as an I2C interface for communicating with an imager or other video input device. This interface is the CAM_I2C_SCL/SDA described below. VI_GP6 also supports PWM and other functionality to control flash brightness and timing or a shutter.

Bidirectional

Table 53 Camera I2C


CAM_I2C_SCL Serial Clock Bidirectional

CAM_I2C_SDA Serial Data Bidirectional

3.3.9 Miscellaneous Interfaces Table 54 JTAG


JTAG_TCK Test Clock Input

JTAG_TDI Test Data In Input

JTAG_TDO Test Data Out Output

JTAG_TMS Test Mode Select Input

JTAG_TRST_N Test Reset Input

JTAG_RTCK Return Test Clock Input



Table 55 Keyboard


KB_COL[7:0] Columns Input

KB_ROW[15:0] Rows Output

Table 56 OWR (One-Wire Interface)


OWR One Wire Signal Bidirectional

Table 57 PWFM (Pulse Width/Frequency Modulation)


PMFM_PWM[3:0] Pulse Width Frequency Modulation. These are four outputs from the four pulse width frequency modulators. They output a frequency divided down from a 24MHz source and output a pulse of programmed width. Output

3.3.10 Power, Ground and Reserved Table 58 Core Power


VDD_CORE Main Core power. Input

VDD_CORE_SENSE Core power feedback (goes to PMU). Output

VDD_CPU CPU power. Input

VDD_CPU_SENSE CPU power feedback (goes to PMU). Output

VDD_RTC RTC (Always-on) power. Input

VDD_TP Measurement test point. Output

Table 59 Digital Interface Power


VDD_PEX PCIe core digital power. Input

VDD_DDR_RX Voltage reference used by DDR pads (supports both DDR2 and LPDDR2). Input

VDDIO_AUDIO Audio I/O partition power. Input

VDDIO_BB Baseband I/O partition power. Input

VDDIO_DDR DDR memory interface power Input

VDDIO_HSIC High Speed Inter-Chip interface I/O power. Input

VDDIO_LCD LCD interface I/O power. Input

VDDIO_NAND NAND I/O partition power. Input

VDDIO_PEX_CLK Power for PCIe clock. Input

VDDIO_SDIO SD/SDIO I/O partition power. Input

VDDIO_SYS System I/O partition power. Input

VDDIO_UART UART I/O partition power. Input

VDDIO_VI Video Input interface I/O power. Input

NOTE: I/O partition refers to the blocks of interface pins that fall under each section or partition. Some interfaces can be brought out on different I/O partitions.



Table 60 Analog Power


AVDD_OSC Oscillator I/O power. Input

AVDD_PEX Analog PCIe power. Input

AVDD_PEX_PLL Dedicated PCIe PLL power. PCIe controller internal PLL. Input

AVDD_PLLE PLLE power. PLLE is dedicated to the PCIe interface Input

AVDD_PLLA_P_C

Multipurpose pin providing support for: PLLA power. PLLA is source for audio. PLLP power. PLLP is fixed 216 MHz source for most peripherals. PLLC power. PLLC is general purpose PLL.

Input

AVDD_PLLM PLLM power. PLLM is the source for the external memory controller. Input

AVDD_PLLU PLLU power. PLLU and PLLD are both powered by AVDD_PLLU. PLLU is the source for the USB PHY and controllers, PLLD is the souce for DSI and display subsystem in general. Input

AVDD_PLLX PLLX power. PLLX is dedicated to the Cortex-A9 CPU complex. Input

AVDD_USB USB I/O power. Input

AVDD_USB_PLL Dedicated USB PLL power. USB controller internal PLL. Input

AVDD_DSI_CSI DSI & CSI I/O power. Input

AVDD_HDMI HDMI I/O power. Input

AVDD_HDMI_PLL Dedicated HDMI PLL power. HDMI controller internal PLL Input

AVDD_VDAC Video DAC power Input

AVDD_IC_USB IC-USB power Input

Table 61 Fuse Power


VPP_FUSE Fuse Source.

VPP_KFUSE K Fuse Source. Must be pulled down to GND with a 10K ohm resistor.

Table 62 Other


THERMD_N THERMD_P

Differential Thermal Diode pins.

PLL_S_PLL_LF Loop filter cap for PLLS (6800pf to GND)

ACC1_DETECT ACC3_DETECT

Accessory detect 1 and 3. The detect pins are optional wake pins and can be used to detect when a device is connected if the Tegra MWP is configured as a host. Input

Table 63 Ground and Reserved


GND Ground Input

GND_CORE_SENSE Ground for CORE power feedback. Output

GND_CPU_SENSE Ground for CPU power feedback. Output

GND_TP VGND_TP

Measurement test points. Output

DNC Do Not Connect



4.0 DC Characteristics Note: This section contains preliminary estimates based on design targets and may be revised during

characterization.

4.1 Absolute Maximum Ratings The absolute maximum ratings describe stress conditions. These parameters do not set minimum and maximum operating conditions that will be tolerated over extended periods of time. If the device is exposed to these parameters for extended periods of time, no guarantee is made and device reliability may be affected.

It is not recommended to operate the Tegra 200 series MWP under these conditions, recommended operating conditions are provided in section 4.2

WARNING: Exceeding the listed conditions may damage and/or affect long-term reliability of the part. Tegra 200 series processors should never be subjected to conditions exceeding the absolute maximum ratings.

Table 64 Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

VM_CORE Core power rails -0.5 1.32 V VDD_CORE, VDD_RTC

VM_CPU CPU power rails -0.5 1.1 V VDD_CPU

VM_PEX 1.05V PCIE power rails -0.5 1.1 V AVDD_PEX, AVDD_PEX_PLL, VDD_PEX, AVDD_PLLE

VM_PLL 1.1V PLL power rails -0.5 1.21 V AVDD_PLLM, AVDD_PLLA_P_C, AVDD_PLLU, AVDD_PLLX

VM_12 1.2V power rails -0.5 1.32 V AVDD_DSI_CSI, VDDIO_DDR (LPDDR2), VDDIO_HSIC

VM_18 1.8V power rails -0.5 1.98 V AVDD_OSC, VDDIO_SYS, AVDD_HDMI_PLL, VDDIO_DDR (DDR2)

VM_33 3.3V power rails -0.5 3.63 V AVDD_HDMI, AVDD_USB, AVDD_USB_PLL

VM_DDRX Voltage reference used by DDR pads -0.5 3.63 V VDD_DDR_RX

VM_ICUSB IC-USB power rail -0.5 3.6 V AVDD_IC_USB

VM_VDAC VDAC power rail -0.5 3.45 V AVDD_VDAC

VM_WR Wide range I/O power rails -0.5 3.63 V VDDIO_AUDIO, VDDIO_BB, VDDIO_LCD, VDDIO_NAND, VDDIO_SDIO, VDDIO_UART, VDDIO_VI

VM_PIN Voltage applied to any powered I/O pin -0.5 VDD + 0.5 V 1

VM_VBUS USB Supply voltage -0.5 -0.5

6.0 0.5

V V

USB_VBUS enabled USB_VBUS not enabled

VESD Human Body Model (HBM) 2000 V

Electrostatic Discharge Voltage Charge Device Model (CDM) 500 V

Tstg Storage temperature -40 125 °C

1. VBUS (VM_VBUS) is an exception the stated VM_PIN specification and has its own absolute maximum specification.

Note: All power rails are with respect to GND. VDD = Common name for powered voltage rail under consideration

Tegra 200 Series Mobile Web Processor DC Characteristics


4.2 Recommended Operating Conditions The parameters listed in following table are specific to a temperature range and operating voltage. Operating the Tegra 200 series MWP beyond these parameters is not recommended. Exceeding these conditions for extended periods may adversely affect device reliability.

Table 65 Tegra 250 Recommended Operating Conditions (Voltage Measured at Tegra 250 Ball)

Symbol Parameter Min Typical Max Unit Notes

VR_CORE

Core power rails - Fixed Voltage Implementation 1.14 1.20 1.26 V VDD_CORE, VDD_RTC 5, 6, 8

Core power rails – DVFS Setpoints

1.000, 1.025, 1.050, 1.075, 1.100, 1.125, 1.150, 1.175, 1.200

V

VDD_CORE, VDD_RTC 1, 2, 3, 4, 5, 6, 8

AC + DC Error at any DVFS Point 5.0 %

VR_CPU

CPU power rails – Fixed Voltage Implementation 0.855 0.9 0.945 V VDD_CPU 5, 6, 8

CPU power rails – DVFS Setpoints

0.750, 0.775, 0.800, 0.825, 0.850, 0.875, 0.900, 0.925, 0.950, 0.975, 1.000, 1.025, 1.050

V VDD_CPU1, 3, 4, 5, 6, 8

AC + DC Error at any DVFS Point 5.0 %

VR_PEX 1.05V PCIE power rails 1.0185 1.05 1.0815 V AVDD_PEX, AVDD_PEX_PLL, VDD_PEX, AVDD_PLLE

VR_PLL 1.1V PLL power rails 1.045 1.1 1.155 V AVDD_PLLM, AVDD_PLLA_P_C, AVDD_PLLU, AVDD_PLLX

VR_12 1.2V power rails 1.14 1.20 1.26 V AVDD_DSI_CSI, VDDIO_HSIC, VDDIO_DDR (LPDDR2)

VR_18 1.8V power rails 1.71 1.80 1.89 V AVDD_OSC, VDDIO_SYS, AVDD_HDMI_PLL, VDDIO_DDR (DDR2)

VR_33 3.3V power rails 3.135 3.3 3.465 V AVDD_HDMI, AVDD_USB 7, AVDD_USB_PLL, VDDIO_PEX_CLK

VR_DDRX Voltage reference for DDR 2.66 2.8, 3.3 3.465 V VDD_DDR_RX

VR_ICUSB IC-USB power rail 1.8V 3.0V

1.71 2.85

1.80 3.0

1.89 3.15

V V

AVDD_IC_USB

VR_VDAC VDAC power rail 2.66 2.80 2.94 V AVDD_VDAC

VR_WR18

VR_WR33

Wide range I/O power rails 1.8V 2.8 - 3.3V

1.71 2.66

1.80 2.8, 3.3

1.89 3.465

V V

VDDIO_AUDIO, VDDIO_BB, VDDIO_LCD, VDDIO_NAND, VDDIO_SDIO, VDDIO_UART, VDDIO_VI

VR_FUSE Fuse Programming Power 3.135 3.3 3.465 V VPP_FUSE

tTEMP-A Operating temperature (ambient) 0 25 70 °C Must be maintained within Max TJ

TJ Operating temperature as sensed from Thermal Diode 90 °C

1. These voltage rails are intended to operate over the range defined by the Dynamic Voltage and Frequency Scaling (DVFS) mechanism. 2. VDD_CORE and VDD_RTC must be within 170mV when both are on.

3. Minimum core voltage may be updated at the end of the characterization.

4. PMU has to be able to supply this core voltage range. 5. At power on, VDD_CORE and VDD_RTC must run at 1.20V and VDD_CPU must run at 1.0V. After power on with software enabled voltages can vary to accommodate different

operating conditions.

6. Do not tie VDD_CORE and VDD_CPU voltage regulators together. 7. USB1_VBUS should not be driven until AVDD_USB is powered.

8. VDD_CPU must maintain a lower voltage relative to VDD_CORE (VDD_CPU < VDD_CORE). This voltage differential is TBD pending further characterization.

Tegra 200 Series Mobile Web Processor DC Characteristics


4.3 DC Characteristics Voltages less than the minimum stated value can be interpreted as an undefined state or logic level low which may result in unreliable operation. Voltages exceeding the maximum value can damage and/or adversely affect device reliability.

Table 66 DC Characteristics

Symbol Parameter Min Max Unit Notes

VIL CMOS Input Low Voltage -0.5 0.25 x VDD V CMOS inputs.

VIH CMOS Input High Voltage 0.75 x VDD 0.5 + VDD V CMOS inputs.

VIL-XO Input Low Voltage –0.5 0.1 x VDD V XTAL_OUT pin when used as input for external clock.

VIH-XO Input High Voltage 0.9 x VDD 0.5 + VDD V XTAL_OUT when used as input for external clock.

VIL-VBUS VBUS Detect Input Low Voltage –0.5 0.8 V USB VBUS input.

VIH-VBUS VBUS Detect Input High Voltage 3.35 5.25 V USB VBUS input.

VIL-DDC HDMI INT (HPD) and DDC Input Low Voltages -0.5 0.25 x VDDIO_LCD V HDMI and DDC inputs

VIH-DDC HDMI INT (HPD) and DDC Input High Voltages 0.75 x VDDIO_LCD 5.3 V HDMI and DDC inputs

VIL-OWR OWR Input Low Voltage -0.5 0.25 x VDDIO_SYS V OWR Input

VIH-OWR OWR Input High Voltage 0.75 x VDDIO_SYS 5.3 V OWR Input

VOL Output Low Voltage 0.15 x VDD V CMOS outputs.

VOH Output High Voltage 0.85 x VDD V CMOS outputs.

IIN Input Leakage Current -1 1 uA CMOS input pins with no internal pullup or pulldown enabled.

IOZ Output Tristate Leakage Current -1 1 uA CMOS pins with no internal pullup or pulldown enabled. Pin configured as output, but output disabled.

CIN Pin Capacitance 3 5 pf CMOS pins.

4.4 Power-up Ramp Time Requirement When enabling any power rail to its nominal voltage (Vnom), the rise time must be at least 20usec or slower to prevent the power ESD protection clamp from being turned on, where Vnom is the nominal power voltage level.

The fastest slew-rate (SR_max) in each power rail is SR_max = 0.8Vnom/20us = 40Vnom (V/ms). For example, the maximum slew rate for a 1.2V rail is 48V/ms and the maximum slew rate for a 3.3V rail is 132V/ms.

For each power rail, the slew rate of any two neighboring points between 0.1 x Vnom and 0.9 x Vnom must be equal to or slower than SR_max.

For each power rail, the slew rate of any two neighboring points higher than 1.1 x Vnom must be equal to or slower than SR_max.

There are no ramp time requirements between 0.7Vnom and 1.3Vnom (+/-30%) for any voltage fluctuations or voltage adjustments.


5.0 AC Characteristics

NOTE: This section contains preliminary information based on design targets and may be revised during characterization and testing.

5.1 Clocking Specifications The Tegra 200 series MWP requires two clock sources including a 32KHz clock from an external source, and a higher frequency reference clock either from an external source, or via a connected crystal. The input timing requirements for the external clock sources as well as the requirements for the crystal and associated components are described in the following sections.

5.1.1 32KHz Clock Input Timing The 32KHz clock is input on the CLK_32K_IN ball. This is a standard CMOS input on the VDDIO_SYS power rail operating at 1.8V ± 5%.

Figure 3 CLK_32K_IN Clock Input Timing Diagram

Table 67 CLK_32K_IN Clock Input Timing Parameters

Symbol Parameter Min Typ Max Unit

tCP

CLK_32K_IN Input period 30.52 us

CLK_32K_IN Input frequency 32.375 32.768 33.161 KHz

CLK_32K_IN duty cycle 40 60 %

CLK_32K_IN tolerance Basic functionality Accurate RTC functionality (e.g. time keeping)1

1.2 100

% ppm

1. This accuracy may not be required if RTC in PMU used for this purpose.

2. There are no specific requirements for rise/fall times on CLK_32K_IN, but the edges should be increasing (rising) or decreasing (falling) only – There should be no significant glitches on the edges. The input is Schmidt trigger, so some minor noise is allowed.

5.1.2 External Reference Clock Input Timing The XTAL_OUT pin can either be used in conjunction with XTAL_IN to support a crystal connection, or XTAL_OUT can be used as an input for an external reference clock. The crystal oscillator block is powered by AVDD_OSC

Figure 4 XTAL_OUT as Input for External Reference Option


Tegra 200 Series Mobile Web Processor AC Characteristics


Figure 5 XTAL_OUT External Clock Input Option Timing Diagram

tCP

tFTRTt

XTAL _OUT

Table 68 XTAL_OUT External Clock Input Option Timing Parameters


tCP XTAL_OUT Input period (12MHz) 83.33 ns

tCP XTAL_OUT Input period (13MHz) 76.92

tCP XTAL_OUT Input period (19.2MHz) 52.08

tCP XTAL_OUT Input period (26MHz) 38.46

XTAL_OUT duty cycle 45 55 %

XTAL_OUT Jitter (RMS) 250 ps

tRT XTAL_OUT edge rise time 2 ns

tFT XTAL_OUT edge fall time 2 ns

5.1.3 Crystal Connection & Selection The Tegra 200 series MWP supports the use of an external reference clock input to XTAL_OUT or a crystal connection to XTAL_OUT and XTAL_IN to generate the reference clock internally. The crystal oscillator block is powered by AVDD_OSC. Table 69 contains the requirements for the crystal used, the value of the parallel bias resistor and information to calculate the values of the two external load capacitors (CL1 and CL2) shown in the circuit.

Figure 6 Crystal Connection

Table 69 Crystal and Circuit Requirements


FP Parallel resonance crystal Frequency 12, 13, 19.2, 26

MHz

FTOL Frequency Tolerance ±50 ppm

CL Load Capacitance for crystal parallel resonance 5 7 10 pf

DL Crystal Drive Level 300 uW

RBIAS External Bias Resistor 2 MΩ




ESR Equivalent Series Resistance 12MHz, 13MHz & 19.2MHz 26MHz

80 50

Ω

tSTART Start-up time TBD ms

1. FP, FTOL, CL & DL are found in the Crystal Datasheet. 2. External Bias resistor RBIAS provides feedback to the oscillator so oscillation will occur when power is applied.

3. Start-up time is defined as the time from AVDD_OSC reaching valid ON level (1.8V ±5%) and the time the internal oscillator is stable and within 5% of the target frequency (as measured on test pin during characterization).

4. ESR = RM * (1 + C0/CL)2 where RM is the Motional Resistance and C0 is the Shunt Capacitance from the Crystal datasheet. Some crystal datasheets may specify ESR directly –

consult the manufacturer if it is not clear whether ESR or RM are specified.

The value of the external load capacitors (CL1 and CL2) can be obtained using the following formula:

CL = (CL1 x CL2) / (CL1 + CL2) + CPCB or (CLx / 2) + CPCB

Since CL1 and CL2 are typically of equal value. Solving for CLx gives the following formula:

CLx = (CL1 x 2) – (CPCB x 2)

- CL = Load capacitance from Crystal datasheet

- CPCB is the PCB capacitance (trace, via, pad, etc.)

5.2 Display Controller The display controller supports a broad range of interfaces and configurations for driving LCD or similar displays. Some of the common types include:

Simple RGB Interface with Pixel Clock, Horizontal/Vertical Syncs, and Display Enable – usually RAMless

Parallel CPU style with Write Enable, Chip Select, Data/Command and 8 to 24 data bits – usually has it’s own frame buffer RAM

Serial SPI type with Clock, Chip Select, embedded or external Data/Command pin, Output and possibly input data pins

There are two display controllers in the Tegra 200 series processor. The LCD interface signals for the 1st controller are “LCD1_xxx” while the signals assigned to the 2nd controller are “LCD2_xxx”. The LCD 1 controller signals are the Primary position in the Signal Pinout pin multiplexing table. LCD 2 signals are the Alternate 1 position. Since the timing for both are the same, LCDx_xxx will be used to indicate either controller. The most common digital parallel and serial panel interfaces are covered in the following sections.

5.2.1 RGB Interface This display interface is used to drive panels or other display devices that typically require a pixel clock, horizontal and vertical syncs and display enable. These devices do not usually have their own RAM (frame buffer) but are refreshed out of the memory located in an external controller, in this case, the Tegra 200 series MWP.

The Tegra 200 series display controller drives the interface signals based off an internal clock. The external LCD_PCLK runs at the same frequency as the internal clock for the most common cases. The timing diagrams/tables show the Data (LCDx_D[23:0]), Syncs (LCDx_HSYNC and LCDx_VSYNC) and display enable (LCDx_DE) signals with respect to the latching edges of the external PCLK. PCLK can be programmed for active high or active low polarity. With active high polarity, the pins transition on the rising edge of the internal clock to be latched by the external device with the falling edge. Active low polarity, means the pins transition on the falling edge of the internal clock to be latched by the external device with the rising edge.



Figure 7 RGB Interface Timing Diagram

Table 70 RGB Interface Timing Parameters


tCP

LCDx_PCLK period 8.33 ns

LCDx_PCLK frequency 120 MHz

LCDx_PCLK duty cycle 40 60 %

tDSKEW LCDx_D[23:0] skew relative to PCLK edge1 -22 22

tCSKEW LCDx_HSYNC, LCDx_VSYNC, LCDx_DE skew relative to LCDx_PCLK edge1 -22 22

tODSU LCDx_D[23:0] output setup to LCDx_PCLK latching edge1 tCP/2 – 2

tCSSU LCDx_HSYNC, LCDx_VSYNC, LCDx_DE setup to LCDx_PCLK latching edge1 tCP/2 – 2

tODSU LCDx_D[23:0] output hold from LCDx_PCLK latching edge1 tCP/2 – 2

tCSSU LCDx_HSYNC, LCDx_VSYNC, LCDx_DE hold from LCDx_PCLK latching edge1 tCP/2 – 2

tRT Rise time 13 ns

tFT Fall time 13 ns

1. LCDx_PCLK polarity programmed high or low. When high, data, control & syncs skew times are relative to the rising edge of LCDx_PCLK/ LCDx_WR_N. When low, they are relative to the falling edge.

2. The skew values are valid when the loads on the clock and data/control are similar and the pad configuration registers are programmed with the same characteristics.

5.2.2 Parallel CPU Type Interface Some display drivers have their own timing controller and frame buffer (pixel data RAM) integrated. In these cases, a CPU style interface is used to connect to the Tegra 200 series MWP. These interfaces are usually comprised of a chip select, write strobe and a data/command pin to select between data to registers or other control logic or pixel data to the frame buffer. The same data pins are used for both commands and pixel data.

Initialization Cycles

When initializing the external display device registers or logic, the Tegra 200 series MWP uses a simple software driven mechanism. The CS, DC and Data pins are configured as GPIOs and the application toggles these in the proper sequence to transfer data and latch it into the display driver.

Pixel Data Transfers

When continuous pixel data transfers are required (similar to the RGB Interface case), the pins are reconfigured as clock, chip select, write strobe and data and driven by the display controller hardware.

Similar to the RGB Interface case, the Tegra 200 series display controller drives the interface signals based off an internal clock. The external LCDx_PCLK runs at the same frequency as the internal clock for typical cases. The timing diagram shows the Data (LCDx_D[23:0]), chip select (LCDx_CSx) write strobe and data/command (LCDx_DCx) signals with respect to edges of the write strobe (LCDx_PCLK for primary display & LCDx_WR_N for alternate display). LCDx_PCLK or LCD_WR_N can be



programmed for active high or active low polarity. With active high polarity, the pins transition on the rising edge of the internal clock to be latched by the external device with the falling edge of LCDx_PLK or LCDx_WR_N. The LCDx_DCx pin can be programmed to either stay high all the time while in pixel transfer mode, or set to deactivate during the Horizontal and Vertical blank periods.

Figure 8 Parallel CPU Type Display Interface Timing Diagram

Table 71 Parallel CPU Type Display Interface Timing Parameters


tP Internal clock period 8.33 ns

Internal clock frequency 120 MHz

tCP LCDx_PCLK / LCDx_WR_N period 1 tP

LCDx_PCLK / LCDx_WR_N duty cycle 40 60 %

tODSU LCDx_D[23:0] output setup to 1st LCDx_PCLK / LCDx_WR_N latching edge1 tP/2 - 2 ns

tCSSU LCDx_CS[1:0]_N setup to 1st LCDx_PCLK / LCDx_WR_N latching edge1 tP/2 - 2 ns

tDCSU LCDx_DCx setup to 1st LCDx_PCLK / LCDx_WR_N latching edge1 tP/2 - 2 ns

tODH LCDx_D[23:0] hold from last LCDx_PCLK / LCDx_WR_N latching edge1 tP/2 - 2 ns

tCSH LCDx_CS[1:0]_N hold from last LCDx_PCLK / LCDx_WR_N latching edge1 tP/2 - 2 ns

tDCH LCDx_DCx hold from last LCDx_PCLK / LCDx_WR_N latching edge1 tP/2 - 2 ns

1. LCDx_PCLK/ LCDx_WR_N polarity can be programmed high or low. When high, data, control & syncs skew times are relative to the rising edge of LCDx_PCLK/ LCDx_WR_N. When low, they are relative to the falling edge.

Parallel CPU Type IS (Initialization Sequence) Cycles

In addition to the initialization usually required to configure the registers/logic in a display driver with a built in controller, some also require periodic re-initialization of some of the registers. Often this is to set the memory pointers back to the beginning of the on-chip display buffer. The Tegra 200 series MWP supports what are called IS (Initialization Sequences) which occur at the beginning of each new frame. The IS registers are programmed such that the LCDx_CSx_N, LCDx_PCLK or LCDx_WR_N, LCDx_DCx and LCDx_D[23:0] pins are driven in the correct sequence to correctly achieve the necessary command writes.

These IS sequences are driven by hardware rather than software as is the case for the early initialization cycles. The timing for these cycles is shown in Figure 9. The IS cycles run at half the speed of the normal Pixel data transfers. The write pulse high (or low depending on polarity) time is one full internal clock. The initial chip select and each data/command signal transition are 2 clocks prior to the latching edge of the write strobe and remain stable for one clock after the strobe is de-asserted.



Four 32-bit Initialization Sequence registers are programmed with values that translate in the high or low states on the CDx_PCLK/LCDx_WR_N, LCDx_DCx, and LCDx_D[23:0] pins for each staage of the IS (initialization sequence). This allows any arbitrary sequence to be supported as long as it is not too long to fit in the available 128-bits. 9-bit and 18-bit interface widths can be selected. 8- and 16-bit I/Fs can be supported by only using part of the 9- or 18-bits available. For 9-bits (or 8), up to 10 IS cycles are possible. For 18-bits (or 16), up to 6 instructions are possible.

Figure 9 Parallel CPU Type IS (Initialization Sequence) Timing Diagram

Table 72 Parallel CPU Type IS (Initialization Sequence) Timing Parameters


tP Internal clock period 8.33 ns

Internal clock frequency 120 MHz

tCH LCDx_PCLK / LCDx_WR_N high time 3tP – 2 ns

tCL LCDx_PCLK / LCDx_WR_N low time tP – 2 ns

tCSSU LCDx_CS[1:0]_N setup to 1st LCDx_PCLK / LCDx_WR_N edge 2tP – 2 ns

tCSH LCDx_CS[1:0]_N hold from to 2nd LCDx_PCLK / LCDx_WR_N edge tP – 2 ns

tODSU LCDx_D[23:0] output setup to 1st LCDx_PCLK / LCDx_WR_N edge 2tP – 2 ns

tODSU LCDx_D[23:0] output hold from 2nd LCDx_PCLK / LCDx_WR_N edge tP – 2 ns

tDCSU LCDx_DC[1:0] setup to 1st LCDx_PCLK / LCDx_WR_N edge 2tP – 2 ns

tDCH LCDx_DC[1:0] hold from 2nd LCDx_PCLK / LCDx_WR_N edge tP – 2 ns

1. LCDx_PCLK/ LCDx_WR_N polarity can be programmed active high or active low. When active high, LCDx_CS[1:0]_N, data, LCDx_DC[1:0] times are relative to the rising edge of LCDx_PCLK/ LCDx_WR_N. When active low, they are relative to the falling edge.

5.2.3 Serial CPU Type Interface For command and register initialization, one of the SPI interfaces (SPI3) is mapped onto the same pins as the LCD interface. This enables interfacing to serial panel drivers that are compatible with the SPI protocol. For these cases, the AC timing information can be found in section 5.8 .

Table 73 LCD/SPI3 Mapping

Description LCD Function Name SPI3 Function Name

Chip Select LCD_CS0_N LCD_CS1_N

SPI3_CS2_N SPI3_CS3_N

Serial Clock LCDx_SCK SPI3_SCK

Serial Output Data LCDx_SDOUT SPI3_DOUT

Serial Input Data (optional) LCDx_SDIN SPI3_DIN



Pixel Data Transfers

For designs that require the pixel data transferred over the serial interface, the LCD serial interface controller is used. This is mapped to the same pins as described above, except the LCD controller is used instead of SPI3 and reads are not supported. The signals are referenced to the internal display clock rising edge. The AC timing shown in the diagram and table are referenced to the external LCDx_SCK (primary display) or LCDx_WR_N (Secondary display) which is ½ the frequency of the internal clock (the internal clock is shown for reference purposes). LCDx_SCK can be programmed to latch the commands and data on the rising or falling edge of the clock. The Serial I/F supports an internal display clock frequency up to 41.5MHz. This results in a maximum LCDx_SCK frequency of 20.75MHz.

Figure 10 CPU Style Serial Display Interface Timing Diagram

LCDx_SCK

LCDx_DC[1:0]

tODSU

tCSSU

LCDx_CS[1:0]_N

BIT 0 BIT 1 BIT 2 BIT nLCDx_SDOUT

tDCSU

tCL tCH tCP

tCSH

tDCH

tODH

Internal Display Clock

tP

tODH

Table 74 CPU Style Serial Display Interface Timing Parameters


tP Internal clock period 12 ns

tCP LCDx_SCK period 2 tP

LCDx_SCK frequency 41.5 MHz

LCDx_SCK duty cycle 40 60 %

tCH LCDx_SCK high time 9 ns

tCL LCDx_SCK low time 9 ns

tODSU LCDx_SDOUT output setup to 1st LCDx_SCK latching edge1 tP – 2 ns

tCSSU LCDx_CS[1:0]_N setup to 1st LCDx_SCK latching edge1 3tP – 2 ns

tDCSU LCDx_DC setup to LCDx_SCK latching edge1 3tP – 2 ns

tODH LCDx_SDOUT hold from LCDx_SCK latching edge1 tP – 2 ns

tCSH LCDx_CS[1:0]_N hold from last LCDx_SCK latching edge1 tP – 2 ns

tDCH LCDx_DC[1:0] hold from last LCDx_SCK latching edge1 5tP – 2 ns

tDSU LCDx_SDIN setup to LCDx_SCK latching edge1

tHU LCDx_SDIN hold from LCDx_SCK latching edge1

1. The example above assumes LCDx_SCK polarity is active high, the rising edge is the latching edge and a 1 clock CS option is enabled.



5.3 Video Input The Video Input (VI) is the center for all video input data processing. It receives video from several input units such as the 8-bit parallel CCIR 605/656 interface and CSI, and processes and directs that data to other functional units such as main memory, ISP, and display controller.

Data in various video and pixel formats can be received, processed (for example, cropped, downscaled, color-space converted, and format-converted), redirected to other functional units in the device, or stored to main memory.

5.3.1 Parallel Interface

Figure 11 VI Parallel Input Timing Diagram

Table 75 VI Parallel Clock Input Timing Parameters


tCP VI_PCLK period 8.33 ns

VI_PCLK frequency 120 MHz

VI_PCLK duty cycle 45 55 %

tCH VI_PCLK high time 3 ns

tCL VI_PCLK low time 3 ns

tRT VI_PCLK edge rise time 1 ns

tFT VI_PCLK edge fall time 1 ns

tDSU VI_D[11:0] setup time to VI_PCLK edge1 1 ns

tDH VI_D[11:0] hold time from VI_PCLK edge1 1 ns

tSSU VI_HSYNC, VI_VSYNC setup time to VI_PCLK edge1 1 ns

tSH VI_HSYNC, VI_VSYNC hold time from VI_PCLK edge1 1 ns

1. VI_PCLK latching edge can be programmed for rising or falling edge. Rising edge shown.



5.3.2 Reference Clock Output The Video Input (VI) interface supports a variety imaging peripherals such as cameras and video decoders. Many of these devices require a reference clock which the Tegra 200 series MWP can provide. This is the VI_MCLK pin which can output a clock up to 80MHz. The VI interface is capable of up to 95MHz operation, but many imagers have their own integrated PLLs and do not require the reference clock to run at the full frequency. For those that do not have PLLs and run beyond 80MHz, an external clock source may be required. VI_MCLK is located in the VI I/O block and is powered by the VDDIO_VI rail. The output drive strengths and slew rate are programmable.

Figure 12 VI_MCLK Output Timing Diagram

Table 76 VI_MCLK Output Timing Parameters


tCP

VI_MCLK period 12.5 ns

VI_MCLK frequency 80 MHz

VI_MCLK duty cycle 40 60 %

tCH VI_MCLK high time 5 ns

tCL VI_MCLK low time 5 ns

tRT VI_MCLK edge rise time 2 ns

tFT VI_MCLK edge fall time 2 ns



5.4 Audio The Tegra 200 series MWP has five Digital Audio Ports (DAP1, DAP2, DAP3, DAP4 and DAP5 – DAPx is used to represent any of the five). The following timing in the following sections applies to any of these DAP interfaces depending on whether they are configured for I2S/PCM or AC’97 mode.

5.4.1 I2S, PCM and TDM Timing The I2S and PCM (master and slave modes) interfaces support transfer rates of 2.5 MHz ± 10%.

Figure 13 Master Mode Timing Diagram

Figure 14 Slave Mode Timing Diagram

Table 77 I2S and PCM Timing Parameters


tCYL DAPx_SCLK cycle time 360 440 ns

tCH DAPx_SCLK high time 160 ns

tCL DAPx_SCLK low time 160 ns

tDLY DAPx_FS delay from DAPx_SCLK falling edge 300 ns

tDDLY DAPx_DOUT delay from DAPx_SCLK falling edge 300 ns

tDSU DAPx_DIN setup time to DAPx_ SCLK rising edge 60 ns

tDH DAPx_DIN hold time from DAPx_SCLK rising edge 0 ns

tFSU DAPx_FS setup to DAPx_SCLK rising edge 60 ns

tFH DAPx_FS hold from DAPx_SCLK rising edge 0 ns

tRT DAPx_SCLK rise time 60 ns

tFT DAPx_SCLK fall time 60 ns

Note: Above for transfer rate of 2.5MHz (+-10%)



5.4.2 AC97 Timing

Figure 15 AC’97 Timing Diagram

Table 78 AC’97 Timing Parameters


tCP DAPx_SCLK period 81.4 ns

DAPx_SCLK frequency 12.288 MHz

DAPx_SCLK output jitter 750 ps

DAPx_SCLK duty cycle 40 60 %

tCH DAPx_SCLK high time 32.5 49 ns

tCL DAPx_SCLK low time 32.5 49 ns

tSP DAPx_FS period 20.8 ns

DAPx_FS frequency 48 KHz

tSH DAPx_FS high time 1.3 us

tSL DAPx_FS low time 19.5 us

tDSU DAPx_DIN, DAPx_DOUT setup to DAPx_SCLK, falling edge 15 ns

tDH DAPx_DIN, DAPx_DOUT hold from DAPx_SCLK, falling edge 5 ns

tSSU DAPx_SYNC setup to DAPx_SCLK rising edge 15 ns

tSHLD DAPx_SYNC hold from DAPx_SCLK rising edge 5 ns

tRT DAPx_SCLK, DAPx_SYNC, DAPx_SDIN, DAPx_SDOUT rise times 21 6 ns

tFT DAPx_SCLK, DAPx_SYNC, DAPx_SDIN, DAPx_SDOUT fall times 21 6 ns

1. The Drive and Slew Rate for these can be adjusted using the Pad Configuration registers.



5.5 Memory Cards and SDIO Peripherals Timing The Tegra 200 series MWP integrates four controllers that can support an 8-bit High Speed MMC functionality.

5.5.1 HS-MMC Controller Controllers in the Tegra 200 series MWP support both the High-speed and Backward-compatible interface modes as well as cards designed for the High (2.7V-3.6V) and Mid (1.7V-1.95V) voltage ranges.

Figure 16 HSMMC Timing Diagram

Table 79 HSMMC High-Speed Timing Parameters


tCP HSMMC_CLK period 19.23 ns

HSMMC_CLK frequency 52 MHz

tCH HSMMC_CLK high time 8.5 10.5 ns

tCL HSMMC_CLK low time 8.5 10.5 ns

tISU HSMMC_CMD, HSMMC_DAT[7:0] input setup time 3 ns

tIH HSMMC_CMD, HSMMC_DAT[7:0] input hold time 3 ns

tODLY HSMMC_CMD, HSMMC_DAT[7:0] output delay time 14 ns

tOH HSMMC_CMD, HSMMC_DAT[7:0] output hold time 5 ns

tRT Output rise time 3 ns

tFT Output fall time 3 ns

Table 80 HSMMC Backward-Compatible Timing Parameters


tCP HSMMC_CLK period 38.46 ns

HSMMC_CLK frequency 26 MHz

tCH HSMMC_CLK high time 15 24 ns

tCL HSMMC_CLK low time 15 24 ns

tISU HSMMC_CMD, HSMMC_DAT[7:0] input setup time 3 ns

tIH HSMMC_CMD, HSMMC_DAT[7:0] input hold time 3 ns

tODLY HSMMC_CMD, HSMMC_DAT[7:0] output delay time 26 ns

tOH HSMMC_CMD, HSMMC_DAT[7:0] output hold time 9 ns





5.5.2 SDIO The Tegra 200 series MWP can support full SDIO functionality and an SD Memory card interface (HSMMC). These controllers can be routed to multiple physical locations on the device. The SD timing shown in this section applies to any of these configurations. The SD/SDIO controllers support Default and High Speed modes as well as the High and Low voltage ranges.

Figure 17 SDIO Timing Diagram

Table 81 SDIO Standard Mode Timing Parameters


tCP SDIOx_CLK period 40 ns

SDIOX_CLK frequency 25 MHz

tCH SDIOX_CLK high time 16 ns

tCL SDIOX_CLK low time 16 ns

tISU SDIOX_CMD, SDIOX_DAT input setup time 3 ns

tIH SDIOX_CMD, SDIOX_DAT input hold time 3 ns

tODLY SDIOX_CMD, SDIOX_DAT output delay time 27 ns



Table 82 SDIO High-Speed Mode Timing Parameters


tCP SDIOx_CLK period 20 ns

SDIOX_CLK frequency 50 MHz

tCH SDIOX_CLK high time 9 ns

tCL SDIOX_CLK low time 9 ns

tISU SDIOX_CMD, SDIOX_DAT input setup time 3 ns

tIH SDIOX_CMD, SDIOX_DAT input hold time 3 ns

tODLY SDIOX_CMD, SDIOX_DAT output delay time 14 ns

tOH SDIOX_CMD, SDIOX_DAT output hold time 5 ns





5.6 HSI HSI is a MIPI standard interface and one of the options on the Tegra 200 series MWP for interfacing to similarly equipped Baseband devices. These pins are powered by VDDIO_BB.

Figure 18 HSI Timing Diagram

Table 83 HSI Timing Parameters

Symbol Parameter Min Max Unit

tBT Nominal Bit time 101 ns

tES Edge Separation 5.5 ns

tSK Skew at the Tegra 200 series transmitter pins 0.5 ns

tRT Rise time 2 ns

tFT Fall time 2 ns

1. Nominal or typical value, not minimum spec.

2. HSI_READY & HSI_WAKE are asynchronous to HSI_DATA/ HSI_FLAG and inputs pass through an internal synchronizer and have no specific timing requirements but meet HSI protocol.



5.7 I2C Interface I2C controllers can be routed to multiple physical locations on the device. These timing specifications are for high-speed mode transfer rates of up to 400 KHz.

Figure 19 I2C Basic Clock & Data Timing Diagram

Table 84 I2C Basic Clock & Data Timing Parameters


tCYC PWR_I2C_SCL/I2Cx_SCL cycle time 2.5 us

tCH PWR_I2C_SCL/I2Cx_SCL high time 0.6 us

tCL PWR_I2C_SCL/I2Cx_SCL low time 0.6 us

tRT Rise time 300 ns

tFT Fall time 300 ns

tDSU PWR_I2C_SDA/I2Cx_SDA setup to PWR_I2C_SCL/I2Cx_SCL rising edge 100 ns

tDH PWR_I2C_SDA/I2Cx_SDA hold from PWR_I2C_SCL/I2Cx_SCL falling edge 0 0.9 us

Figure 20 I2C START, STOP Timing Diagram

Table 85 I2C START, STOP Timing Parameters


tRSSU Setup time for repeated START condition 0.6 us

tRSH Hold time for repeated START condition 0.6 us

tSPSU Setup time for STOP condition 0.6 us

tBFT Bus free time between STOP & Start condition 1.3 us



5.8 Serial Peripheral Interface (SPI) SPI controllers can be routed to multiple physical locations on the device.

Figure 21 SPI Master Timing Diagram

1. CSx_N can be driven by Software or Hardware. When driven by Hardware, the polarity is programmable. Active low Hardware driven CSx_N is shown in the diagrams

Table 86 SPI Master Timing Parameters


tCP SPIx_SCLK period 20 ns

SPIx_SCLK duty cycle 45 55 %

tCH SPIx_SCLK high time 9 ns

tCL SPIx_SCLK low time 9 ns

tDSU SPIx_MISO setup to SPIx_SCLK rising edge 3 ns

tDH SPIx_MISO hold from SPIx_SCLK rising edge 2 ns

tDD SPIx_MOSI delay from SPIx_SCLK falling edge 0.5 4 ns

tCSU SPIx_CSx_N setup time 0.5 tCP

tCSL SPIx_CSx_N low time tCSU + tCCS + n1 tCP

tCSH SPIx_CSx_N high time (INT_SIZE2 + 1) / 4 tCP

tCCS SPIx_SCLK rising edge to SPIx_CSx_N rising edge 1 tCP

1. n is the number of bits in the Bit Length of the transfer 2. INT_SIZE is the register bit field for selecting the idle time between transfers.

Note: Polarity of SCLK is programmable. Data can be driven or input relative to either the rising edge (shown above) or falling edge.

Note: SPIx_CSx_N can be driven by Software or Hardware. When driven by Hardware, the polarity is programmable. Active low Hardware driven. SPIx_CSx_N is shown in the diagrams.



Figure 22 SPI Slave Timing Diagram

Table 87 SPI Slave Timing Parameters


tSCP SPIx_SCLK period 2*(tSDD+ tMSU1) ns

tSCH SPIx_SCLK high time tSDD + tMSU1 ns

tSCL SPIx_SCLK low time tSDD + tMSU1 ns

tSCSU SPIx_CSx_n setup time 1 tSCP

tSCSH SPIx_CSx_n high time 1 tSCP

tSCCS SPIx_SCLK rising edge to SPIx_CSx_n rising edge 1 1 tSCP

tSDSU SPIx_DOUT setup to SPIx_SCLK rising edge 4 ns

tSDH SPIx_DOUT hold from SPIx_SCLK rising edge 2 ns

tSDD SPIx_DIN delay from SPIx_SCLK falling edge (Primary2) 2.5 11 ns

tSDD SPIx_DIN delay from SPIx_SCLK falling edge (ALT12) 3.5 16 ns

tSDD SPIx_DIN delay from SPIx_SCLK falling edge (ALT22) 3 13 ns

tSDD SPIx_DIN delay from SPIx_SCLK falling edge (ALT32) 4 17 ns

1. tMSU is the setup time required by the external master 2. Primary, ALT1/2/3 refers to the position of the SPI pins in the Signal Pinout Multiplexing tables in Section 3.1, Signal List and Multiplexing Functions.

Note: Polarity of SCLK is programmable. Data can be driven or input relative to either the rising edge (shown above) or falling edge.



5.9 JTAG The Tegra 200 series MWP has an optional JTAG interface that can be used either for SCAN testing, or for communicating with either integrated CPU.

Figure 23 JTAG Timing Diagram

Table 88 JTAG Timing Parameters


tCP JTAG_TCK period 100 ns

JTAG_TCK frequency 10 MHz

JTAG_TCK duty cycle 40 60

tCH JTAG_TCK high time 40 ns

tCL JTAG_TCK low time 40 ns

tDSU JTAG_TDI setup to JTAG_ TCK rising edge 0 ns

tDH JTAG_TDI hold from JTAG_TCK rising edge 12 ns

tODLY JTAG_TDO delay from JTAG_TCK falling edge 25 ns

tRT JTAG_TCK rise time 1 ns

tFT JTAG_TCK fall time 1 ns

Tegra 200 Series Mobile web Processor

6.0 Power Sequencing 6.1 Power-up Sequence The following rails must be powered-on prior to the rising edge of SYS_RESET_N

VDD_RTC

VDD_CORE

VDDIO_SYS

VDDIO_OSC

VDDIO_DDR

VDDIO_NAND

VDD_DDR_RX

AVDD_PLLM, AVDD_PLLA_P_C, AVDD_PLLU, AVDD_PLLX

Any of the “wide-range” digital I/O rails which will operate in the 2.8-3.3V range

Any rails necessary for communicating with the chosen boot device.

Additionally, both CLK_32K_IN and the reference clock on XTAL_OUT must be valid prior to the rising edge of SYS_RESET_N.

During Power-up, CORE_PWR_REQ and SYS_CLK_REQ are tri-stated. The PMU and reference clock sources must provide VDD_CORE and the reference clock during Power-up without requiring that these REQ signals be asserted. Later, the software will initialize the proper state for CORE_PWR_REQ, CPU_PWR_REQ, and SYS_CLK_REQ if these signals are needed to control core power, CPU power, and the reference clock.

Figure 24 shows the sequencing requirements for powering up the Tegra 200 series MWP.

Recommendations

NVIDIA recommends (but does not require) that VDD_CPU remain powered-off throughout the power-up sequence. The bootloader may enable VDD_CPU via CPU_PWR_REQ or another system-specific mechanism.

NVIDIA recommends (but does not require) that AVDD_USB remains powered down until 1ms after clocks are valid. This reduces the peak current consumption of AVDD_USB during power-up.

NVIDIA recommends (but does not require) that VDDIO_SYS is high before other 1.8V rails can start ramping. This reduces the possibility of a higher inrush current during power-up which could occur if VDDIO_SYS and other 1.8V rails ramp at same time.

NVIDIA recommends (but does not require) that VDDIO_DDR is powered prior to powering VDD_DDR_RX to avoid unnecessary leakage at power up.


Tegra 200 Series Mobile Web Processor Power Sequencing


Figure 24 Power-up Sequence Timing Diagram

Table 89 Power-up Sequence Timing Parameters


tCORE Delay from VDD_RTC active to VDD_CORE active 0 ms

tSYS Delay from VDD_CORE active to VDDIO_SYS active 1 ms

tVLOW Delay from VDDIO_SYS active to other 1.8V rails active 0 ms

tVHIGH Delay from VDDIO_SYS active to 2.8V-3.3V I/O rails active 1 ms

tSIG1 Delay from Voltage rail active to first rising edge on any I/O pin referenced to that rail 0

ms

tVPLL Delay from VDDIO_SYS active to AVDD_PLL rails active 0 ms

tCLKVUSB Delay from System clock and 32kHz clock valid to AVDD_USB active – ms

tCLKRST

Delay from:

- System clock valid

- 32kHz clock valid

- All power rails required for boot active to rising edge of SYS_RESET_N

1

ms

Tegra 200 Series Mobile Web Processor Power Sequencing


6.2 Deep Sleep Entry Sequence NOTE: This section will be updated in a later release.

6.3 Deep Sleep Exit Sequence NOTE: This section will be updated in a later release.

6.4 Power-down Sequence When completely powering down the the Tegra 200 series processor, it must be in the On (normal active) mode, not in Deep Sleep mode. The sequence should be as follows:

1. SYS_RESET_N is asserted

2. The higher voltage I/O rails (2.8V or higher) should be removed along with SYS_RESET_N or later

3. The lower voltage rails (1.8V, 1.1V, and 1.2V other than the cores) should be removed with or later than the higher voltage rails

4. VDD_RTC, VDD_CORE, VDD_CPU and any remaining 1.2V power rails are removed last.

Do not violate VM_PIN, the maximum voltage applied to any I/O pin, during the Power-down sequence.

The Power-down sequence is recommended. However, it is acceptable to have the power rails removed without the sequencing as long as the duration of any possible changes from the recommended sequence are short (< 10 ms). It is possible to have increased leakage while the different rails ramp down at different rates (the leakage will not cause damage). This case would be likely in the event the power source (battery, etc.) was disconnected suddenly.


7.0 Package Description This section details thermal specifications and package dimensions and for Tegra 200 series MWP packages.

RoHS Compliance

The Tegra 200 series MWP packages are RoHS compliant. All Tegra 200 series parts are lead free unless marked with "E" for Eutectic part number.

The Tegra 200 series product family meets the RoHS guidelines for electronic components, and hardware set forth in the European Union’s Directive 2002/95/EC of the European Parliament and the Council on the Restriction of Hazardous Substance (RoHS).

Storage and Handling

Refer to the packing label shipped with your order for specific storage, handling and expiration instructions.

Table 90 Typical Handling and Storage Environment Symbol Description Relative Humidity (RH) Minimum Temperature Maximum Temperature

TSTG Storage temperature (shelf life in sealed bag): 1 year Less than 90 % NA 40oC

TA Floor Life: JEDEC MSL 4 (up to 72 hours after breaking the vacuum seal on the bag containing the device)1

Less than 60% NA 30oC

1. Compliant with IPC/JEDEC Moisture Sensitivity Level J-STD-020 MSL 4.

7.1 Thermal Specification Table 91 provides package thermal characteristics under the following conditions:

0m/s air velocity surrounding the package

Ambient operating temperature: 70oC

No thermal underfill epoxy present

Table 91 Package Thermal Characteristics

Processor Package Thermal Design Power1 at TJ2 = 90oC RθJA

3

Tegra 250 664 Ball FCBGA, 23x23 mm, 0.8mm pitch 2.25W TBDoC/W

1. Thermal Design Power is the power dissipation for use in thermal design considering high-compute applications. Thermal Design Power is not the theoretical maximum power the device can generate.

2. TJ = Die Junction Temperature; TJ (max) = 90oC.

3. RθJA (Theta-JA) = Thermal Resistance Junction-to-Ambient, o C/W


Tegra 200 Series Mobile web Processor Package Description


7.2 Package Marking Complete product marking is done during assembly. All marking in each line is center justified within the marking area. All character font style is “Arial” or equivalent except in the company and logo area.

Figure 25 Marking Example

Character height tolerance = +/- 0.2 mm Dimension G = +/- 0.50 mm

Table 92 Product Part Numbers

Product Part Number (5th Line)

Tegra 250 T20-H-A2



7.3 Package Drawing & Dimensions

Figure 26 Package Drawing



Table 93 Package Drawing Dimensions and Notes

Symbol Dimension in mm

Min Nom Max

A 1.80 1.95 2.10

A1 0.33 0.40 0.46

A2 0.82 0.87 0.95

A5 – – –

A6 0.20 0.28 0.35

D/E 22.90 23.00 23.10

D1/E1 21.60 BASIC

Wx 3.00 BASIC

Wy 3.00 BASIC

U 3.00 BASIC

V 2.00 BASIC

e 0.80 BASIC

f 0.70 BASIC

gx 7.99 BASIC

gy 7.97 BASIC

b 0.40 0.50 0.60

aaa 0.15

ccc 0.20

ddd 0.20

dee 0.15

fff 0.08

Number of Balls 664

NOTES

1. Controlling Dimension: Millimeter.

2. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.

3. Dimension b is measured at the maximum solder ball diameter, parallel to primary datum C.

4. The pattern of pin 1 fiducial is for reference only.

5. Drawing not to scale.

6. All passive locations shown, some or all locations may not be populated.

7. Compliant to JEDEC publication 95, page 4.5-1/E to 4.5-19/E.

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Macrovision Compliance Statement

NVIDIA Products that are Macrovision enabled can only be sold or distributed to buyers with a valid and existing authorization from Macrovision to purchase and incorporate the device into buyer’s products.

Macrovision copy protection technology is protected by U.S. patent numbers 5,583,936; 6,516,132; 6,836,549; and 7,050,698 and other intellectual property rights. The use of Macrovision’s copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited

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