model pcb thermals with greater accuracy

8/14/2019 Model PCB Thermals With Greater Accuracy

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Power Electronics Technology February 2008 www.powerelectronics.com22

Model PCB Thermals

with Greater AccuracyBy Byron Blackmore, Electronics Cooling EngineeringSupervisor, Flomerics, Marlborough, Mass.

Electronics companies at the leading edge o per-ormance are being orced to address board-levelthermal requirements at the earliest stages odesign. Printed circuit boards (PCBs) constitutethe primary area where mechanical engineers

can inuence the thermal design at the conceptual designphase. So, the ability to accurately predict the thermalperormance o the PCB early in the development processis becoming more critical than ever beore.

A key limitation o tools designed to simulate the per-ormance o PCBs early in the design process has beentheir inability to take into account the eects on thermalconductivity o localized concentrations o copper. But arecent improvement in these design tools gives designersthe ability to model the eects o copper concentration onthermal conductivity in board-level thermal simulations.

Te latest generation o PCB design tools makes it pos-sible to model copper concentration at whatever level o de-tail is desired, even to the point o modeling each individualtrace. Tis approach has been demonstrated to substantiallyimprove the accuracy o upront PCB thermal simulation. In

turn, this greater accuracy can help improve time to market,and reduce engineering and manuacturing costs.

Increasing Importance of Board DesignIn the airly recent past, board-level thermal simulation

was not considered to be a critical part o the mechanicaldesign ow. Power-dissipation levels were low, and as longas temperature and airow guidelines were met, thermalissues were usually relatively easy to resolve.

In this scenario, the task o the mechanical engineer wassimple: ensure that the chassis housed each PCB withinsucient airow at the right temperature. Termal man-agement was usually addressed at the time the chassis wasdesigned, normally by adding ans and cooling vents.

Te thermal design was typically based on a system-levelsimulation. Te chassis designed by this method normallyhad a relatively long shel lie, typically three to ve years.Once the thermal solution was xed, it was expected tolast through several generations o boards. Te mechanical

By vg PCB lye y mll cell clclg he heml ccvy ech cell, heml ml l geee me cce heml pfle cc lcl cce cppe he b.

Fig. 2. Simulation o board temperatures with the smeared

copper approach yields a microprocessor junction temperature

o 55.4C above ambient.

Fig. 1. With the smeared copper approach to thermal modeling, the

simulation tool calculates an average value or thermal conductivity

in a local area such as that surrounding the microprocessor.

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PrintEd CirCuit Boards

and PCB design processes were largely decoupled, enablingmechanical and PCB designers to work independently.

As Moores Law marched on, mechanical and PCBdesigners ound themselves having to interact morerequently. Tis was driven by the act that PCB power

dissipation or many designs was crossing an importantthreshold beyond which thermal compliance came intoquestion. Tis threshold is linked to the ability o the PCBitsel to act as a heatsink.

As a large at surace, the PCB is very eective in transer-ring heat rom components to the air. However, like any heat-

sink, a limit exists. A common rule o thumb to describe thelimit comes rom a simple heat-transer calculation, whichis an expression o the heatsinking ability o a PCB.

Given that 100C is a common maximum temperatureo components, the power that a PCB can dissipate is

estimated to be:Q = h3 SA3 (1 2),

where Q is power dissipation expressed in watts (W),h is the heat-transer coecient expressed as W/(C3 in2),SA is the surace area expressed as in2, 1 is the maximumcomponent temperature in C and 2 is the air tempera-

ture in C.he heat-transer coeicient is

largely dependant on the airlowspeed, although there is no simpleequation to describe the relationshipbetween these two variables. Te re-lationship between heat-transer co-

ecient and airow speed can varydepending on ow regime (laminar,transitional or turbulent) and the ge-ometry o the heat-dissipating object(at plate, cylinder, etc.). For a PCBsitting in airow at 20C and 200linear f/min, the maximum powerdissipation is 1.8 W/in2.

Simulation Process FlowElectronic manuacturers are be-

ginning to address these problems bypaying more attention to thermal de-sign at the board level. Ofen, whendesigning a new board or an existingenclosure, electrical engineers aresimulating the board alone to iden-tiy hot spots. Problems identiedat this stage ofen can be addressedby layout changes that can be madenearly without cost at this stage othe process. Board-level simulationtools are usually much easier orelectronic engineers to use, becausethey are designed around tools they

already use, such as unctional blockdiagrams and physical layouts.In a typical board-level thermal

simulation process ow, the systemsarchitect will develop the initial con-cept design by creating a unctionalblock diagram. Te hardware designengineer then drives the rst physi-cal layout directly rom the blockdiagram.

At an early stage in the designprocess, long beore the mechanicalengineer gets involved, the electrical

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www.powerelectronics.com Power Electronics Technology February 20082525

engineer can use board-level simulation to evaluate the newboard design in an existing system. A 3-D computationaluid dynamics (CFD) solver predicts airow and tempera-ture or both sides o the board.

Ofen the designer will identiy hot spots, and thus,

cooling management can be considered rom the earlieststages o the design process. Changes made to the unctionalblock diagram are reected instantly in the physical layoutand thermal representations.

Local Copper ConcentrationAs the importance o board-level

design rises, the accuracy o the ther-mal simulation results becomes morecritical. he thermal conductivityo the board itsel has an importantimpact on simulation results in manydesigns. PCB thermal conductivity is

particularly important in applicationswhere conduction is the primarymechanism o thermal management.Local thermal conductivity can be-come critical in many applications be-cause o the large dierence betweenthe thermal conductivity o copperand the dielectric material.

Te traditional smeared approachdetermines how much copper is oneach layer o the board and then cal-culates the average thermal conduc-tivity or that layer by averaging thethermal properties o the copper anddielectric material. Te problem withthis approach is that it does not takeinto account the local thermal con-ductivities, which can have a majorimpact on the thermal perormanceo the board.

For example, consider the case o aboard with a regulator that dissipatesthe vast majority o power. What mat-ters most rom a thermal perormancestandpoint is the thermal resistance o

the primary conduction path betweenthe component and the chassis. Temost power-consuming componentsusually have a large number o tracesrunning to them so the copper con-centration and thermal conductivityin their vicinity is considerably higherthan the average or the board.

Te thermal resistance o the pri-mary conduction path seen by thishigh-power-dissipation componentis usually much lower than the aver-age or the board. Te result is that

Fig. 3. The area surrounding the processor is modeled as 144-cell

array such that an average conductivity value is calculated or

each cell or patch.


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the traditional smeared approach typically shows junctiontemperatures higher than they actually are. ime and moneymay be wasted solving problems that either are less seriousthan they appear to be or do not exist at all.

Developers o PCB thermal simulation sofware are ad-dressing this challenge by providing the ability to divideeach layer o copper and dielectric material into arrays opatches o variable sizes with the thermal conductivity beingseparately dened or each patch.

Te ability to determine the size o patches used tosubdivide the layer is important because increasing thenumber o patches can substantially increase the amounto time required to simulate the thermal perormance othe design. Users need the ability to trade o simulationaccuracy against solution time.

ypically, in the early stages o the design process, de-signers will use larger patches to quickly evaluate a largenumber o design alternatives. Once they have identied aew promising designs, the patch size will typically be de-creased to determine the thermal perormance with a higherlevel o certainty. Users also have the ability to reduce the

patch size in areas that are more critical to thermal manage-ment, such as the area surrounding high-power-dissipationcomponents.

Simulation ExampleTe ollowing example shows how the ability to model

local copper concentration can improve the accuracy o PCBdesign simulation. Te example is based on a airly simpleboard, with 30 components, that operates in a conduction-cooled environment. Te heat is conducted through wedge-locks that provide a thermal and mechanical connectionrom the PCB to the chassis.

his system is designed or most o the heat to be

conducted through the board into the chassis, although araction o the heat will naturally be conducted into the air.In this example, the majority o the power in the board isdissipated by a microprocessor with 80 leads and a land. Teprimary heat conduction path runs between the land and

the leads. Although this example uses a microprocessor, thetechniques employed to simulate the processors thermalperormance can be applied to any power transistor, IC,module or other power device.

In this example, we begin by exporting the board layoutrom the Allegro PCB design system into Flomerics FLO/PCB sofware. A special menu called Flow EDA is installedin Allegro. We use this menu to gather inormation romthe board, including the location, size and orientation ocomponents, and layer inormation. Next, we export thebit-map images that Allegro generates or each layer (withthe copper appearing as black and the dielectric material aswhite) into the simulation sofware. In this simulation, weassume a 45C ambient temperature.

In the rst simulation, we employ the smeared copperapproach, which averages out the thermal conductivity overa broad area. Fig. 1 shows the local area o interest aroundthe microprocessor, while Fig. 2 shows the results o thissimulation.

With this approach, we divide the board into two localareas, one incorporating the processor and a band sur-rounding the processor (the highlighted area in Fig. 1), andanother comprising the rest o the board. Te PCB thermalsimulation sofware then calculates the amount o copperand dielectric in each local area and an average value or

thermal conductivity in each area.Te smeared approach assumes that the thermal conduc-tivity o the entire area around the component is uniormand consists o this average value. Tis approach yields a

junction temperature o 55.4C above ambient.Next, speciy a 12 3 12 array in the area around the

microprocessor. A dialog box appears with the image thathas been captured. With that image you can use the sliderbars to control the number o elements on each side. Tesimulation sofware then calculates the average thermalconductivity in each o the 144 patches dened by the ar-ray based on the images o the board traces provided by thePCB design sofware.

Fig. 4. When the local area around the processor is modeled

as an array, the thermal profle reveals a maximum junction

temperature o 50.2C above ambient or the die.

Fig. 5. In the most detailed model o the area surrounding the

processor, the tool assigns a thermal conductivity value to each

trace.

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Te array more realistically depicts the location o thecopper traces and so more accurately models the ow o heataway rom the processor as shown in Figs. 3 and4. Te array

approach shows a reduction in the junction temperature othe processor to 50.2C above ambient.

Finally you can model the array around the processorin its ull detail. Assign the surace area covered by eachtrace with the thermal conductivity o copper and assign

the thermal conductivity o the dielectric material to therest o the area (Fig. 5). Tis detailed approach provides thehighest level o accuracy that can be achieved in modelingheat conduction around the processor.

In this case, it shows an increase in junction temperatureo 45C above ambient (Fig. 6). Assuming that the result othis iteration provides perect accuracy, the copper-patchesapproach provided an error o 6.76% while the traditionalsmeared copper approach provided an error o 17.82%.

Higher ResolutionTe act that junction temperature continually ell as the

accuracy o the model increased can be explained by the act

that increasing the resolution o the model provided a moreconcentrated and ecient heat-conduction path. Accuracynaturally increases as the size o the patches is reduced.

In this application, the primary heat-conduction pathis between the lead and lands, and there is a 0.6-mm gapbetween the lead and lands. As the size o the patches ap-proaches 0.6 mm, the accuracy o the results can be expectedto improve substantially. PETech


Fig. 6.A temperature profle based on the detailed model in Fig. 5

indicates the lowest processor junction temperature o all the

simulations 45C above ambient.

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model pcb thermals with greater accuracy

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