modeling and simulation lab

Department of ECE Modeling and Simulation Lab Record

MODELING AND SIMULATION LAB

SYLLABUS

LIST OF EXPERIMENTS:

1. FPGA Implementation of Simple Alarm System

2. FPGA Implementation of Parity Checker

3. FPGA Implementation of Scrolling Display

4. FPGA Implementation of Multimode Calculator

5. FPGA Implementation of Multimode Calculators

6. Modeling and Prototyping with Simulink and Code Composer Studio with DSK

7. Graphical Simulation and Modeling using MATLAB

8. Simulation of Delta Modulation, Adaptive Delta Modulation and QPSK Constellation

1Vidyaa Vikas College of Engineering and Technology


Exp.No: ________ Date: __________________

1. A) FPGA IMPLEMENTATION OF SIMPLE ALARM SYSTEM

AIM:

To design and implement Simple Alarm System using FPGA

TOOLS REQUIRED:

Simulation : ModelSim

Synthesis : Xilinx 9.2i

SIMULATION PROCEDURE:

1. To start the programs click the modelsim software.

2. The main page is opened, click the file option to create a new source in VHDL.

3. After the program is typed, it is saved in a name with extension’ .vhd’

4. Then the program is compiled and errors are checked.

5. After that it is simulated.

6. Then the program is viewed and the signal option is clicked from the view menu and

input signals are given.

7. Then in the edit option, force is selected and the values are given.

8. Finally Add – wave is clicked view the result waveform.

SYNTHESIS PROCEDURE:

1. In the Xilinx, open a new project and give the file name.

2. Select VHDL module from XC3S400-4pq208.

3. Type the program and create new source.

4. Select implementation constraint file and give the file name.

5. Then click assign package pin (run) from user constraints.

6. Give the pin location and save the file.

7. Run the synthesis XST, implement design and generate program file sequentially.

8. Select program and wait until it gets succeed.


Department of ECE Modeling and Simulation Lab Record9. Give the input and observe the output in the Xilinx kit.



PROGRAM:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alarm is

PORT (clk, rst, remote, sensors: IN STD_LOGIC;

siren: OUT STD_LOGIC);

end alarm;

architecture Behavioral of alarm is

TYPE alarm_state is (disarmed, armed, intrusion);

ATTRIBUTE enum_encoding: STRING;

ATTRIBUTE enum_encoding OF alarm_state: TYPE IS "sequential";

SIGNAL pr_state, nx_state: alarm_state;

SIGNAL flag: STD_LOGIC;

begin

----- Flag: -----------------------------

PROCESS (remote, rst)

BEGIN

IF (rst='1') THEN

flag <= '0';

ELSIF (remote'EVENT AND remote='0') THEN

flag <= NOT flag;

END IF;

END PROCESS;

----- Lower section: --------------------

PROCESS (clk, rst)

BEGIN

IF (rst='1') THEN

pr_state <= disarmed;

ELSIF (clk'EVENT AND clk='1') THEN



pr_state <= nx_state;

END IF;

END PROCESS;

----- Upper section: -------------------

PROCESS (pr_state, flag, remote, sensors)

BEGIN

CASE pr_state IS

WHEN disarmed =>

siren <= '0';

IF (remote='1' AND flag='0') THEN

nx_state <= armed;

ELSE

nx_state <= disarmed;

END IF;

WHEN armed =>

siren <= '0';

IF (sensors='1') THEN

nx_state <= intrusion;

ELSIF (remote='1' AND flag='1') THEN


ELSE

nx_state <= armed;

END IF;

WHEN intrusion =>

siren <= '1';

IF (remote='1' AND flag='1') THEN


ELSE

nx_state <= intrusion;

END IF;

END CASE;



END PROCESS;

END Behavioral;

RESULT:

Thus the “Simple Alarm System” was implemented in Spartan-3 Trainer and its working is

demonstrated on interfacing board.



Exp.No: ________ Date: __________________

1. B) FPGA IMPLEMENTATION OF PARITY CHECKER

AIM:

To design and implement parity checker using FPGA

TOOLS REQUIRED:





2. The main page is opened, click the file option to create a new source in VHDL.













5. Then click assign package pin(run) from user constraints.




9. Give the input and observe the output in the Xilinx kit.



PROGRAM:

library ieee;

use ieee.std_logic_1164.all;

entity parity is

port(x,y,z,p:in std_logic;

c:out std_logic);

end parity;

architecture tms of parity is

begin

process(x,y,z,p)

begin

if(x='0' and y='0' and z='0' and p='0')then

c<='0';

elsif(x='0' and y='0' and z='0' and p='1')then

c<='1';


c<='1';


c<='0';


c<='1';


c<='0';


c<='0';


c<='1';


c<='1';




c<='0';


c<='0';


c<='1';


c<='0';


c<='1';


c<='1';


c<='0';

else

c<='x';

end if;

end process;

end tms;


Department of ECE Modeling and Simulation Lab Record3 BIT EVEN PARITY GENERATOR:

TRUTH TABLE:

4 BIT EVEN PARITY CHECKER:

TRUTH TABLE:

Four bits Received Parity Error CheckX Y Z P C0 0 0 0 00 0 0 1 10 0 1 0 10 0 1 1 00 1 0 0 10 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 11 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 01 1 0 1 11 1 1 0 11 1 1 1 0


Three bit message Parity bit

X Y Z P

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1


RESULT:

Thus the “parity checker” was implemented in Spartan-3 Trainer and its working is




Exp.No: ________ Date: __________________

1. C) FPGA IMPLEMENTATION OF SCROLLING DISPLAY

AIM:

To design and implement Scrolling display using FPGA

TOOLS REQUIRED:





2. The main page is opened; click the file option to create a new source in VHDL.













5. Then click assign package pin(run) from user constraints.





Department of ECE Modeling and Simulation Lab Record9. Give the input and observe the output in the Xilinx kit.



PROGRAM:

library ieee;


entity led is

port(h,i,j,k:in std_logic;

a,b,c,d,e,f,g:out std_logic);

end led;

architecture display of led is

begin

process(h,i,j,k)

begin

if(h='0' and i='0' and j='0' and k='0')then

a<='1';

b<='1';

c<='1';

d<='1';

e<='1';

f<='1';

g<='0';

elsif(h='0' and i='0' and j='0' and k='1')then

a<='0';

b<='1';

c<='1';

d<='0';

e<='0';

f<='0';

g<='0';


a<='1';

b<='1';

c<='0';



d<='1';

e<='1';

f<='0';

g<='1';


a<='1';

b<='1';

c<='0';

d<='1';

e<='1';

f<='0';

g<='0';


a<='0';

b<='1';

c<='1';

d<='1';

e<='0';

f<='1';

g<='1';


a<='1';

b<='0';

c<='1';

d<='1';

e<='0';

f<='1';

g<='1';


a<='1';

b<='0';


Department of ECE Modeling and Simulation Lab Recordc<='1';

d<='1';

e<='1';

f<='1';

g<='0';


a<='1';

b<='1';

c<='1';

d<='0';

e<='0';

f<='1';

g<='0';


a<='1';

b<='1';

c<='1';

d<='1';

e<='1';

f<='1';

g<='1';


a<='1';

b<='1';

c<='1';

d<='1';

e<='0';

f<='1';

g<='1';

end if;

end process;

end display;



TRUTH TABLE:

Number

to be

display

inputs outputs

h i j k a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

1 0 0 0 1 0 1 1 0 0 0 0

2 0 0 1 0 1 1 0 1 1 0 1

3 0 0 1 1 1 1 0 1 1 0 0

4 0 1 0 0 0 1 1 1 0 1 1

5 0 1 0 1 1 0 1 1 0 1 1

6 0 1 1 0 1 0 1 1 1 1 1

7 0 1 1 1 1 1 1 0 0 1 0

8 1 0 0 0 1 1 1 1 1 1 1

9 1 0 0 1 1 1 1 1 0 1 1



RESULT:

Thus the “Scrolling display” was implemented in Spartan-3 Trainer and its working is




Exp.No: ________ Date: __________________

1. D) FPGA IMPLEMENTATION OF MULTIMODE CALCULATORS

AIM:

To design and implement multimode calculator using FPGA

APPARATUS REQUIRED:





2. The main page is opened; click the file option to create a new source in VHDL.













5. Then click assign package pin (run) from user constraints.




9. Give the input and observe the output in the Xilinx kit.



PROGRAM:

library ieee;


use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity cal is

port (a, b: in std_logic_vector (7 downto 0);

sel: in std_logic_vector (3 downto 0);

result: out std_logic_vector (7 downto 0);

mulresult: out std_logic_vector (15 downto 0));

end cal;

architecture Behavioral of cal is

begin

process (a, b, sel)

begin

case sel is

when"0000"=>result<=a+b;

when"0001"=>result<=a-b;

when "0010"=>mulresult<=a*b;

when"0100"=>result<=a and b;

when"0101"=>result<=a or b;

when"0110"=>result<=a xor b;

when"0111"=>result<=a nor b;

when"1000"=>result<=a nand b;

when"1001"=>result<=a+1;

when"1010"=>result<=a-1;

when"1011"=>result<=b+1;

when"1100"=>result<=b-1;

when"1101"=>result<=not a;

when"1110"=>result<=not b;



OUTPUT:



when others =>result<="00000000";

end case;

end process;

end Behavioral;

RESULT:

Thus the “multimode calculator” was implemented in Spartan-3 Trainer and its

working is demonstrated on interfacing board.



Exp.No: ________ Date: __________________

2. PCB DESIGN USING CAD

AIM:

To design and implement 3 to 8 decoder SPICE

TOOLS REQUIRED:

1. Orcad 9.1

2. Desktop computer

PROCEDURE:

Simulation:

1. Open Orcad release and open new project.

2. Create a new folder at a particular path and select analog and mixed circuit wizard

option.

3. Select components from PSPICE library.

4. Place components in appropriate locations on schematic page, then make routing

between the components.

5. Save the content and create netlist.

6. Open new simulation option in the PSICE tool and give run time details.

7. Place the markers and run the PSPICE model.

8. End of the process.

Layout:

1. Select the *.dsn file in the left panel

2. Select the create net list menu in the tools menu bar

3. Select layout tag (PCB Foot print)

4. Browse the location to save the *.mnl file then click OK

5. Open the layout application

6. Click new menu in file menu bar



3 TO 8 DECODER:

V

0

V

B

D 0

1

0

U 2 C

7 4 L S 1 1

981 0

1 1

U 4 B

7 4 L S 1 1

364

5

D 3

V

D 6

0

D 7

U 1 B

7 4 L S 0 4

3 4

0

V

SD S TM 3

I N 2

U 3 A

7 4 L S 1 1

11 22

1 3

0

0

C

1

V

U 1 C

7 4 L S 0 4

5 6

D 2

A

D 4

V

U 2 B

7 4 L S 1 1

364

5

V

U 3 B

7 4 L S 1 1

364

5

1

U 1 A

7 4 L S 0 4

1 2

D 5

V

0

0

SD S TM 2

I N 1

D 1

1

0

V

U 3 C

7 4 L S 1 1

981 0

1 1

U 2 A

7 4 L S 1 1

11 22

1 3

SD S TM 1

I N 0

0

V

V

U 4 A

7 4 L S 1 1

11 22

1 3

OUTPUT:



7. Load the template file (default.tch) in the working directory(C:\Program files\orcad\

layout\data\default.tch) then click open

8. Load the text list source file where you have stored *.mnl file then click open

9. Save the board file *.max

10. Rearrange the components as you like

11. Select the obstacle tool from the tool bar

12. Draw space to cover all the footprints.

13. Go to auto menu-choose place board then click auto route board

RESULT:

Thus the given digital circuits were designed and layout was drawn using PSPICE



Exp.No: ________ Date: __________________

3. MODELING AND PROTOTYPING WITH SIMULINK AND CODE COMPOSER STUDIO WITH

DSK

AIM:

To model and prototype the conversion of basic waveforms using differentiator and

integrator in Simulink and to implement the basic examples in DSK Kit using Code composer

studio

APPARATUS REQUIRED:

SOFTWARES:

1. MATLAB 7.5

2. CODE COMPOSER STUDIO

HARDWARE:

1. DSK KIT (TMS 320 C 6711 Or TMS 320 C 6713 )

MODELING AND PROTOTYPING WITH SIMULINK

GENERAL PROCEDURE:

Step 1: Start MATLAB

Step 2: Click simulink icon in the MATLAB Command Window

Step 3: Create a new model - Select File > New > Model in the Simulink Library Browser

Step 4: From the Simulink Library Browser click simulink. Select the sources required and

track it to the new file created. Join all the blocks.

Step 5: Click Start simulation icon in the created new file and double click the scope



Step 6: Display Screen “Scope” will be opened and the respective output can be viewed.

Step 7: Errors and warnings will be displayed in the Mat lab Command Window.

A.Conversion of Basic waveforms using differentiator and integrator

PROCEDURE:

a.Conversion of Basic waveforms using differentiator


Step 2: Click simulink icon in the MAT LAB Command Window.

Step 3: Create a new model - Select File > New > Model in the Simulink Library

Browser.

Step 4: From the Simulink Library Browser click simulink. Click “Sources” under

simulink. Select “Sine waveform” and track it to the new file created. Click

“Continuous” under simulink.. Select “derivative dw /dt” and track it to the

new file created. Click “Sources” under Simulink. Select “Scope” and track it

to the new file created.

Step 5: Connect the blocks.


Step 7: Display Screen “Scope” will be opened and the output Cosine waveform is

viewed.

A. Conversion of Basic waveforms using Integrator


Step 2: Click simulink icon in the MATLAB Command Window

Step 3: Create a new model - Select File > New > Model in the Simulink Library

Browser.



OUTPUT:

CONVERSION OF SINE WAVE INTO COSINE WAVEFORM USING DIFFERENTIATOR

OUTPUT DISPLAY

CONVERSION OF SQUARE WAVEFORM INTO SPIKES USING DIFFERENTIATOR:

OUTPUT DISPLAY:



Step 4: From the Simulink Library Browser click simulink. Click “Sources” under

simulink. Select “Square generator” and track it to the new file created. Click

“Continuous” under simulink.elect “Integrator 1/s” and track it to the new file

created. Click “Sources” under Simulink. Select “Scope” and track it to the

new file created.

Step 5: Connect the blocks.


Step 7: Display Screen “Scope” will be opened and the output “Triangular” waveform

is viewed.

THEORY:

Simulink is a software package which enables to model, simulate and analyze

the systems whose outputs change over time. These systems are referred to as

dynamic systems. It is also used to explore the behavior of a wide range of real-world

dynamic systems such as electrical circuits, shock absorbers, braking systems and

many other electrical, mechanical, and thermodynamic systems.

CODE COMPOSER STUDIO WITH DSK KIT

PROCEDURE:

Step 1: Connect adapter and power supply card to the System.

Step 2: Code composer studio software to be opened.

Step 3: In the screen, click the icon “PROJECT” and select “open”. Select “C “Drive.

Step 4: Enter into TI Folder. Click “Examples” and enter into “dsk6711”.

Step 5: In “dsk6711” folder select the “Bios” file. Click “Swill test”. Select

“Swiltest.pjt”.

“Swiltest.C “Screen will be opened.

Step 6: Goto “PROJECT” select “Rebuild all”. “Swiltest.C” program will be compiled



CONVERSION OF SINE WAVE INTO COSINE WAVEFORM USING INTEGRATOR:

OUTPUT DISPLAY:

CONVERSION OF SQUARE WAVE INTO TRIANGULAR WAVE USING INTEGRATOR:

OUTPUT DISPLAY



Step 7: Goto “FILE” select “Load Program”. The output file is viewed as

“Swiltest.out”.

Step 8: Goto “DEBUG” icon select “Run”

RESULT:

Thus the conversion of basic waveforms using differentiator and integrator is

modeled using Simulink.



Exp.No: ________ Date: __________________

4 GRAPHICAL SIMULATIONS AND MODELLING OF AN IMAGE USING MATLAB

AIM:

To perform modeling of an image and simulate it using MATLAB

TOOLS REQUIRED:

MATLAB 7 or Higher Version

PROGRAM:

RGB to Gray scale conversion of Image

clc;

clear all;

close all;

a=imread('C:\Documents and Settings\All Users\Documents\My Pictures\Sample Pictures\

Water lilies.jpg')

b=rgb2gray(a)

subplot(1,2,1)

imshow(a),title('original image')

subplot(1,2,2)

imshow(b),title(‘Grayscaleimage):



OUTPUT:

RGB TO Gray scale Conversion of image



Un sharp Image

clc;

clear all;

close all;

a=imread('C:\Documents and Settings\All Users\Documents\My Pictures\Sample Pictures\

Water lilies.jpg')

h=fspecial(‘unsharp’);

b=imfilter(a,h);

subplot(1,2,1)

imshow(a),title('original image')

subplot(1,2,2)

imshow(b),title(‘Un sharp mask’):

PROCEDURE:

1. Open a MATLAB new file and enter the corresponding coding for the RGB to Gray scale conversion and un sharp Image.

2. Save and run the mat lab file.

3. Obtain the corresponding output for image modeling

RESULT:

An image has been modeled and simulated using MATLAB



OUTPUT:

Un sharp Image



Exp.No: ________ Date: __________________

5 (A &B) DELTA MODULATION AND ADAPTIVE DELTA MODULATION

AIM:

To simulate the delta and Adaptive delta modulation using MAT LAB

TOOLS REQUIRED:

Simulation : MATLAB 7.0 or higher version

ALGORITHM:

Step: 1: Start the program

Step: 2: Get the length of the sinusoidal signal

Step: 3: Compute the step size

Step: 4: Plot the output sequence

Step: 5: Terminate the process

PROGRAM:

DELTA MODULATION:

% function to generate Linear Delta Modulation for sin wave % generating sin wave t=[0:2*pi/100:2*pi]; a=10*sin(t); n=length(a); dels=1; xhat(1:n)=0; x(1:n)=a;



OUTPUT:

0 10 20 30 40 50 60 70 80 90 100-20

-15

-10

-5

0

5

10

15

20



d(1:n)=0; % Linear Delta Modulation

for k=1: n

if (x(k)-xhat(k)) > 0

d(k)=1;

else d(k)=-1;

end %if xtilde(k)=xhat(k)+d(k)*dels; xhat(k+1)=xtilde(k); end %k %Prints figure(1); hold on; plot(a) plot(xhat); plot(d-15); axis([0 100 -20 20])

PROGRAM:

ADAPTIVE DELTA MODULATION:

% adaptive delta modulation for sin wave % generating sin wave t=[0:2*pi/100:2*pi]; a=10*sin(t); n=length(a); mindels=1;



dels(1:n)=mindels; xhat(1:n)=0; x(1:n)=a; % Adaptive Delta Modulation

d(1:n)=1; for k=2:n if ((x(k)-xhat(k-1)) > 0 )d(k)=1; else d(k)=-1; end %if if k==2 xhat(k)=d(k)*mindels+xhat(k-1); end if ((xhat(k)-xhat(k-1)) > 0) if (d(k-1) == -1 &d(k) ==1) xhat(k+1)=xhat(k)+0.5*(xhat(k)-xhat(k-1)); elseif (d(k-1) == 1 &d(k) ==1) xhat(k+1)=xhat(k)+1.15*(xhat(k)-xhat(k-1)); elseif (d(k-1) == 1 &d(k) ==-1) xhat(k+1)=xhat(k)-0.5*(xhat(k)-xhat(k-1)); elseif (d(k-1) == -1 &d(k) ==-1) xhat(k+1)=xhat(k)-1.15*(xhat(k)-xhat(k-1)); end



OUTPUT:

0 20 40 60 80 100 120-20

-15

-10

-5

0

5

10

15



else if (d(k-1) == -1 &d(k) ==1) xhat(k+1)=xhat(k)-0.5*(xhat(k)-xhat(k-1)); elseif (d(k-1) == 1 &d(k) ==1) xhat(k+1)=xhat(k)-1.15*(xhat(k)-xhat(k-1)); elseif (d(k-1) == 1 &d(k) ==-1) xhat(k+1)=xhat(k)+0.5*(xhat(k)-xhat(k-1)); elseif (d(k-1) == -1 &d(k) ==-1) xhat(k+1)=xhat(k)+1.15*(xhat(k)-xhat(k-1)); endend %Plots figure(1);hold on; plot(a); plot(xhat); plot(d-15)

RESULT:


Department of ECE Modeling and Simulation Lab RecordThus the Mat lab program was simulated for delta and adaptive modulation the

waveforms are plotted.



Exp.No: ________ Date: __________________

5(C) QPSK CONSTELLATION

AIM:

To simulate the QPSK transmitter and receiver circuit and to obtain the constellation

using MAT LAB

TOOLS REQUIRED:

MATLAB 7.0

PROCEDURE:

4. Open a MATLAB new file and enter the corresponding coding for the QPSK transmitter and receiver.

5. Save and run the mat lab file.

6. Obtain the corresponding output for QPSK constellation, BER for QPSK

PROGARM:

%%%%%%%%%%%%PROGRAM FOR QPSK CONSTELLATION %%%%%%%%%

nSamp = 8; numSymb = 100;

M = 4; SNR = 14;

seed = [12345 54321];

rand('state', seed(1)); randn('state', seed(2));

numPlot = 10;

rand('state', seed(1));

msg_orig = randsrc(numSymb, 1, 0:M-1);

stem(0:numPlot-1, msg_orig(1:numPlot), 'bx');

xlabel('Time'); ylabel('Amplitude');

grayencod = bitxor(0:M-1, floor((0:M-1)/2));

msg_gr_orig = grayencod(msg_orig+1);

msg_tx = modulate(modem.pskmod(M), msg_gr_orig);



OUTPUT:

-1.5 -1 -0.5 0 0.5 1 1.5-1.5

-1

-0.5

0

0.5

1

1.5

Quadrature

In-Phase

Scatter plot

-1 -0.5 0 0.5 1

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Quadra

ture

In-Phase

Scatter plot

0 1 2 3 4 5 6 7 8 90

0.5

1

1.5

2

2.5

3

Time

Am

plit

ude



msg_tx = rectpulse(msg_tx,nSamp);

h1 = scatterplot(msg_tx);

randn('state', seed(2));

msg_rx = awgn(msg_tx, SNR, 'measured', [], 'dB');

h2 = scatterplot(msg_rx);

RESULT:

Thus the corresponding plot for the QPSK constellation and BER were obtained.


modeling and simulation lab

Documents

vidyaa vikas

simulation

fpga implementation

attribute

simulation

file

program

alarmstate