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Modeling Embedded Systems
Tajana Simunic Rosing Department of Computer Science and Engineering University of California, San Diego.
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Models, Languages and Tools Sequent. program
State
machine
Data- flow
Concurrent processes
C/C++
Verilog
Java
VHDL
Implementation A
Implementation
B
Implementation
C
Components of a formal design model n Functional specification
¨ Relationships between inputs, outputs & states n Properties
¨ Relations between I/O/S that can be checked against the functional specification
¨ 3 types: inherent in model of computation, those that can be verified syntactically & semantically for a given specification
n Performance indices ¨ Evaluate quality of design
n Constraints ¨ On performance indices, usually inequalities
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Design process Design: n A set of components interacting with each other and with the environment
that is not a part of design Model of Computation (MOC): n Defines the behavior and interaction of the design blocks Design process: n Takes a model at a higher level of abstraction and refines it to a lower
level along with mapping constraints, performance indices and properties to the same level
Validation: n Process of checking if design is correct
¨ Simulation/emulation, formal verification of specification or implementation Synthesis: n Design refinement where more abstract specifications are translated into
less abstract specifications 5
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Models of Computation Elements n State
¨ e.g. in HW : n Combinational states: one state for a given time t n Sequential states: multiple states possible for time t
n Decidability ¨ Can a property be determined in a finite amount of
time? n Concurrency and communication
¨ Embedded systems usually have coordinated concurrent processes -> communication required
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Communication
¨ Blocking
… send () …
… receive () …
… send () …
… receive () …
… send () …
… receive () … ack … process a {
.. P(S) //obtain lock .. // critical section V(S) //release lock }
process b { .. P(S) //obtain lock .. // critical section V(S) //release lock }
n Message Passing ¨ Non-blocking
n Shared memory
¨ Extended rendezvous
Models of computation comparison Communication/ local computations
Shared memory
Message passing Synchronous | Asynchronous
Communicating finite state machines
StateCharts SDL
Data flow (Not useful) Kahn networks, DFG, SDF
Petri nets various versions of Petri Nets
Discrete event (DE) model
VHDL*, Verilog*, SystemC*, …
Only experimental systems, e.g. distributed DE in Ptolemy
Von Neumann model+ C, C++, Java C, C++, Java & libraries, ADA
*Classification based on implementation with centralized data structures +Consists of a processing unit, control unit and storage for instructions & data
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Model of Computation Examples n State machine models
¨ FSM, StateCharts , SDL n Petri nets n Communicating processes
¨ Kahn processes, Communicating Sequential Processes n Ada n Dataflow models
¨ DFG, SDFG n Discrete event models
¨ VHDL, Verilog, SystemC, SpecC n Synchronous languages
¨ Cycle based models, Esterel, Lustre
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Classical automata
• Moore-automata: O = H(S); S+ = f(I, S)
• Mealy-automata O = H(I, S); S+ = f(I, S)
Internal state S input I output O
S0 S1
S2 S3
e=1
e=1
e=1
e=1 0 1
2 3
clock
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Finite-state machines (FSMs)
Idle
GoingUp
req > floor
req < floor
!(req > floor)
!(timer < 10)
req < floor
DoorOpen
GoingDn
req > floor
u,d,o, t = 1,0,0,0
u,d,o,t = 0,0,1,0
u,d,o,t = 0,1,0,0
u,d,o,t = 0,0,1,1
u is up, d is down, o is open
req == floor
!(req<floor)
timer < 10
t is timer_start
Elevator Control process using a state machine
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Elevator Control with Fire Mode
n FireMode ¨ When fire is true, move elevator to 1st floor and open door
Idle
GoingUp
req>floor
req<floor
!(req>floor)
timeout(10)
req<floor
DoorOpen
GoingDn
req>floor
u,d,o = 1,0,0
u,d,o = 0,0,1
u,d,o = 0,1,0
req==floor
!(req<floor)
fire
fire fire
fire
FireGoingDn
floor>1
u,d,o = 0,1,0
u,d,o = 0,0,1
!fire
FireDrOpen
floor==1
fire
u,d,o = 0,0,1
UnitControl
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Models of Computation n State Machine Models
¨ FSM, StateCharts , CFSM, SDL n Petri nets n Communicating Processes
¨ Kahn processes, Communicating Sequential Processes n Ada n Dataflow models
¨ DFG, SDFG n Discrete Event Systems
¨ VHDL, Verilog, SystemC, SpecC n Synchronous languages
¨ Cycle based models, Esterel, Lustre
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Back to Elevator Example
fire
!fire FireGoingDn
floor>1
u,d,o = 0,1,0
FireDrOpen
floor==1
fire
FireMode
u,d,o = 0,0,1
Idle
GoingUp
req>floor
req<floor
!(req>floor)
timeout(10)
req<floor
DoorOpen
GoingDn
req>floor
u,d,o = 1,0,0
u,d,o = 0,0,1
u,d,o = 0,1,0
req==floor !(req>floor)
u,d,o = 0,0,1
NormalMode
UnitControl NormalMode
FireMode
fire !fire
UnitControl ElevatorController
RequestResolver
...
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StateCharts: edge labels event [condition] / reaction
n Events: ¨ Exist only until the next evaluation of the model ¨ Can be either internally or externally generated
n Conditions: ¨ Refer to values of variables that keep their value until they are
reassigned n Reactions:
¨ Can either be assignments for variables ¨ or creation of events
n Example: ¨ service-off [not in Lproc] / service:=0
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StateCharts: Simulation
Status= values of all variables + set of events + current time Step = execution of the three phases
Status phase 2 phase 3
phase 1
Three phases: 1. Effects of external changes on events and conditions are evaluated, 2. The set of transitions to be made in the current step and right hand
sides of assignments are computed, 3. Transitions become effective, variables obtain new values.
Statecharts – Example 1
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A B Ce
f
g h
D
k m
A B C
D
g
f h
e
k k k m
Equivalent FSM Representation
Statechart Example
Statecharts – Example 2
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A Bf
g
n Ek
m C D
h
Statechart Example
AC AD BC BD
E
n n
f f
g g
h h
m m m m k Equivalent FSM Representation
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StateCharts: Application Examples n Power converter system for trams, metros & trains
¨ System-level modeling and automated code generation ¨ Guarantee latencies less than 10 microseconds ¨ Cut development time by 50% ¨ Time from design completion to first prototype down to 1hr
from 3 months ¨ Defect free code automatically generated for a number of
RTOS implementations
By Alstom
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StateCharts: Application Examples n Development of defibrillator and pacemaker
technology ¨ Model system behavior before requirements are finalized ¨ Check that SW provides mathematically consistent
representation of the product’s system – correct and unambiguous representation of model behavior
¨ More accurate and extensive verification – guarantee device works 100% of the time for at least 7-10yrs
¨ Cut product verification costs by 20% ¨ 15-20% overall cost reduction per projects on future
development
By Guidant CRM
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StateCharts: Application Examples n Jet engine electronic controller design
¨ System level specification and consistency check ¨ Construction of on-screen simulation of the cockpit display ¨ Evaluate correctness in normal and faulty operation
modes ¨ Project so successful that now StateCharts are used for:
n Independent overspeed protection system n Thrust reverse control system n Engine fuel control system
By BMW
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StateCharts: Summary n Hierarchy n AND- and OR-super states n Default state, History n Timing behavior n State oriented behavior n Edge labels n Concurrency n Synchronization & communication
¨ Broadcast, shared memory n Simulation n Cross compiling
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Models of Computation n State Machine Models
¨ FSM, StateCharts , SDL n Petri nets n Communicating Processes
¨ Kahn processes, Communicating Sequential Processes n Ada n Dataflow models
¨ DFG, SDFG n Discrete Event Systems
¨ VHDL, Verilog, SystemC, SpecC n Synchronous languages
¨ Cycle based models, Esterel, Lustre
SDL n Designed for specification of distributed systems.
n Dates back to early 70s,formal semantics defined in the late 80s, updates from 1984 to 1999 by International Telecommunication Union (ITU)
n Provides textual and graphical formats
n Similar to StateCharts, each FSM is called a process, but it uses message passing instead of shared memory for communication
n Supports operations on data
Communication among SDL-FSMs n Communication between FSMs (or “processes“)
is based on message-passing, assuming a potentially indefinitely large FIFO-queue.
§ Each process fetches next entry from FIFO,
§ checks if input enables transition,
§ if yes: transition takes place,
§ if no: input is ignored (exception: SAVE-mechanism).
Determinate? n Let tokens be arriving at FIFO at the same time: FOrder in which they are stored is unknown:
All orders are legal so simulators can show different behaviors for the same input, all of which are correct.
Operations on data n Variables can be declared locally for processes. n Their type can be predefined or defined in SDL itself. n SDL supports abstract data types (ADTs)
Process interaction diagrams n Interaction between processes can be described in
process interaction diagrams, which are a special case of block diagrams
n In addition to processes, these diagrams contain channels and declarations of local signals.
,B
Hierarchy in SDL n Process interaction diagrams can be included in
blocks. The root block is called system.
Processes cannot contain other processes, unlike in StateCharts.
Timers n Timers can be declared locally n Elapsed timers put signal into queue, but are not necessarily
processed immediately n RESET removes a timer also from FIFO-queue.
Vending machine example Machine sells pretzels, chips, cookies, & doughnuts
Accepts nickels, dime, quarters, and half-dollars
It is not a distributed application.
° [J.M. Bergé, O. Levia, J. Roullard: High-Level System Modeling, Kluwer Academic Publishers, 1995]
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SDL: Real World Example n ADSL design
¨ Ideal language for telecom design; communication between components and their different states of operation can be easily modeled with SDL
¨ Object orientation and automatic code generation significantly simplified system design verification
¨ Early testing done on SDL – significant savings in the cost of expensive test equiptment
By Siemens
SDL summary ¨ FSM model for the components, ¨ Non-blocking message passing for communication, ¨ Implementation requires bound for the maximum length of
FIFOs; may be very difficult to compute, ¨ Not necessarily determinate ¨ Timer concept adequate just for soft deadlines, ¨ Limited way of using hierarchies, ¨ Limited programming language support, ¨ No description of non-functional properties, ¨ Excellent for distributed applications (used for ISDN), ¨ Commercial tools available (see http://www.sdl-forum.org)
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Models of Computation n State Machine Models
¨ FSM, StateCharts , SDL, CFSM n Petri nets n Communicating Processes
¨ Kahn processes, Communicating Sequential Processes n Ada n Dataflow models
¨ DFG, SDFG n Discrete Event Systems
¨ VHDL, Verilog, SystemC, SpecC n Synchronous languages
¨ Cycle based models, Esterel, Lustre
Petri nets: confusion J n Concurrency & conflict lead
to confusion…. ¨ Symmetric ¨ Asymmetric
58 Tajana Simunic Rosing Source: Murata’89
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Producer-Consumer with Priority
n Modeling synchronization control when sharing resources n Multiprocessor CPUs, distributed systems
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Petri Net Properties n Behavioral
¨ Reachability n Marking M reachable from marking Mo
¨ k - Boundedness n Number of tokens in each place does not exceed finite number k n Safe if 1-bounded
¨ Liveness n Can fire any transition of the net – related to absence of deadlocks
n Structural ¨ Controlability
n Any marking can be reached from any other marking ¨ Structural boundednes ¨ Conservativeness – weighted sum of tokens constant
Petri Net Liveness n L0-live (dead): a particular transition can
never fire ¨ In the figure below, t0 can never fire
n see reachability graph
Petri Net Liveness n L1-live: a particular transition can fire at
least once for some firing sequence ¨ In the figure below, t1 can only fire once, for
some firing sequence
Petri Net Liveness n L2-live: a particular transition can fire k
times for a particular firing sequence, for any k. ¨ In the figure below, t2 can only fire once,
twice, etc, for different firing sequences
Petri Net Liveness n L3-live: a particular transition can fire
infinitely in a particular firing sequence. ¨ In the figure below, t3 can fire infinitely for the
firing sequence t3, t3, t3, t3,… ¨ Note that the number of times t1 and t2, fire is
finite for any firing sequence.
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Petri Nets - Analysis
n Structural ¨ Incidence matrix
n State Space Analysis techniques ¨ Coverability Tree ¨ Reachability Graph
Example n Assume
¨ e=6 ¨ Mo=[0 12]
n Can we reach M=[6 0] from Mo? n Can it be statically scheduled? n What size buffers are needed at
P1 & P2?
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P1
P2T1 T2
32
4 e
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Petri nets: Applications n Model, simulate and analyze networking
protocols (e.g. TCP, Ethernet, etc) n Model, simulate and analyze complex network
elements (e.g. router, switch, optical mux); check their logical behavior
n Design and analyze network performance and AoS with logical models of traffic generators, protocols and network elements
n Study network behavior characteristics (e.g. throughput, blocking probability etc)
By Siemens
Petri nets in practice
n Example apps: ¨ TCP performance ¨ Security system
design and automated code geneeration
¨ MAC design ¨ ….
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Petri Nets - Summary n PN Graph
¨ places (buffers), transitions (action), tokens (data)
n Firing rule ¨ Transition enabled if enough tokens in a place
n Properties ¨ Structural (consistency, structural boundedness) ¨ Behavioral (reachability, boundedness, etc.)
n Analysis techniques n Applications
¨ Modeling of resources, mutual exclusion, synchronization
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Models of Computation n State Machine Models
¨ FSM, StateCharts , SDL, CFSM n Petri nets n Communicating Processes
¨ Communicating Sequential Processes, Ada, Kahn processes n Dataflow models
¨ DFG, SDFG n Discrete Event Systems
¨ VHDL, Verilog, SystemC, SpecC n Synchronous languages
¨ Cycle based models, Esterel, Lustre n HW Models n Unified Modeling Language (UML)
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Process n A sequential program
¨ Executes concurrently with other processes
n Basic operations on processes ¨ Create & terminate, suspend &
resume, join n Process communication
¨ Shared memory (and mutexes) ¨ Message passing ¨ Rendezvous
buttons inside
elevator
Unit Control
b1
down
open
floor
...
Request Resolver
...
up/down buttons on
each floor
b2 bN
up1 up2 dn2
dnN
req
up
System interface
up3 dn3
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ADA-rendez-vous task screen_out is entry call_ch(val:character; x, y: integer); entry call_int(z, x, y: integer); end screen_out; task body screen_out is ... select accept call_ch ... do .. end call_ch; or accept call_int ... do .. end call_int; end select;
Sending a message: begin screen_out.call_ch('Z',10,20); exception when tasking_error => (exception handling) end;
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Task graphs
Nodes are a „program“ described in some programming language
Sequence constraint
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Models of Computation n State Machine Models
¨ FSM, StateCharts , SDL, CFSM n Petri nets n Communicating Processes
¨ Communicating Sequential Processes, Ada n Dataflow models
¨ Kahn processes ¨ DFG, SDFG
n Discrete Event Systems ¨ VHDL, Verilog, SystemC, SpecC
n Synchronous languages ¨ Cycle based models, Esterel, Lustre
n Petri nets n HW Models n Unified Modeling Language (UML)
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Kahn process network
process channel
KPN - executable task graphs
Communication is via infinitely large FIFOs
Nonblocking write, blocking read => DETERMINATE
Important properties of KPN: Continuous
Output signals can be gradually produced; never have to consume all input to produce some output
Monotonic Output depends on input but doesn’t change previous output
Continuous monotonic processes => ITERATIVE
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Petri net model of a Kahn process
n KPNs are deterministic: ¨ Output determined by
n Process, network, initial tokens
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Modeling Embedded Systems
Tajana Simunic Rosing Department of Computer Science and Engineering University of California, San Diego.
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Dataflow Process Networks A
B
C D
modulate convolve
transform
A B C D
Z
Nodes with more complex transformations
t1 t2
+ –
*
A B C D
Z
Nodes with arithmetic transformations
t1 t2
Z = (A + B) * (C - D)
n Dataflow: ¨ Maps input tokens to output tokens ¨ Outputs function of current inputs
n No need to keep state on suspend/resume
¨ Scheduling for resource sharing
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Dataflow process examples n HW resource scheduling
¨ Constraints: 2 mult, 2 ALU ¨ List scheduler ¨ Additional constraints
n Performance n Power n Area etc.
*
NOP
*
*
<
*
*
+
NOP
1 2
3
4
5
6
7 *
8
+ 9
10
11
0
n
T1
T2
T3
T4
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SDF notation n Nodes have rates of data production or
consumption. n Edges have delays.
¨ Delays do not change rates, only the amount of data stored in the system at startup.
+ - 1 2
5 0
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SDF Scheduling n By building a set of “flow and
conservation” equations 3a – 2b = 0 4b – 3d = 0 b – 3c = 0 2c – a = 0 d – 2a = 0 Solution: a = 2c; b = 3c; d = 4c Possible schedules: BBBCDDDDAA BDBDBCADDA BBDDBDDCAA …
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Dataflow process examples n Design of a first 802.11b WLAN card
¨ New product – combines RF, MAC and PHY; lots of DSP ¨ Implemented on an ASIC ¨ Previous design hand coded VHDL
n System level design with COSSAP by Synopsys ¨ Explore architectural trade-offs – what in gates, what on DSP ¨ Scheduling trade-offs: latency, area, propagation delay between
clocks, and vendor library n Results:
¨ Reduced time to market by a factor of TWO! ¨ Architectural exploration within 10% of actual measurements in
terms of timing and area
by Symbol Tech.
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Models of Computation n State Machine Models
¨ FSM, StateCharts , SDL, CFSM n Petri nets n Communicating Processes
¨ Kahn processes, Communicating Sequential Processes n Ada n Dataflow models
¨ DFG, SDFG n Discrete Event Systems
¨ VHDL, Verilog, SystemC, SpecC n Synchronous languages
¨ Cycle based models, Esterel, Lustre n HW Models n Unified Modeling Language (UML)
126 Tajana Simunic Rosing
Discrete Events n Notion of time is fundamental: global order
¨ events are objects which carry ordered time info ¨ there is a casual relationship between events
n DE simulator maintains global event queue ¨ Verilog, VHDL
n Expensive - ordering tame stamps can be time consuming
n Large state & Low Activity => Effective simulation n Simultaneous events lead to non-determinacy
¨ require complex conflict resolution schemes ¨ e.g. delta delays
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Simultaneous Events in the Discrete Event Model
A B C t
t
A B C
t
A B C
t
t
B has 0 delay B has delta delay
t+
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VHDL: Entities entity full_adder is port(a, b, carry_in: in Bit; -- input ports sum,carry_out: out Bit); --output ports end full_adder;
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VHDL: Architectures architecture structure of full_adder is
component half_adder port (in1,in2:in Bit; carry, sum:out Bit); end component;
component or_gate port (in1, in2:in Bit; o:out Bit); end component; signal x, y, z: Bit; -- local signals begin -- port map section i1: half_adder port map (a, b, x, y); i2: half_adder port map (y, carry_in, z, sum); i3: or_gate port map (x, z, carry_out); end structure;
architecture behavior of full_adder is begin sum <= (a xor b) xor carry_in after 10 Ns; carry_out <= (a and b) or (a and carry_in) or (b and carry_in) after 10 Ns; end behavior;
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VHDL processes & waits Processes model HW parallelism
process begin a <= b after 10 ns end
process
begin prod <= x and y ; wait on x,y; end process;
process (x, y)
begin prod <= x and y ; end process;
Waits: wait until signal list;
wait until a; wait until condition;
wait until c='1'; wait for duration;
wait for 10 ns; wait; suspend indefinitely wait on = sensitivity list
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VHDL Simulation of an RS FF architecture one of RS_Flipflop is begin process: (R,S,Q,nQ) begin Q <= R nor nQ; nQ <= S nor Q; end process; end one;
0ns 0ns+δ 0ns+2δ
R 1 1 1
S 0 0 0
Q 1 0 0
nQ 0 0 1
0001
1100
0000
0111
1st δ
2nd δ
δ cycles reflect the fact that no real gate comes with zero delay.
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VHDL Summary n Entities and architectures n Multiple-valued logic n Modeling hardware parallelism by processes
¨ Wait statements and sensitvity lists n VHDL simulation cycle
¨ δ cycles
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Models of Computation n State Machine Models
¨ FSM, StateCharts , SDL, CFSM n Petri nets n Communicating Processes
¨ Kahn processes, Communicating Sequential Processes n Ada n Dataflow models
¨ DFG, SDFG n Discrete Event Systems
¨ VHDL, Verilog, SystemC, SpecC n Synchronous reactive languages
¨ Cycle based models, Esterel, Lustre n HW Models n Unified Modeling Language (UML)
Tajana Simunic Rosing
Reactive Synchronous Languages n Assumptions
¨ Instantaneous reactions ¨ Discrete event ¨ Static
n Cycle based models ¨ Excellent for (single) clocked synchronous circuits
n Control flow oriented (imperative) languages ¨ Esterel
n Data flow languages ¨ Lustre, Signal
n Deterministic behavior n Simulation, software and hardware synthesis,
verification
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Reactive Synchronous Models: Esterel Statements
n Emit S n Present S then p else q end n Pause n P; Q, P||Q n Loop p end n Await S n Abort p when S n Suspend p when S n Sustain S = (loop emit S; pause end)
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Abort Statement Normal termination Aborted termination Aborted termination, Emit A preempted Normal termination B not checked in the first cycle (like await)
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Time in Esterel n Global clock with precise control over
when events appear ¨ At every tick: read inputs, compute, output
n Statements ¨ A bounded number in one cycle
n Emit, present, loop
¨ Take multiple cycles: n Pause, await, sustain
n Causality analysis ¨ Deterministic & non-contradictory
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Esterel Application Examples ● TI used Esterel to automatically synthesize full
coverage tests for a safety-critical design ● Showed functional coverage covered only 30% of the
design, with Esterl 100% covered ● Airbus
● Significant decrease in errors due to increase in automated code generation (40-70%) ● e.g fly by wire controls & automatic flight control 70%, display
computer 50%, warning & maintenance computer 40% ● Major increase in productivity
146 Tajana Simunic Rosing
Esterel Summary ● Reactive synchronous language ● Control flow oriented ● Imperative syntax ● Synchrony assumption useful for safety
critical embedded systems ● Convert timing relations to causal ordering ● Used in verification
● e.g. TI, Airbus
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Models of Computation n State Machine Models
¨ FSM, StateCharts , SDL, CFSM n Petri nets n Communicating Processes
¨ Kahn processes, Communicating Sequential Processes n Ada n Dataflow models
¨ DFG, SDFG n Synchronous languages
¨ Cycle based models, Esterel, Lustre n Discrete Event Systems
¨ VHDL, Verilog, SystemC, SpecC n HW Models n Unified Modeling Language (UML)
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Levels of hardware modeling 1. System level 2. Algorithmic level 3. Instruction set level 4. Register-transfer level (RTL) 5. Gate-level models 6. Switch-level models 7. Circuit-level models 8. Device-level models 9. Layout models 10. Process and device models
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Instruction level
Assembler (MIPS) Simulated semantics and $1,$2,$3 Reg[1]:=Reg[2] ∧ Reg[3]
or $1,$2,$3 Reg[1]:=Reg[2] ∨ Reg[3]
andi $1,$2,100 Reg[1]:=Reg[2] ∧ 100
sll $1,$2,10 Reg[1]:=Reg[2] << 10
srl $1,$2,10 Reg[1]:=Reg[2] >> 10
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Register transfer level: MIPS Controller
BP
C
Inst
ruct
ion
regi
ster
IR
Mem
ory
Spe
iche
r
alu_
co
ntro
l
T
sign_ extend
<<2
4
*
ALU
Reg
0
0
0
0
0
01
1
1
1
1
1
2
2
3
§
31:26
25:21
20:16
25:0 15:0
15:11
i2
a2
a1
i3
a3
a
2
a1
o2
o
1
PC
Sou
rce
Targ
etW
rite
ALU
Op
ALU
Sel
A
ALU
Sel
B
Reg
Writ
e
Reg
Des
t
Mem
ToR
eg
IRW
rite
Mem
Rea
d
Mem
Writ
e
PC
Writ
e
PC
Writ
eC
IorD
* § 31: 28
"00“
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Models of Computation n State Machine Models
¨ FSM, StateCharts , SDL, CFSM n Petri nets n Ada n Communicating Processes
¨ Kahn processes, Communicating Sequential Processes n Dataflow models
¨ DFG, SDFG n Synchronous languages
¨ Cycle based models, Esterel, Lustre n Discrete Event Systems
¨ VHDL, Verilog, SystemC, SpecC n HW Models n Unified Modeling Language (UML)
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UML (Unified modeling language)
From
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UML Summary § UML
- State machine diagram (StateChart-like) - Activity diagram (extended Petri nets) - Deployment diagram (exec. arch.) - Use case diagram - Package diagram (hierarchy) - Class diagrams - Timing diagrams (UML 2.0), UML for real-time
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Models and Languages Summary n Multiple models and languages are essential for high-
level design ¨ Managing complexity by abstraction ¨ Formality ensures refinement correctness ¨ Model choice depends on
n Class of applications n Required operations (synthesis, scheduling, ...)
n Multiple MOCs can co-exist during all phases of design ¨ Specification ¨ Architectural mapping and simulation ¨ Synthesis, code generation, scheduling ¨ Detailed design and implementation ¨ Co-simulation
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Sources and References
n Peter Marwedel, “Embedded Systems Design,” 2004. n Frank Vahid, Tony Givargis, “Embedded System
Design,” Wiley, 2002. n Wayne Wolf, “Computers as Components,” Morgan
Kaufmann, 2001. n Axel Jantsch, “Modeling Embedded Systems and
SOCs,” Morgan Kaufmann, 2004. n Alberto Sangiovanni-Vincentelli @ UCB n Mani Srivastava @ UCLA n Rajesh Gupta @ UCSD n Nikil Dutt @ UCI