modeling real-time system architectures bran selic ...modeling real-time system architectures bran...
TRANSCRIPT
![Page 1: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/1.jpg)
Mod
elin
g Re
al-T
ime
Syst
em
Arch
itect
ures
Bran
Sel
icPr
inci
pal E
ngin
eer
IBM
Sof
twar
e G
roup
–R
atio
nal S
oftw
are
bsel
ic@
ca.ib
m.c
om
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2
Lab
Bu
ildin
g
rin
g r
oad
A Pa
rabl
e
♦“A
rchi
tect
ural
” dec
ay, c
ause
d by
:�
Lack
of h
igh-
leve
l (ar
chite
ctur
al) v
iew
(“th
e fo
rest
vs
the
trees
”)�
Diff
icul
ties
in fo
rmal
ly e
nfor
cing
arc
hite
ctur
al d
ecis
ions
Lisl
e, Il
linoi
s:
![Page 3: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/3.jpg)
3
The
Case
of S
oftw
are
♦M
ost s
oftw
are
syst
ems
are
cons
truct
ed b
y la
bor-i
nten
sive
m
icro
con
stru
ctio
n m
eans
: …
.one
line
of c
ode
(tree
) at a
tim
e
♦Ea
ch li
ne o
f cod
e re
pres
ents
mul
tiple
des
ign
deci
sion
s
…an
y on
e of
thos
e de
cisi
ons
may
resu
lt in
a c
atas
troph
ic
failu
re o
f the
ent
ire s
yste
m
♦Th
e lik
elih
ood
of fa
ilure
exc
eeds
the
likel
ihoo
d of
suc
cess
…w
hat c
an w
e do
?
![Page 4: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/4.jpg)
4
Thes
is: W
hat W
e Ca
nDo
♦D
esig
n an
d im
plem
ento
ur s
yste
ms
at th
e ap
prop
riate
(h
igh)
leve
l of a
bstra
ctio
n
…us
ing
a sp
ecifi
catio
n la
ngua
ge/fo
rm th
at m
atch
es th
e pr
oble
m
♦Si
gnifi
cant
ly in
crea
se th
e le
vel o
f aut
omat
ion
in th
e en
tire
proc
ess
but p
artic
ular
ly d
urin
g im
plem
enta
tion
…to
pre
vent
arc
hite
ctur
al d
ecay
![Page 5: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/5.jpg)
5
Pres
enta
tion
Ove
rvie
w♦
Mod
els
and
mod
elin
g in
sof
twar
e♦
Req
uire
men
ts fo
r arc
hite
ctur
al m
odel
ing
♦C
once
pts
for a
rchi
tect
ural
mod
elin
g♦
Arch
itect
ural
pat
tern
s fo
r em
bedd
ed s
oftw
are
![Page 6: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/6.jpg)
6
Early
Sof
twar
e M
odel
s
“…bu
bble
s an
d ar
row
s, a
s op
pose
d to
pro
gram
s,
…ne
ver c
rash
”--
B. M
eyer
“UM
L: T
he P
ositi
ve S
pin”
Amer
ican
Pro
gram
mer
, 199
7
Mon
itor
PH Rais
ePH
Cont
rol
PH
PH re
ache
d X
enab
le disa
ble
Curr
ent P
H
star
t
stop
Inpu
t val
veco
ntro
l
![Page 7: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/7.jpg)
7
Mon
itor
PH Rais
ePH
Cont
rol
PH
PH re
ache
d X
enab
le disa
ble
Curr
ent P
H
star
t
stop
Inpu
t val
veco
ntro
l
…an
d W
hy T
hey
Faile
d
main () {
BitVector typeFlags
(maxBits);
char buf
[1024];
cout
<<
msg;
while (cin
>>
buf) {
if ...
?Im
ple
men
tin
g
pro
gra
m
![Page 8: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/8.jpg)
8
Engi
neer
ing
Mod
els
![Page 9: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/9.jpg)
9
Wha
t Eng
inee
rs D
o♦
Befo
re th
ey b
uild
the
real
thin
g...
…th
ey fi
rst b
uild
mod
els…
and
then
lear
n fro
m th
em
�
➼ ➼➼➼�
![Page 10: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/10.jpg)
10
�Pu
rpos
e:To
hel
p us
und
erst
and
a co
mpl
ex p
robl
em o
r sol
utio
nTo
com
mun
icat
e id
eas
abou
t a p
robl
em o
r sol
utio
nTo
driv
e im
plem
enta
tion
Engi
neer
ing
Mod
els
♦En
gine
erin
g m
odel
:A
redu
ced
repr
esen
tatio
n of
som
e sy
stem
Mod
elM
odel
ed s
yste
m
![Page 11: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/11.jpg)
11
Char
acte
ristic
s of
Use
ful M
odel
s♦
Abst
ract
�Em
phas
ize
impo
rtant
asp
ects
whi
le h
idin
g/re
mov
ing
irrel
evan
t one
s
♦U
nder
stan
dabl
e�
Expr
esse
d in
a fo
rm th
at is
read
ily u
nder
stoo
d by
obs
erve
rs
♦Ac
cura
te�
Faith
fully
repr
esen
ts th
e m
odel
ed s
yste
m
♦Pr
edic
tive
�C
an b
e us
ed to
der
ive
corre
ct c
oncl
usio
ns a
bout
the
mod
eled
sys
tem
♦In
expe
nsiv
e�
Muc
h ch
eape
r to
cons
truct
and
stu
dy th
an th
e m
odel
ed s
yste
m
Mos
t sof
twar
e m
odel
s of
the
past
faile
d on
one
or
mor
e of
thes
e po
ints
!
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12
SC_MODULE(producer)
{ sc_outmaster<int> out1;
sc_in<bool> start; // to kick-start the
producer
void generate_data ()
{ for(int
i =0; i <10; i++).{
out1 =i ; //this will invoke the slave;}
} SC_CTOR(producer)
{ SC_METHOD(generate_data);
sensitive << start;}};
SC_MODULE(consumer)
{ sc_inslave<int> in1;
int
sum; // declare as a module state variable
void accumulate (){
sum += in1;
cout<< “Sum = “ << sum <<
endl;}
SC_CTOR(consumer)
{ SC_SLAVE(accumulate, in1);
sum = 0; // initialize the
accumulator}};
SC_MODULE(top) // structural module
{ producer *A1;
consumer *B1;
sc_link_mp<int> link1;
SC_CTOR(top)
{ A1 = new producer(“A1”);
A1.out1(link1);
B1 = new consumer(“B1”);
B1.in1(link1);}};
Mod
els
of S
oftw
are
«sc_
slav
e»co
nsum
er«s
c_m
etho
d»pr
oduc
erst
art
out1
in1
«sc_
link_
mp»
link1
![Page 13: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/13.jpg)
13
Mod
el E
volu
tion:
Add
ing
Deta
il
♦D
etai
l can
be
adde
d co
ntin
uous
ly u
ntil
the
spec
ifica
tion
is c
ompl
ete
«sc_
met
hod»
prod
ucer
star
tou
t1
NotS
tarte
d
Star
tedstar
t
prod
ucer
NotS
tarte
d
Star
ted
star
t/gen
erat
e_da
ta( )
prod
ucer
void
gen
erat
e_da
ta()
{for (
int i
=0; i
<10;
i++)
{o
ut1
= I;}
}
St1
St2
![Page 14: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/14.jpg)
14
The
Rem
arka
ble
Thin
g Ab
out S
oftw
are
Softw
are
has
the
rare
pro
perty
that
it a
llow
s us
to d
irect
ly e
volv
e m
odel
s in
to fu
ll-fle
dged
im
plem
enta
tions
with
out c
hang
ing
the
engi
neer
ing
med
ium
, too
ls, o
r met
hods
!
⇒Th
is e
nsur
es p
erfe
ct a
ccur
acy
of s
oftw
are
mod
els;
th
e m
odel
and
the
mod
eled
sys
tem
are
iden
tical
The
mod
el is
the
impl
emen
tatio
n
![Page 15: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/15.jpg)
15
Mod
el-D
riven
Sty
le o
f Dev
elop
men
t♦
An a
ppro
ach
to s
oftw
are
deve
lopm
ent i
n w
hich
the
focu
s an
d pr
imar
y ar
tifac
ts o
f dev
elop
men
t are
mod
els
(as
oppo
sed
to p
rogr
ams)
�W
orki
ng in
the
prob
lem
dom
ain
rath
er th
an th
e im
plem
enta
tion
(tech
nolo
gy) d
omai
n
�Pl
atfo
rm in
depe
nden
ce
♦Ba
sed
on g
reat
er u
se o
f aut
omat
ion
�Au
tom
atic
gen
erat
ion
of c
ompl
ete
prog
ram
s fro
m m
odel
s�
Exec
utab
le m
odel
s –
early
in th
e de
sign
pro
cess
![Page 16: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/16.jpg)
16
Mod
elin
g ve
rsus
Pro
gram
min
g La
ngua
ges
♦C
over
diff
eren
t ran
ges
of a
bstra
ctio
n
Leve
l of
Abst
ract
ion
high
lowPr
ogra
mm
ing
Lang
uage
s(C
/C++
, Jav
a, …
)
Mod
elin
gLa
ngua
ges
(UM
L,…
)
∆ ∆∆∆ LO: :::da
ta la
yout
, ar
ithm
etic
alan
d lo
gica
lop
erat
ors,
etc.
∆ ∆∆∆ HI: :::st
atec
harts
,in
tera
ctio
ndi
agra
ms,
arch
itect
ural
stru
ctur
e, e
tc.
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17
Prog
ram
min
gLa
ngua
ge
Cove
ring
the
Full
Rang
e of
Det
ail
♦“A
ctio
n” la
ngua
ges
(e.g
., Ja
va, C
++) f
or fi
ne-g
rain
det
ail
Leve
l of
Abst
ract
ion
high
lowPr
ogra
mm
ing
Lang
uage
s(C
/C++
, Jav
a, …
)
Mod
elin
gLa
ngua
ges
(UM
L,…
)
impl
emen
tatio
n le
vel
Fine
-gra
inlo
gic,
arith
met
icfo
rmul
ae,
etc.
![Page 18: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/18.jpg)
18
Sum
mar
y: M
odel
s an
d So
ftwar
e M
odel
ing
♦M
odel
ing
is p
artic
ular
ly w
ell-s
uite
d fo
r sof
twar
e de
velo
pmen
t bec
ause
the
mod
els
can
be g
radu
ally
ev
olve
d in
to fu
ll-fle
dged
impl
emen
tatio
ns w
ith th
e ai
d of
co
mpu
ter-b
ased
aut
omat
ion
♦M
odel
-driv
en d
evel
opm
ent i
s an
app
roac
h to
sof
twar
e de
velo
pmen
t tha
t tak
es a
dvan
tage
of t
his
uniq
ue p
rope
rty�
Wor
king
clo
ser t
o th
e pr
oble
m d
omai
n
�Le
ads
to h
ighe
r pro
duct
ivity
and
relia
bilit
y�
Plat
form
inde
pend
ence
![Page 19: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/19.jpg)
19
Pres
enta
tion
Ove
rvie
w♦
Mod
els
and
mod
elin
g in
sof
twar
e♦
Req
uire
men
ts fo
r arc
hite
ctur
al m
odel
ing
♦C
once
pts
for a
rchi
tect
ural
mod
elin
g♦
Arch
itect
ural
pat
tern
s fo
r em
bedd
ed s
oftw
are
![Page 20: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/20.jpg)
20
(Run
-Tim
e) A
rchi
tect
ure
♦An
abs
tract
vie
w o
f a s
yste
m th
at id
entif
ies
only
the
impo
rtant
ele
men
ts a
nd re
latio
nshi
ps
♦W
e w
ill fo
cus
only
on
run-
time
arch
itect
ures
:
The
run-
time
orga
niza
tion
of s
igni
fican
t sof
twar
e
com
pone
nts
inte
ract
ing
thro
ugh
inte
rface
s, th
ose
com
pone
nts
bein
g co
mpo
sed
of s
ucce
ssiv
ely
smal
ler
com
pone
nts
and
inte
rface
s
![Page 21: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/21.jpg)
21
Why
Arc
hite
ctur
e is
Impo
rtant
♦En
able
s co
mm
unic
atio
n be
twee
n st
akeh
olde
rs�
expo
ses
how
indi
vidu
al re
quire
men
ts a
re h
andl
ed
♦D
rives
sys
tem
con
stru
ctio
n�
deco
mpo
sitio
n in
to u
nits
of r
espo
nsib
ility
and
para
llel
deve
lopm
ent
♦D
eter
min
es a
sys
tem
’s c
apac
ity fo
r evo
lutio
nary
gro
wth
A
CB
Med
iato
r
XA
CB
XA
CB
Med
iato
r
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22
Beh
avio
rS
ervi
ces
Lay
er
Ap
plic
atio
n L
ayer
Ter
min
alA
Ter
min
alB
Ch
ann
el1
Ch
ann
el2
Str
uct
ure
Exam
ple
Com
plex
Arc
hite
ctur
e Sp
ec♦
Exam
ple
tele
com
sys
tem
arc
hite
ctur
e
![Page 23: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/23.jpg)
23
Par
t
com
posi
tion
(exi
sten
ce d
epen
denc
y)
Basi
c Ru
n-Ti
me
Arch
itect
ural
Pat
tern
s
♦C
onta
inm
ent:
aggr
egat
ion
(info
rmat
ion
hidi
ng)
Lay
er N
+1
Lay
er N
Co
nta
iner
Par
t
Co
nta
iner
Par
t
Par
tBP
artA
�Pe
er-to
-pee
r com
mun
icat
ion:
�La
yerin
g
![Page 24: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/24.jpg)
24
Arch
itect
ural
Com
pone
nt D
esig
n
Sys
tem
2
Sys
tem
1L
ibra
ry
Ter
min
alA
Ter
min
alB
Ch
ann
el1
Ch
ann
el2
Ter
min
alA
Ter
min
alT
este
r
Ter
min
al
Ch
ann
el
Ter
min
alT
este
r
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25
Ter
min
alA
Ter
min
alB
Ch
ann
el1
Ch
ann
el2
Ter
min
alA
Ter
min
alB
Ch
ann
el1
Refin
ing
Arch
itect
ures
(Reu
se)
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26
Lab
Bu
ildin
g
Arch
itect
ural
Dec
ay
♦Th
e (u
sual
ly) g
radu
al d
iver
genc
e be
twee
n an
ar
chite
ctur
al m
odel
and
its
corre
spon
ding
pro
gram
im
plem
enta
tion
♦C
ause
d by
:
�M
isun
ders
tand
ings
of a
rchi
tect
ural
inte
nt
�D
esig
n di
sagr
eem
ents
�Im
plem
enta
tion
(cod
ing)
erro
rs
♦O
ften
occu
rs d
urin
g lo
w-le
vel m
aint
enan
ce w
ork
![Page 27: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/27.jpg)
27
Prev
entin
g Ar
chite
ctur
al D
ecay
♦En
sure
vis
ibilit
y an
d en
forc
emen
t of a
rchi
tect
ural
inte
nt
♦Ac
hiev
ed b
y:
�R
equi
ring
that
all
desi
gn w
ork
to ta
ke p
lace
at t
he m
odel
leve
l
�Au
tom
atic
ally
gen
erat
ing
impl
emen
tatio
ns d
irect
ly fr
om m
odel
s
…i.e
., us
e m
odel
-driv
en d
evel
opm
ent
![Page 28: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/28.jpg)
28
Sum
mar
y: R
equi
rem
ents
for A
rchi
tect
ural
Mod
elin
g
♦Th
e hi
ghes
t-lev
el s
peci
ficat
ions
of a
sof
twar
e sy
stem
�Ke
y to
suc
cess
ful s
yste
m d
efin
ition
, con
stru
ctio
n, a
nd e
volu
tion
�R
ecur
sive
not
ion:
sub
syst
ems
also
hav
e ar
chite
ctur
es
♦Ar
chite
ctur
al s
pecs
incl
ude
both
stru
ctur
e an
d be
havi
or♦
Stru
ctur
al a
spec
ts c
an b
e re
pres
ente
d by
com
bina
tions
of f
our
basi
c m
icro
-pat
tern
s♦
Sign
ifica
nt b
enef
its a
re o
btai
ned
if ar
chite
ctur
al m
odel
s ca
n be
obje
ct o
rient
ed♦
A ke
y re
quire
men
t is
the
abilit
y to
pre
serv
e an
arc
hite
ctur
e in
the
face
of e
volu
tion
�R
equi
res
visi
bilit
y an
d au
tom
ated
enf
orce
men
t�
Mod
els
and
MD
D s
eem
wel
l sui
ted
to th
is p
urpo
se
![Page 29: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/29.jpg)
29
Pres
enta
tion
Ove
rvie
w♦
Mod
els
and
mod
elin
g in
sof
twar
e♦
Req
uire
men
ts fo
r arc
hite
ctur
al m
odel
ing
♦C
once
pts
for a
rchi
tect
ural
mod
elin
g♦
Arch
itect
ural
pat
tern
s fo
r em
bedd
ed s
oftw
are
![Page 30: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/30.jpg)
30
Por
ts
Stru
ctur
ed O
bjec
ts: E
xter
nal S
truct
ure
♦C
ompl
ex o
bjec
ts w
ith m
ultip
le “f
aces
” �
Mul
tiple
inte
ract
ion
poin
ts: p
orts
�Ea
ch p
ort i
s de
dica
ted
to a
spe
cific
pur
pose
and
pre
sent
s th
e in
terfa
ce a
ppro
pria
te to
that
pur
pose
![Page 31: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/31.jpg)
31
S1
S2
S3
S1
S2
S1
tran
siti
on
S1t
oS
2:{i
nt
x;x
= 0;
p2.
sen
d(s
1);
p3.
sen
d(s
2);
… };
Stru
ctur
ed O
bjec
ts: I
nter
nal B
ehav
ior
♦M
ay a
ct a
s co
ntai
ners
for b
ehav
ior (
and
othe
r thi
ngs)
![Page 32: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/32.jpg)
32
call
ack
tim
e
nu
mb
er
call
ack
talk
tran
sfer
Cal
ler
Op
erat
or
Cal
lee
Prot
ocol
s: R
eusa
ble
Beha
vior
Pat
tern
s♦
Inte
ract
ion
cont
ract
s be
twee
n ca
psul
es�
e.g.
, ope
rato
r-ass
iste
d ca
ll
![Page 33: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/33.jpg)
33
Op
erat
orA
ssis
ted
Cal
l
Alic
e
Ch
arlie
Bo
bca
ller
calle
e
op
erat
or
initi
al
conn
ecte
d
conn
ectin
g
prot
ocol
sta
te m
achi
ne
calle
rop
erat
orca
llee
sign
ifica
nt s
eque
nces
Dex
ter
Prot
ocol
Spe
cific
atio
ns♦
A co
llabo
ratio
n th
at m
ay b
e re
quire
d on
mul
tiple
oc
casi
ons
and
situ
atio
ns
![Page 34: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/34.jpg)
34
sig
nal
sou
rce
call
calle
r
nu
mb
erca
ller
ack
calle
e
Inco
min
g s
ign
als
sig
nal
targ
et
call
calle
e
tran
sfer
calle
r
ack
calle
r
Ou
tgo
ing
sig
nal
s
Op
erat
orR
ole
initi
al
conn
ecte
d
conn
ectin
g
prot
ocol
sta
te m
achi
ne
calle
rop
erat
orca
llee
sign
ifica
nt s
eque
nces
Prot
ocol
Rol
es♦
Spec
ifies
one
par
ty in
a p
roto
col
![Page 35: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/35.jpg)
35
Prot
ocol
Ref
inem
ent
♦U
sing
sta
ndar
d in
herit
ance
sig
nal
sou
rce
call
calle
r
nu
mb
erca
ller
ack
calle
e
Inco
min
g s
ign
als
sig
nal
targ
et
call
calle
e
tran
sfer
calle
r
ack
calle
r
Ou
tgo
ing
sig
nal
s
Op
erat
orR
ole
sig
nal
sou
rce
call
calle
r
nu
mb
erca
ller
ack
calle
e
Inco
min
g s
ign
als
sig
nal
targ
et
call
calle
e
tran
sfer
calle
r
ack
calle
r
Ou
tgo
ing
sig
nal
s
rep
lyca
ller
qu
ery
calle
rE
xten
ded
Op
erat
orR
ole
![Page 36: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/36.jpg)
36
En
viro
nm
ent
c :
Cls
X
S1
S2
Ports
♦Bo
unda
ry o
bjec
ts th
at�
help
sep
arat
e di
ffere
nt (p
ossi
bly
conc
urre
nt) i
nter
actio
ns�
fully
isol
ate
an o
bjec
t’s in
tern
als
from
its
envi
ronm
ent
“The
re a
re v
ery
few
pro
blem
s in
com
pute
r sci
ence
that
ca
nnot
be
solv
ed b
y ad
ding
an
extra
leve
l of i
ndire
ctio
n”
![Page 37: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/37.jpg)
37
Ports
and
Pro
toco
ls♦
Each
por
t rea
lizes
a s
ingl
e pr
otoc
ol ro
le�
corre
spon
ds to
the
“type
” of t
he p
ort t
hat c
an b
e us
ed fo
r sta
tic
type
che
ckin
g�
exte
nsio
n of
the
tradi
tiona
l obj
ect i
nter
face
con
cept
with
a
dyna
mic
asp
ect
![Page 38: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/38.jpg)
38
Con
nect
ors
mod
el c
omm
unic
atio
n ch
anne
lsE
ach
conn
ecto
r su
ppor
ts a
sin
gle
prot
ocol
Sta
tic ty
ping
rul
es a
pply
(co
mpa
tible
pr
otoc
ols)
sen
der
: F
ax
rem
ote:
Fax
Pro
t
rece
iver
: F
axre
mot
e:F
axP
rot
Co
nn
ecto
r
Colla
bora
ting
Obj
ects
♦U
sing
con
nect
ors
![Page 39: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/39.jpg)
39
Fax
Cal
l
Rel
aypo
rtre
ceiv
eCtr
l: C
ontr
olse
ndC
trl:
Con
trol
c : C
ontr
olc
: Con
trol
sen
der
:Fax
rem
ote:
Fax
Pro
t
rece
iver
:Fax
rem
ote:
Fax
Pro
t
Com
posi
tion:
Stru
ctur
al P
atte
rns
![Page 40: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/40.jpg)
40
f1:F
axC
all
sen
der
:Fax
rece
iver
:Fax
f1 := create(FaxCall);
Stru
ctur
ed O
bjec
t Sem
antic
s♦
Run
-tim
e as
serti
on: t
he c
ompl
ete
inte
rnal
stru
ctur
e of
a
com
posi
te is
aut
omat
ical
ly c
reat
ed (r
ecur
sive
ly, i
f ne
cess
ary)
whe
n th
e ob
ject
is c
reat
ed
![Page 41: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/41.jpg)
41
Bene
fits
of R
un-T
ime
Asse
rtion
♦Ar
chite
ctur
al e
nfor
cem
ent:
only
exp
licitl
y pr
escr
ibed
ar
chite
ctur
al s
truct
ures
can
be
inst
antia
ted
�it
is n
ot p
ossi
ble
to b
ypas
s (c
orru
pt) t
he a
rchi
tect
ure
by lo
w-
leve
l pro
gram
min
g
♦Si
mpl
ifica
tion:
low
-leve
l pro
gram
cod
e th
at d
ynam
ical
ly
crea
tes
(des
troys
) com
pone
nts
and
the
conn
ectio
ns
betw
een
them
is e
limin
ated
�in
som
e sy
stem
s th
is c
an b
e as
muc
h as
35%
of a
ll co
de
♦M
ajor
net
gai
n in
pro
duct
ivity
and
relia
bilit
y
![Page 42: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/42.jpg)
42
sen
der
:Fax
c : C
ontr
ol
rece
iver
:Fax
c : C
ontr
ol
c : S
yste
mC
ontr
ol
Beha
vior
Por
ts rece
iveC
trl:
Con
trol
~se
nder
Ctr
l: C
ontr
ol~
Beh
avio
r P
ort
Impl
emen
tatio
nB
ehav
ior
Por
t
♦Po
rts d
irect
ly c
onne
cted
to th
e st
ate
mac
hine
initi
al
conn
ecte
d
conn
ectin
g
cont
aine
r st
ate
mac
hine
![Page 43: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/43.jpg)
43
Arch
itect
ural
Mod
elin
g an
d UM
L♦
Thes
e fu
ndam
enta
l arc
hite
ctur
al m
odel
ing
conc
epts
hav
e be
en in
corp
orat
ed in
to th
e la
test
ver
sion
of t
he U
ML
stan
dard
(UM
L 2.
0)�
Cur
rent
ly u
nder
goin
g st
anda
rdiz
atio
n (d
ue A
pril
2004
)
�To
ol s
uppo
rt al
read
y av
aila
ble
from
var
ious
ven
dors
♦U
ML
as a
n ar
chite
ctur
al d
escr
iptio
n la
ngua
ge
![Page 44: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/44.jpg)
44
Sum
mar
y: A
rchi
tect
ural
Mod
elin
g Co
ncep
ts
♦Si
gnifi
cant
con
verg
ence
am
ong
diffe
rent
AD
Ls o
n th
e ba
sic
conc
epts
nee
ded
for a
rchi
tect
ural
mod
elin
g�
ACM
E, U
ML-
RT,
SD
L, M
etaH
/AAD
L
�St
ruct
ured
obj
ects
, por
ts, c
onne
ctor
s, p
roto
cols
♦Th
e U
ML
2.0
stan
dard
incl
udes
all
the
basi
c co
ncep
ts
requ
ired
for m
odel
ing
softw
are
arch
itect
ure
![Page 45: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/45.jpg)
45
Pres
enta
tion
Ove
rvie
w♦
Mod
els
and
mod
elin
g in
sof
twar
e♦
Req
uire
men
ts fo
r arc
hite
ctur
al m
odel
ing
♦C
once
pts
for a
rchi
tect
ural
mod
elin
g♦
Arch
itect
ural
pat
tern
s fo
r em
bedd
ed s
oftw
are
![Page 46: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/46.jpg)
46
Desi
gn P
atte
rns
♦A
desi
gn p
atte
rnis
a p
rove
n ge
nera
lized
sol
utio
n to
a
gene
raliz
ed p
robl
em th
at c
an b
e us
ed to
der
ive
a sp
ecifi
c so
lutio
n to
a s
peci
fic p
robl
em
♦R
epre
sent
dis
tille
d re
usab
le e
xper
ienc
e
♦M
ajor
ben
efits
of u
sing
pat
tern
s:�
Sim
plify
and
spe
ed-u
p de
sign
�R
educ
e ris
k
�Fa
cilit
ate
com
mun
icat
ions
bet
wee
n de
sign
ers
![Page 47: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/47.jpg)
47
line
card
NEn
d us
er
line
card
1
unre
liabl
e tra
nsm
issi
onm
ediu
m
SW
ITC
H
. . .
AB
prot
ocol
AB
sen
der
AB
rece
iver
End
user
End
user
AB
sen
der
AB
rece
iver
Exam
ple
Syst
em♦
A m
ulti-
line
pack
et s
witc
h th
at u
ses
the
alte
rnat
ing-
bit
prot
ocol
as
its li
nk p
roto
col
![Page 48: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/48.jpg)
48
pack
etiz
erun
pack
erR
ecei
ver
Sen
der
Alte
rnat
ing
Bit P
roto
col (
1)♦
A si
mpl
e on
e-w
ay p
oint
-to-p
oint
pac
ket p
roto
col
dat
a(1)
ackA
pkt
Ad
ata(
1)
ack
ack
dat
a(2)
ackB
pkt
Bd
ata(
2)
ack
ack
AB
prot
ocol
…et
c.
![Page 49: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/49.jpg)
49
Sen
der
SM
ackB
/^ac
kda
ta/^
pktA
ackA
/^ac
kda
ta/^
pktB
timeo
ut/^
pktB
timeo
ut/^
pktA
Acc
eptP
ktA
Wai
tAck
A
Acc
eptP
ktB
Wai
tAck
B
pktA
/^da
taac
k/^a
ckA
pktB
/^da
taac
k/^a
ckB
timeo
ut/^
ackB
timeo
ut/^
ackA
Rcv
dP
ktA
Wai
tPkt
B
Rcv
dP
ktB
Wai
tPkt
A
Rec
eive
r S
M
Alte
rnat
ing
Bit P
roto
col (
2)♦
Stat
e m
achi
ne s
peci
ficat
ion
![Page 50: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/50.jpg)
50
Addi
tiona
l Con
side
ratio
ns♦
Supp
ort i
nfra
stru
ctur
e SW
ITC
H
AB
rece
iver
AB
sen
der
op
erat
or
inte
rfac
e
DB
inte
rfac
e
Sys
tem
op
erat
or
DB
ase
AB
lin
esm
anag
er
![Page 51: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/51.jpg)
51
Cont
rol
The
set o
f (ad
ditio
nal)
mec
hani
sms
and
actio
ns re
quire
d to
brin
g a
syst
em in
to th
e de
sire
d op
erat
iona
l sta
te a
nd to
m
aint
ain
it in
that
sta
te in
the
face
of v
ario
us p
lann
ed a
nd
unpl
anne
d di
srup
tions
�Fo
r sof
twar
e sy
stem
s th
is in
clud
es:
�sy
stem
/com
pone
nt s
tart-
up a
nd s
hut-d
own
�fa
ilure
det
ectio
n/re
porti
ng/re
cove
ry�
syst
em a
dmin
istra
tion,
mai
nten
ance
, and
pro
visi
onin
g�
(on-
line)
sof
twar
e up
grad
e
![Page 52: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/52.jpg)
52
Retro
fittin
g Co
ntro
l Beh
avio
r
Acce
ptPk
tA
Wai
tAck
A
Acce
ptPk
tB
Wai
tAck
B
Faile
d
Just
Crea
ted
Hard
war
eAu
dit
Get
tingD
ata
Read
yToG
o
Anal
ysin
gFa
ilure
![Page 53: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/53.jpg)
53
Faile
d
Just
Crea
ted
Hard
war
eAu
dit
Get
tingD
ata
Read
yToG
o
Anal
ysin
gFa
ilure
Ope
ratio
nal
The
Cont
rol A
utom
aton
♦In
isol
atio
n, th
e sa
me
cont
rol b
ehav
ior a
ppea
rs m
uch
sim
pler
![Page 54: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/54.jpg)
54
Cont
rol v
ersu
s Fu
nctio
n
♦C
ontro
l beh
avio
r is
ofte
n tre
ated
in a
n ad
hoc
man
ner,
sinc
e it
is n
ot p
art o
f the
prim
ary
syst
em fu
nctio
nalit
y
�ty
pica
lly re
trofit
ted
into
the
fram
ewor
k op
timiz
ed fo
r the
func
tiona
l beh
avio
r
�le
ads
to c
ontro
llabi
lity
and
stab
ility
prob
lem
s
♦H
owev
er, i
n hi
ghly
-dep
enda
ble
syst
ems
as m
uch
as
80%
of t
he s
yste
m c
ode
is d
edic
ated
to c
ontro
l beh
avio
r!
![Page 55: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/55.jpg)
55
Som
e Im
porta
nt O
bser
vatio
ns
♦C
ontro
l pre
dica
tes
func
tion
�be
fore
a s
yste
m c
an p
erfo
rm it
s pr
imar
y fu
nctio
n, it
firs
t has
to
reac
h its
ope
ratio
nal s
tate
♦C
ontro
l beh
avio
r is
ofte
n in
depe
nden
t of f
unct
iona
l
beha
vior
�th
e pr
oces
s by
whi
ch a
sys
tem
reac
hes
its o
pera
tiona
l sta
te is
ofte
n th
e sa
me
rega
rdle
ss o
f the
spe
cific
func
tiona
lity
of th
e
com
pone
nt
![Page 56: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/56.jpg)
56
The
Recu
rsiv
e Co
ntro
l Ar
chite
ctur
al P
atte
rn
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57
Basi
c De
sign
Prin
cipl
es
♦Se
para
te c
ontro
l fro
m fu
nctio
n
�se
para
te c
ontro
l com
pone
nts
from
func
tiona
l com
pone
nts
�se
para
te c
ontro
l int
erfa
ces
from
func
tiona
l int
erfa
ces
�im
bed
func
tiona
l beh
avio
r with
in c
ontro
l beh
avio
r
♦C
entra
lize
cont
rol (
deci
sion
mak
ing)
�if
poss
ible
, foc
us c
ontro
l in
one
com
pone
nt
�pl
ace
cont
rol p
olic
ies
in th
e co
ntro
l com
pone
nts
and
cont
rol
mec
hani
sms
insi
de th
e co
ntro
lled
com
pone
nts
![Page 58: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/58.jpg)
58
Co
ntr
olle
dC
om
po
nen
t 1
. . .
Co
ntr
olle
dC
om
po
nen
t N
Cont
rol
inte
rface
Func
tiona
l(s
ervi
ce)
inte
rface
Cen
tral
Co
ntr
olle
r
The
Basi
c St
ruct
ural
Pat
tern
♦Se
t of c
ompo
nent
s th
at n
eed
to b
e co
ntro
lled
in a
co
ordi
nate
d fa
shio
n
![Page 59: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/59.jpg)
59
Cen
tral
Co
ntr
olle
r
Co
ntr
olle
dCo
mpo
nent
1. .
.C
on
tro
lled
Com
pone
ntN
Cen
tral
Co
ntr
olle
r
. . .
Co
ntr
olle
dCo
mpo
nent
1. .
.C
on
tro
lled
Com
pone
ntN
Cen
tral
Co
ntr
olle
r
Recu
rsiv
e Ap
plic
atio
n♦
Hie
rarc
hica
l con
trol
�sc
ales
up
to a
rbitr
ary
num
ber o
f lev
els
![Page 60: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/60.jpg)
60
Co
mp
Set
Faile
d
Just
Crea
ted
Hard
war
eAu
dit
Get
tingD
ata
Read
yToG
o
Anal
ysin
gFa
ilure
Ope
ratio
nal
c1:C
om
p1
cN:C
om
pN
Real
izat
ion
with
Por
ts a
nd O
bjec
ts♦
Com
posi
te p
lays
role
of c
entra
lized
con
trolle
r
![Page 61: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/61.jpg)
61
Expl
oitin
g In
herit
ance
♦Ab
stra
ct c
ontro
l cla
sses
can
cap
ture
com
mon
con
trol
beha
vior
and
stru
ctur
e♦
Diff
eren
t sub
clas
ses
capt
ure
func
tion-
spec
ific
beha
vior
Ab
stra
ctC
on
tro
llee
po
rts
con
tro
lPo
rt:
Ctr
lPro
toco
l
Sen
der
Rec
eive
r.
. .
![Page 62: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/62.jpg)
62
Faile
d
Just
Crea
ted
Hard
war
eAu
dit
Get
tingD
ata
Read
yToG
o
Anal
ysin
gFa
ilure
Ope
ratio
nal
Expl
oitin
g Hi
erar
chic
al S
tate
s
Ab
stra
ctC
on
tro
llee
po
rts
con
tro
lPo
rt:
Ctr
lPro
toco
l
Sen
der
![Page 63: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/63.jpg)
63
The
Run-
Tim
e La
yerin
g Ar
chite
ctur
al P
atte
rn
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64
Sem
antic
s of
Lay
erin
g (1
)♦
A fu
ndam
enta
lly d
iffer
ent t
ype
of s
truct
ural
rela
tions
hip
Op
erat
ing
Sys
tem
AB
sen
der
op
erat
or
inte
rfac
e
�La
yerin
g is
diff
eren
t fro
m c
onta
inm
ent
�H
ighe
r-lay
ers
do n
ot c
onta
in lo
wer
laye
rs�
Form
ally
, the
low
er la
yers
“con
tain
” the
hig
her l
ayer
s (e
xist
ence
dep
ende
ncy)
but
they
do
not e
ncap
sula
te th
em
![Page 65: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/65.jpg)
65
Har
dwar
e
Lin
k
Net
wo
rk
Lev
el 4
Lev
el 5
Lev
el 6
Lev
el 7
Ope
ratin
gSy
stem
Sem
antic
s of
Lay
erin
g (2
)♦
In c
ompl
ex s
yste
ms,
laye
ring
is a
com
plex
m
ultid
imen
sion
al re
latio
nshi
p�
e.g.
, 7-la
yer m
odel
of O
pen
Syst
em In
terc
onne
ctio
n (O
SI)
![Page 66: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/66.jpg)
66
Inad
equa
te R
epre
sent
atio
ns o
f Lay
erin
g♦
Stai
rcas
e m
odel
�To
aste
r mod
el
Ope
ratin
g Sy
stem
Appl
icat
ion
Gen
eral
Ser
vice
s
Spec
ializ
ed S
ervi
ces
![Page 67: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/67.jpg)
67
Laye
r N
Laye
r N +
1
Mor
e on
the
OSI
Mod
el♦
Two
dist
inct
kin
ds o
f int
erfa
ces:
pee
r and
SAP
SAP
Laye
r N +
1
Publ
ic o
r Priv
ate
Inte
rface
?
Publ
ic In
terfa
ce
![Page 68: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/68.jpg)
68
CD
op
erat
or
inte
rfac
eA
B s
end
er
AB
Tim
ing
Ser
vice
Inte
rnal
im
plem
enta
tion
com
pone
nt
Exte
rnal
im
plem
enta
tion
com
pone
nt
Impl
emen
tatio
n Co
mpo
nent
s♦
Priv
ate
sub-
com
pone
nts
requ
ired
to re
aliz
e th
e fu
nctio
nalit
y of
fere
d by
com
pone
nt th
roug
h its
pub
lic
inte
rface
![Page 69: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/69.jpg)
69
Impl
emen
tatio
nIn
terfa
ce
Usag
eIn
terfa
ceInte
rface
Typ
es fo
r Lay
erin
g♦
Nee
d to
diff
eren
tiate
two
inte
rface
type
s:
�U
sage
inte
rface
: im
plem
enta
tion-
inde
pend
ent i
nter
face
th
roug
h w
hich
a c
ompo
nent
pro
vide
s its
ser
vice
s (fu
nctio
n an
d co
ntro
l)
�Im
plem
enta
tion
inte
rface
(ser
vice
acc
ess
poin
t):
impl
emen
tatio
n-sp
ecifi
c in
terfa
ce th
roug
h w
hich
a c
ompo
nent
ac
cess
es a
n ex
tern
al s
ervi
ce
♦Fr
ont-e
nd/b
ack-
end
view
s:
![Page 70: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/70.jpg)
70
Impl
emen
tatio
n In
terfa
ces
♦Im
plem
enta
tion
inte
rface
s ar
e pu
blic
inte
rface
s bu
t can
be
vie
wed
as
bein
g in
a d
iffer
ent “
plan
e” (d
imen
sion
) fro
m s
ervi
ce in
terfa
ces
CD
AB
sen
der
op
erat
or
inte
rfac
e
AB
Tim
ing
Ser
vice
90o
![Page 71: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/71.jpg)
71
Upp
erLa
yer
Inte
rnal
Co
mp
Serv
ice
acce
sspo
int
Tim
ing
Ser
vice
Mod
elin
g La
yers
with
Por
ts a
nd O
bjec
ts♦
Impl
emen
tatio
n in
terfa
ces
are
mod
eled
by
impl
emen
tatio
n en
d po
rts th
at c
an b
e co
nnec
ted
dire
ctly
to
ser
vice
por
ts o
f oth
er o
bjec
ts
![Page 72: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/72.jpg)
72
Sum
mar
y: A
rchi
tect
ural
Pat
tern
s♦
Des
ign
patte
rns
are
a cr
ucia
l too
l for
all
softw
are
desi
gn�
Des
ign
sim
plifi
catio
n�
Des
ign
relia
bilit
y
�C
omm
unic
atio
n ve
hicl
e
♦Am
ong
the
mos
t im
porta
nt a
re a
rchi
tect
ural
pat
tern
s♦
Two
extre
mel
y us
eful
top-
leve
l arc
hite
ctur
al p
atte
rns:
�R
ecur
sive
con
trol p
atte
rn (f
or re
al-ti
me
syst
ems)
�La
yerin
g
♦Th
ese
patte
rns
can
be s
peci
fied
dire
ctly
in U
ML
![Page 73: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/73.jpg)
73
Conc
lusi
on a
nd S
umm
ary
♦W
e ha
ve c
ross
ed th
e th
resh
old
of a
new
gen
erat
ion
of s
oftw
are
spec
ifica
tion
tech
niqu
es: m
odel
-driv
en d
evel
opm
ent
�Bo
th la
ngua
ges
and
tool
s ha
ve re
ache
d in
dust
rial s
treng
th m
atur
ity�
Man
y la
rge
syst
ems
have
bee
n pr
oduc
ed u
sing
MD
D (>
4M
LoC
)
♦Th
ese
tech
niqu
es a
re b
ased
on
�Ex
tens
ive
use
of m
odel
s an
d m
odel
ing
�Ex
tens
ive
use
of c
ompu
ter-b
ased
aut
omat
ion,
par
ticul
arly
for
impl
emen
tatio
n
♦Th
e ab
ility
to s
peci
fy a
nd e
nfor
ce s
oftw
are
arch
itect
ures
is o
neof
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e be
nefit
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MD
D♦
We
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crib
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e co
ncep
ts th
at a
re s
uita
ble
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ural
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odel
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and
dem
onst
rate
d th
eir a
pplic
atio
n to
exp
ress
ing
usef
ulde
sign
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tern
s fo
r lar
ge re
al-ti
me
and
embe
dded
app
licat
ions
![Page 74: Modeling Real-Time System Architectures Bran Selic ...Modeling Real-Time System Architectures Bran Selic Principal Engineer IBM Software Group – Rational Software bselic@ca.ibm.com](https://reader036.vdocuments.net/reader036/viewer/2022071414/610e28ae0298a950f7473cad/html5/thumbnails/74.jpg)
74
Bibl
iogr
aphy
♦Ba
ss, L
., P.
Cle
men
ts, a
nd R
.Kaz
man
, Sof
twar
e
Arch
itect
ure
in P
ract
ice,
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son-
Wes
ley,
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♦B.
Sel
ic, J
.Rum
baug
h, U
sing
UM
L to
Mod
el C
ompl
ex
Rea
l-Tim
e Sy
stem
s, R
atio
nalw
hite
pape
r: (h
ttp://
ww
w.ra
tiona
l.com
/site
wid
e/su
ppor
t/whi
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pers
/dyn
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♦B.
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ime
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