Published in IET Renewable Power GenerationReceived on 15th November 2013Revised on 14th March 2014Accepted on 6th May 2014doi: 10.1049/iet-rpg.2013.0365ISSN 1752-1416Modelling and analysis of modular multilevelconverter for solar photovoltaic applications toimprove power qualityAlbert Alexander1, Manigandan Thathan21Department of EEE, Kongu Engineering College, Perundurai, Tamil Nadu 638 052, India2Department of EEE, P.A. College of Engineering and Technology, Pollachi, Tamil Nadu 642 002, IndiaE-mail: ootyalex@gmail.comAbstract:Thedesignofcontrol circuit forasolarfedcascadedmultilevel invertertoreducethenumberofsemiconductorswitches is presented in this study. The design includes binary, trinary and modied multilevel connection (MMC)-basedtopologiessuitableforvaryinginputsourcesfromsolarphotovoltaics(PV).Inbinarymode,2Ns +11outputvoltagelevelsare obtainedwhere Nsis the number of individual inverters. This is achievedbydigital logic functions whichincludescounters, ip-opsandlogicgates. Intrinarymode, 3Nslevelsareachievedbycorrespondinglook-uptable. MMCintendsdesigninbothcontrolandpower circuits toprovidecorrespondingoutputvoltagelevelsby appropriateswitchingsequences.Hence toobtaina 15-level inverter, the conventional methodrequires 28switches andinbinarymode 12switches areneeded. In trinary mode with the same 12 switches, 27 levels can be obtained whereas in MMConly 7 switches areemployedtoachieve15levels. Theadvantageof these threedesigns is inthereductionof total harmonic distortionbyincreasing the levels. Simulations are carried out in MATLAB/Simulink and comparisons were made. All the three topologiesare experimentally investigated for a 3 kWp solar PV plant and power quality indices were measured.1 IntroductionMultilevel inverterprovidesasuitablesolutionformediumand high power systems to synthesise a output voltagewhichallows a reductionof harmonic content involtageand current waveforms. Multilevel refers to the multipleconnections of individual inverters termed as stages toprovidetheoutputvoltagewithrequired levels.Increasingthe number of levels will result in the reduction ofharmonic distortion. The three topologies such as yingcapacitor (FC), neutral point clamped(NPC) andcascadedmultilevel inverters (CMLIs) are preferred for variousapplications depending upon its structure and modulationalgorithms. Among the three topologies, CMLI is highlypreferred for the interconnection of renewable energysystems because of the advantages such as absence ofvoltageunbalanceproblem,possibleeliminationofDCDCboost converter, adaptive at lowswitchingfrequencyandabsence of clamping capacitors and diodes.Solar photovoltaic (PV) fed CMLI is dealt in variousliteratures, but it intends for lowvoltage and lowlevelcongurations. Pulse-width modulation (PWM) techniquefor a 5-level CMLI [12] and 7-level CMLI [3] for PVsystem is addressed which requires boost converter,auxiliarycircuitryandmultiplereferencesignals for pulsegeneration. A5-level current CMLIforasinglephasegridconnectedPVsystemgivenin[4] requirestheredesignofLClter to reduce the inductive and resistive losses forhigher power levels. The three control loop maximumpower point (MPP) for a 5-level inverter proposedin[5]employs anoutput transformer betweeninverter andgrid.Inspite of reducing the harmonic distortions whileincreasing the levels, CMLI requires more number ofsemiconductor switches which has to be reduced forminimising switching loss, cost, complexity and space.Series connectionof multilevel inverters introducedin[6]restricts its useinhighpower applications becauseof thenecessity of changing the voltage polarity in every halfcycle and also the switches with different ratings arerequired. A detailed look-up table is required for themethodproposedin[7]whichconsistsofseriesconnectionof a high-voltage NPC and a low-voltage conventionalinverter. A 5-level inverter with four DC sourcescomprisingtwonumbersof2-level and3-level invertersisproposedin[8]. The drawbackof this method is that inconventional inverters upto9level canbegeneratedwiththesamenumberofpowersupplies. Bidirectional switcheswith voltage and current blocking capability for thereduction of switches is proposed in [911] where eachbidirectional switch requires a separate gate drive circuitwhich increases the power loss.In this paper, a digital logic control circuit is proposed for asolar fed CMLI to achieve higher levels with reduced numberof switches without the requirement of bidirectional switches,lter components, detailed look-up tables and outputtransformers. Thetechniquesinclude binary, trinaryandwww.ietdl.org78& The Institution of Engineering and Technology 2015IET Renew. Power Gener., 2015, Vol. 9, Iss. 1, pp. 7888doi: 10.1049/iet-rpg.2013.0365modied multilevel connections (MMCs) to achieve 15level and 27 level, respectively. Fig. 1 shows the three stageCMLI power circuit usedtoachieve15level bybinarymode using digital switching technique comprises ofcounters and logic functions. The same power circuit isusedtoachieve27levelby trinarymodeusingembeddedcontroller. In certain literature, voltage balancing, ultracapacitors, PWMswitchingandtransformers are requiredwhich will be the cause for the increase in cost andmanufacturing problems thereby not desirable for motordriveapplications[1214].InMMC,a15levelisachievedwiththesinglestageinverterbyadditionofinput voltagesusing the embedded controller based on the proposedswitchingsequence. Thecomparisonofthreemethodswiththe existing techniques are analysed and experimentallyveried.This paper is organised as follows: Section 2 presents theproposed logic circuit design and Section 3 exhibits thesimulation results and comparative analysis. Section 4presents the experimental results andSection5gives thenal conclusions.2 Switching strategiesInconventional approach, PWMtechniquesareusedbythecomparisonof reference andcarrier signals toprovide therequired gating signals for the inverter switches. Thenumberof output voltage levels obtained from this approach is givenin the following equationm = 2Ns+1 (1)where mdenotes the output voltage levels andNsis theindividual inverter stages. The number of switches (l )required to achieve m levels is given in the following equationl = 2(m 1) (2)For theimplementationof 15-level CMLI, thenumber ofswitches required is 28 with seven individual inverterstages. Inadditiontothe28switches, 182clampingdiodesincaseofNPCordiodeclampedmultilevelinverterand91balancingcapacitors incaseof FCtypemultilevel inverteralong with 14 DC bus capacitors are needed to achieve15-level output. The proposed paper deals with the followingtopologies for the reduction of switches. Increasing thenumber of levels will subsequently reduce the harmonicdistortion which in turn improves the power quality.2.1 Binary modeIn binary mode operation, the number of levels which can beachievedforthegivenset ofinverterstagesisgiveninthefollowing equationm = 2Ns+11 (3)Hence to obtain a 15-level output, only three inverter stagesarerequiredwith12switches. Toachievethis, aswitchingcircuit withthecontrol strategyincorporatingdigital logicfunctionsisimplementedforthesolarfedCMLI.ThethreeinverterstagesarefedfromvaryingsolarPVinput source.Theinput voltagesarescaledtothepowerof2inordertoachieve the outputvoltage in therange of 2Nswhichcan bemadebypossiblebybinarycounters. Anincremental anddescended operator is required to achieve the condition2Ns + 11 at the output level. For the circuit shown inFig. 1, duringthepositivehalf cycletheswitches S1, S5Fig. 1 Three stage inverter power circuitwww.ietdl.orgIET Renew. Power Gener., 2015, Vol. 9, Iss. 1, pp. 7888doi: 10.1049/iet-rpg.2013.036579& The Institution of Engineering and Technology 2015and S9 are in ON condition and during negative half cycle S3,S7 and S11 are in ON condition. The conduction period foreachhalf cycleis xedat 10 mswhichwill determinetheoutput frequency of the inverter as 50 Hz.The sequence shown in Table 1 gives the switching patterntoattainthedesiredvoltagelevels. INV1, INV2andINV3specify the three inverter stages and Vois the outputvoltage. + and denote the ON and OFF conditionof theswitches. Thesequence + to + + + inthepositivehalf cycleshowstheconductionperiodisfrom0to 90and + + + to + from90to 180. Thesimilarconditionholdsfornegativehalfcyclefrom180to270and270to360. Theswitchespresent intheCMLIare intended to operate based on the switching sequenceenlisted in the truth table.Fig. 2 shows the block diagram for the implementation of thebinary mode. The three stage inverter requires Ns+ 2 (3 + 2 = 5)bit counterswhichactsasanupcounter. Thecombinationallogiccircuitmakesthethreebits(Q1,Q2andQ3)tomoveinforwarddirection duringtherst halfofthepositive halfcycleandsimilarlyinreversedirectionduringsecondhalfof the positive half cycle. The same condition is repeated inbothhalf of thenegativehalf cycle. Thebits(Q1, Q2andQ3) are modied by Q4 and Q4, where Q4 is used tocontrol theincremental operationintherst halfofpositiveor negative half cycles andQ4is usedfor the decrementoperation in the latter half of positive or negative half cycles.ThepulseseparationblockcomprisesofbitsQ5andQ5toseparate the pulses requires for bothpositive andnegativehalf cycles and also controlling other bits in the circuit.Any number of levels can be achieved with thismethodologybyonlyaddingthecountersasaccordancetothe number of inverter stages and control logic functions.2.2 Trinary modeIn trinary mode operation, the number of levels which can beachievedforthegivenset ofinverterstagesisgiveninthefollowing equationm = 3Ns(4)With the three inverter stages 27 levels can be obtained withonly 12 switches. To achieve this, rather than a digital logicfunctions usedinbinarymode, anembeddedcontroller isproposedwithout the utlilisationof transformers [15] andcomplicated algorithms [16]. In this approach, the circuitshown in Fig. 1 is considered whose input voltages arescaledtothepower of 3. Table2illustratestheswitchingsequencefortheswitchesS1S12toobtain13-leveloutputduringthepositivehalfcycleandinnegativehalfcyclethesamesequenceisrotatedbyanangleof90toachievetheremaining13level. Byincludinglevel zero, thedesired27levels will be achieved.2.3 Modied multilevel connectionsIntheabovetwoapproaches,themodicationisrealisedincontrol circuit of CMLI toachieve15and27levels withthreeinverter stages. Inthis approach, themodicationismade inbothcontrol circuit andpredominatelyinpowercircuit toobtain15levelswithonlysevenswitches. Fig. 3shows the circuit diagramof MMCapproach where theinput scalingisnot mandatory. Theadditionof diodeandTable 2 ON/OFF states for three stage 27 levelLevel S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S121 1 0 0 1 1 1 0 0 1 1 0 02 0 1 1 0 1 0 0 1 1 1 0 03 1 1 0 0 1 0 0 1 1 1 0 04 1 0 0 1 1 0 0 1 1 1 0 05 0 1 1 0 0 1 1 0 1 0 0 16 1 1 0 0 0 1 1 0 1 0 0 17 1 0 0 1 0 1 1 0 1 0 0 18 0 1 1 0 1 1 0 0 1 0 0 19 1 1 0 0 1 1 0 0 1 0 0 110 1 0 0 1 1 1 0 0 1 0 0 111 0 1 1 0 1 0 0 1 1 0 0 112 1 1 0 0 1 0 0 1 1 0 0 113 1 0 0 1 1 0 0 1 1 0 0 1Fig. 2 Block diagram of the proposed logic circuitTable 1 ON/OFF states for three stage 15-level inverterPositive half cycle (10 ms) Negative half cycle (10 ms)INV1 INV2 INV3 VoINV1 INV2 INV3 Vo + 48 + 48 + 96 + 96 + + 144 + + 144+ 192 + 192+ + 240 + + 240+ + 288 + + 288+ + + 336 + + + 336+ + + 336 + + + 336+ + 288 + + 288+ + 240 + + 240+ 192 + 192 + + 144 + + 144 + 96 + 96 + 48 + 48www.ietdl.org80& The Institution of Engineering and Technology 2015IET Renew. Power Gener., 2015, Vol. 9, Iss. 1, pp. 7888doi: 10.1049/iet-rpg.2013.0365capacitor(1 nF)istonormalisetheoutput withinthegiveninterval. Table3showstheswitchingsequencetoachievethe15-level output. Basedonthetable, theinvertercircuit(T1T4) isinONconditionat all thelevels, but theinputswitches (S1S3) are controlled in such a way that to obtainthe required output voltage.Let the PV array inputs be V1V3. During the level 1, V1aloneisgivenasinput totheinverterandV2, V3inOFFcondition. Similarlythe15level isachievedbycontrollingtheON/OFFstatusof theinput voltages. Theremaining7level from the truth table will be obtained by controlling thesequence in reverse direction.The comparisonof switches requiredwithall the threemethods proposed is given in Table 4.3 Simulation and results3.1 Modelling of solar PV panelThe simulation and the corresponding harmonics analysis forall the three topologies are carried out in MATLAB/Simulink.The model of solar PV panel is required which serves as theinput for the proposed inverter. In most of the literature basedonsolar PVfedinverter, theinput is givenfromtheDCsupplyandanalysisweremade[17] andalsomost of thesolar PVmodels proposed tends to the estimation of itscharacteristics andMPPtracking[1820]. HenceamodelsuitableforCMLI-basedapplicationisrequiredwhichalsoconsidersthevariationsinirradianceandtemperature[21].Asolar PVpanel is modelled by the interconnection ofsolar cells in series and parallel to achieve the requiredratingof 48 V, 7 A. Eachsolar cell of rating(0.5 V, 7 A)with 96 numbers is connected in series at standard testconditionsof1000 W/mm2and25C. Withtheratingofthepanel giveninTable6, themodellingis madeandP Vand I Vcharacteristics are plotted as shown in Fig. 4.Table 4 Comparison of switchesNo. of stages No. of switches No. of levelsConventional Binary Trinary MMC1 4 3 3 3 15 achieved with only 7 switches2 8 5 7 93 12 7 15 274 16 9 31 815 20 11 63 2436 24 13 127 7297 28 15 255 2187Table 5 Comparison of THD for the solar PV fed CMLIStages Voltage THD (%) Current THD (%)PWM Binary Trinary MMC PWM Binary Trinary MMC1 52.66 42.09 5.55 26.34 26.95 8.142 37.77 23.56 20.43 26.49 3 26.51 16.22 10.70 13.70 20.08 7.71 4 17.15 15.48 11.37 6.92 20.94 8.66 5 11.53 12.93 11.77 2.57 21.64 9.00 6 14.36 12.63 11.76 5.16 22.81 11.96 7 15.25 12.37 12.02 6.48 21.60 11.95 Table 3 Switching sequence for 15-level inverter with MMCLevel S1 S2 S3 T1 T2 T3 T4 Vo0 0 0 0 0 0 0 0 01 1 0 0 1 0 0 1 482 0 1 0 1 0 0 1 963 1 1 0 1 0 0 1 1444 0 0 1 1 0 0 1 1925 1 0 1 1 0 0 1 2406 0 1 1 1 0 0 1 2887 1 1 1 1 0 0 1 336Fig. 3 Single stage 15-level inverter power circuitwww.ietdl.orgIET Renew. Power Gener., 2015, Vol. 9, Iss. 1, pp. 7888doi: 10.1049/iet-rpg.2013.036581& The Institution of Engineering and Technology 2015The equations corresponding to the solar cell model is givenin the following equationsI = IphK1K2(V +1Rs)/Rp(5)whereK1 = Ise(V+1Rs)/(NVt)1 andK2 = Is2e(V+1Rs)/(N2Vt)1 (6)whereIsandIs2arethediodesaturationcurrents, Vtisthethermal voltage, N and N2 are the diode emissioncoefcients andIphisthesolar generatedcurrent giveninthe following equationIph = Ir(Iph0/Ir0) (7)where Iph0is the measured solar generated current forirradianceIr0. Inaddition, thechangeintheoutputvoltagebasedonpartial shadedconditionof thesolar PVis alsoconsideredfora15-level CMLIwhichisshowninFig. 5.According to this gure, based on the variations in theirradianceandtemperatureat solar PV, theoutput voltageoftheinverterobtainedgetsvariedbut thelevel maintainsthesame. Thereal timemonitoringfor thesolar PVwithrespect toits radiationis analysedfor all themonths andbasedonitsinferencethemodellingismadeafterknowingthe variation of irradiance for the given region.3.2 Binary modeTheinput tothe three inverter stagesareto bescaledin thepower of 2 as 48, 96 and 192 Vto achieve the outputvoltage of 326 Vp. Fig. 6shows the proposedsimulationblock of the control circuit which consists of counters,combination circuit and pulse separation circuit. Theclock signal is given as the input to the ve bitasynchronous counter for the movement of bits suitablefor positive and negative half cycles as according to thetruthtable. At logicfunctions, thepulsesareseparatedandgiventothe inverter switches. Fig. 7shows the 15-leveloutput voltage waveform achieved from three stageinverteranditscorrespondingFFT(fast Fouriertransform)analysis.3.3 Trinary modeTheinput tothe three inverter stagesareto bescaledin thepower of 3 as 24, 72 and 216 Vto achieve the outputvoltage of 312 Vp. A programmable pulse generator is usedwhichwill receivetheswitchingsequenceasper thetruthtablefromembeddedcontroller andfedit totheswitchesthrough repeating sequence block. Fig. 8 shows theoutput voltage waveformand its corresponding harmonicspectrum.3.4 Modied multilevel connectionInthis method, theembedded-basedcontroller is usedforproviding the gating signals based on the switchingFig. 4 P V and I V characteristicsa Powervoltageb Currentvoltage characteristics of the solar arrayFig. 5 Solar PV with partial shaded condition for a 15-level CMLIa Variation of panel irradianceb 15-level output voltage waveformwww.ietdl.org82& The Institution of Engineering and Technology 2015IET Renew. Power Gener., 2015, Vol. 9, Iss. 1, pp. 7888doi: 10.1049/iet-rpg.2013.0365Fig. 6 Digital switching circuit for 15-level CMLIFig. 7 15-level output voltage waveform achieved from three stage invertera 15-level output voltage waveformb FFT analysis for three stage 15-level CMLIwww.ietdl.orgIET Renew. Power Gener., 2015, Vol. 9, Iss. 1, pp. 7888doi: 10.1049/iet-rpg.2013.036583& The Institution of Engineering and Technology 2015sequenceaccordingtotheadditionof input voltages. Theinput voltages are 48, 96 and 192 V. Fig. 9 shows theoutput voltage waveformand its corresponding harmonicspectrum.Table 5 shows the comparison of power qualityimprovement pertaining to the reduction of voltage totalharmonic distortion (THD). As current THD is alsoequallyimportant, its values are noted for RLload (L =100 mH, R = 100 ) [22]. All theworks are implementedwith the input solar PV panel and output voltagerequirement of 230 Vrms with appropriate scaling ofinputvoltageandsettinginverteroutput frequency = 50 Hz.In developing PWM-based technique, unipolarswitching with single carrier is used with switchingfrequency of 1 kHz.4 Experimental resultsThe three topologies are implemented separately and thepower quality analyses were made. The design was made toprovide 230 Vrms, 50 Hz AC supply as much of thedomesticloadsoperatesinthissystem. A3 kWpsolar PVplant showninFig. 10isinstalledwhichcomprisesof 28panels of each 115 Wp. The specication of the entirehardwareis listedinTable6. Inbinary mode theinputvoltage are in the range of 48, 96 and 192 V (48 V scaledinpowerof2), respectively. Thisisachievedbytheseriesconnectionof 12 Vbatteryinfour numbers. Hence threeseparateinputsourcesaredesignedtoachievetheoutputof336 Vp (peak voltage). The power circuit of 15-level CMLIconsists of 12 number of MOSFET.Fig. 8 Output voltage waveform and its corresponding harmonic spectruma 27-level output voltage waveformb FFT analysis for three stage 27-level CMLIwww.ietdl.org84& The Institution of Engineering and Technology 2015IET Renew. Power Gener., 2015, Vol. 9, Iss. 1, pp. 7888doi: 10.1049/iet-rpg.2013.0365Fig. 9 Output voltage waveform and its corresponding harmonic spectruma 15-level output voltage waveformb FFT analysis for one stage 15-level CMLIFig. 10 3 kWp solar plantwww.ietdl.orgIET Renew. Power Gener., 2015, Vol. 9, Iss. 1, pp. 7888doi: 10.1049/iet-rpg.2013.036585& The Institution of Engineering and Technology 2015The control circuit consists of CD4520 counters, timer IC555, buffer ICandlogic gates toperformthe actions ofcombinational and pulse separation circuit. The entirehardwaresetupis showninFig. 11a. Theinput fromthesolar PVis giventothebatterythroughchargecontroller(CC).Inputtotheinverterisdriventhroughthebattery.Asthe proposed technique is application specic suitable torural areas, astandalonePVsystemwithbatterystorageistaken into consideration. This method can also beimplementedwithout thebatteryasgridconnectedsystemwherethesameoutput voltagewaveformcanbeachievedforthegiveninverterstages. Thecontrol terminal includestheseparateinput pairs alongwiththeswitchgear devicesfortheinput sideprotection. Theoutput voltagewaveformforathreestage15-levelinverterisshowninFig. 12aandthecorrespondingharmonicanalysismadeinWT3000isshowninFig. 12b. Theharmoniccontentismeasuredupto20th order in both simulation and hardware. The THDobtained in this mode is 15.4%.The circuit showninFig. 11ais alsousedtoachieve27-level output in trinary mode. Here the input to theinverterisintherangeof24,72and216 V(24 V scaledinthepowerof3). Thecontrol circuit comprisesofsinglechip controller embedded with the switching sequencelisted in Table 2. The output voltage waveformof threestage27-level CMLIintrinarymodeisshowninFig. 13aanditsharmonicanalysisisshowninFig. 13b. TheTHDobtained through trinary mode is 13.68%.InMMC, onlyoneinverter showninFig. 11bis usedwheretheinput totheinverter areintherangeof 48, 96and192 V, respectively. Across theeachinput side, threeswitches are connected whose switching action is controlledand monitored by the single chip controller. The addition ofinputvoltageismadeappropriatelybyturningtheswitchesS1S2asper thesequence. TheswitchesT1T4formthefull bridgeinvertercircuitry. Theoutput voltagewaveformof a one stage 15 level is shown in Fig. 14a and thecorrespondingharmonicanalysisisgiveninFig. 14b. TheTHD obtained in this mode is 5.89%.Basedontheresults, it is foundthat byadoptingthesetopologies increased level CMLI can be obtained withreducednumber ofsemiconductorswitches.Inaddition,theharmonic distortions are summarily reduced in bothsimulation and hardware implementations. Earlier works arereportedwiththeimplementationat lowpowerwithVpof150[6], 15[22], 60[10], 10[18] and70 V[23] whereasthe proposed method implemented with 336 Vp. Inaddition, to achieve the 15 level output the number ofswitchesrequiredinexistingworksare19[7], 14[24], 16[25] and 36 [26] whereas only 12 or 7 switches are requiredintheproposedmethodology. For27-levelmethodologyinexistingworksrequires transformersattheinputandoutputendof theinverter andimplementedwithVpof 150and104 V[1213] but theproposedmethoddoesnot requiresTable 6 Hardware design SpecificationsSolar panel descriptionsmodel Solectric 9000Pmpp115 Wpvoc, isc 21.2 V, 7.4 Avpm, ipm 16.5 V, 6.95 Amax system voltage 540 Vtolerance at peak power 5%no. of panels 28total power 3220 WpCCsmake SukaamVI rating 48 V, 10 Ano. of CC 7Battery bankmake EXIDE 6LMS100 Lvoltage, ampere hour 12 V, 100 Ahno. of batteries 28Hardware descriptionswitch MOSFET IRF840no. of switches 12 (12, 27 level) and 7 (15 level)controller ATMEGA 16AVRMeasuring instrumentsoscilloscope Tektronixpower quality analyser WT 3000 make: YokogawaFig. 11 Experimental setup fora Three stage 15-level CMLIb One stage 15-level CMLIwww.ietdl.org86& The Institution of Engineering and Technology 2015IET Renew. Power Gener., 2015, Vol. 9, Iss. 1, pp. 7888doi: 10.1049/iet-rpg.2013.0365Fig. 12 Output voltage waveform for a three stage 15-level invertera 15-level output voltage waveformb Harmonic analysis using WT 3000Fig. 13 Output voltage waveform of three stage 27-level invertera 27-level output voltage waveformb Harmonic analysis using WT 3000Fig. 14 Output voltage waveform of a single stage 15 level invertera 15-level output voltage waveformb Harmonic analysis using WT 3000www.ietdl.orgIET Renew. Power Gener., 2015, Vol. 9, Iss. 1, pp. 7888doi: 10.1049/iet-rpg.2013.036587& The Institution of Engineering and Technology 2015transformersandalsoimplementedfor312 Vp. Duringthepartial shadedcondition, therequiredvoltagelevelswillbeachieved withquietreduction involtage peakwhichinturnis compensated by a battery storage system.5 ConclusionsThepowerqualityimprovement forasolarfedCMLIwithreducednumber of semiconductor switches is investigatedinthispaper.Therequired15-leveloutputisachievedwithonly12switchesinbinarymodeand7switchesinMMCmode. In addition, 27-level output is obtained with 12switches through trinarymode. The mathematical modelforsolarPViscarriedout whichisconsideredastheinput tothe inverter stages. Adetailedsimulationstudyis carriedoutforvariouslevelsandcomparisonhasbeenmade. A3kWpsolar PVfedCMLI isimplementedfor all thethreetopologiesandharmonicsanalysiswasmade. Basedontheobservations, the proposed method provides the multipleadvantages whichincludereducedTHD, less cost, simpledesign, minimum computational complexity and theabsenceof transformers, boost converters, detailedlook-uptableand lter circuit. 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